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Threads 301 to 330 of 22051

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Amp ADC interfacing using VHDL for Spartan-3A

    Started by NJ176, 31st July 2017 09:44
    • Replies: 4
    • Views: 946
    4th August 2017, 17:49 Go to last post
  2. [SOLVED] xilinx timing analyze using modelsim SE

    Started by tanish, 3rd August 2017 17:53
    • Replies: 1
    • Views: 689
    3rd August 2017, 20:53 Go to last post
    • Replies: 2
    • Views: 570
    3rd August 2017, 16:31 Go to last post
  3. Verilog Assignment code

    Started by hareeshP, 1st August 2017 10:23
    • Replies: 4
    • Views: 931
    2nd August 2017, 06:45 Go to last post
  4. VHDL Register transferring.

    Started by hareeshP, 19th July 2017 13:28
    • Replies: 15
    • Views: 1,264
    2nd August 2017, 06:15 Go to last post
  5. jtag uart speed problem

    Started by dipin, 1st August 2017 12:25
    • Replies: 1
    • Views: 681
    1st August 2017, 16:43 Go to last post
  6. FPGA interfacing ADC with sampling rate >150 Msps

    Started by sherif123, 31st July 2017 08:53
    • Replies: 4
    • Views: 724
    31st July 2017, 15:47 Go to last post
  7. [SOLVED] VHDL Equivalent of Verilog Code

    Started by hareeshP, 31st July 2017 12:44
    • Replies: 1
    • Views: 498
    31st July 2017, 13:59 Go to last post
  8. Need help for write code for recurrent block

    Started by Adnan86, 27th July 2017 21:24
    • Replies: 10
    • Views: 1,413
    30th July 2017, 17:15 Go to last post
    • Replies: 3
    • Views: 738
    29th July 2017, 17:32 Go to last post
  9. Closed: how to find area, latency, throughput, power in my design?

    Started by Reeyam, 25th June 2017 01:06
    • Replies: 19
    • Views: 1,883
    29th July 2017, 08:52 Go to last post
  10. Basic theory needed to learn FPGA

    Started by FootTea, 28th July 2017 08:52
    • Replies: 4
    • Views: 734
    29th July 2017, 00:47 Go to last post
  11. Closed: [moved] Input selector from two 8-bit digital port

    Started by jackobian, 3rd June 2017 12:39
    • Replies: 6
    • Views: 1,098
    28th July 2017, 07:24 Go to last post
  12. how to use generate&for to do "x = x + a(i)"

    Started by bravoegg, 26th July 2017 15:58
    • Replies: 10
    • Views: 793
    27th July 2017, 16:34 Go to last post
  13. LDPC: Bit-flipping decoding [Hard decision]

    Started by AbinayaSivam, 27th July 2017 08:30
    • Replies: 0
    • Views: 502
    27th July 2017, 08:30 Go to last post
  14. [SOLVED] qsys jtag_uart doubt

    Started by dipin, 25th July 2017 07:03
    • Replies: 7
    • Views: 870
    27th July 2017, 06:35 Go to last post
  15. Signal declaration based on a generic + VHDL

    Started by dpaul, 26th July 2017 13:20
    • Replies: 2
    • Views: 603
    26th July 2017, 14:00 Go to last post
    • Replies: 2
    • Views: 525
    26th July 2017, 13:07 Go to last post
    • Replies: 0
    • Views: 348
    26th July 2017, 09:14 Go to last post
  16. Booting time of MAX 10 FPGA

    Started by hareeshP, 25th July 2017 08:10
    • Replies: 1
    • Views: 549
    25th July 2017, 19:09 Go to last post
  17. verilog implementation of a viterbi decoder

    Started by tanish, 24th July 2017 09:18
    • Replies: 2
    • Views: 590
    25th July 2017, 04:35 Go to last post
  18. VHDL equivalent of Verilog code

    Started by hareeshP, 24th July 2017 07:39
    • Replies: 13
    • Views: 994
    24th July 2017, 23:18 Go to last post
  19. [SOLVED] Is there a way to probe LVDS serializer output

    Started by nsgil85, 23rd July 2017 09:53
    • Replies: 6
    • Views: 1,000
    24th July 2017, 16:26 Go to last post
  20. 74HC595 implementation in VHDL - URGENT

    Started by Sean_Goddard, 22nd July 2017 21:45
    • Replies: 1
    • Views: 561
    23rd July 2017, 05:16 Go to last post
  21. Closed: Is this FPGA board suitable for learning purposes ??

    Started by arbj2, 22nd July 2017 10:00
    • Replies: 3
    • Views: 793
    23rd July 2017, 01:55 Go to last post
  22. [SOLVED]Closed: Help for declaring an array in system verilog in Modelsim 10.1b

    Started by manik045, 22nd July 2017 09:39
    • Replies: 4
    • Views: 543
    22nd July 2017, 20:10 Go to last post
  23. Closed: DDR2 interfacing Virtex-5 with MIG 3.6

    Started by aminpix, 22nd July 2017 00:13
    • Replies: 2
    • Views: 517
    22nd July 2017, 20:04 Go to last post
  24. Closed: Basic questions regarding NIOS

    Started by mahmood.n, 20th July 2017 10:16
    • Replies: 4
    • Views: 580
    22nd July 2017, 07:50 Go to last post
  25. Closed: how to use spi interface with custom ip

    Started by abhishek7, 18th July 2017 09:43
    • Replies: 2
    • Views: 484
    21st July 2017, 23:57 Go to last post