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Threads 301 to 330 of 22207

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Packet over 10Gig ethernet Interface

    Started by beginner_EDA, 30th October 2017 14:00
    • Replies: 0
    • Views: 317
    30th October 2017, 14:00 Go to last post
    • Replies: 2
    • Views: 830
    30th October 2017, 10:53 Go to last post
  2. VHDL procedure that simulate the lock function a PLL

    Started by shaiko, 27th October 2017 18:22
    • Replies: 12
    • Views: 1,750
    29th October 2017, 23:37 Go to last post
  3. kcounter loop filter

    Started by manishpatkar, 29th October 2017 12:30
    • Replies: 8
    • Views: 793
    29th October 2017, 17:26 Go to last post
  4. Nested clock in vhdl

    Started by ananthan95, 19th October 2017 12:58
    • Replies: 17
    • Views: 1,627
    29th October 2017, 14:05 Go to last post
    • Replies: 1
    • Views: 431
    27th October 2017, 16:15 Go to last post
  5. Closed: Multiplexer in VHDL with a 2D array and for loop

    Started by moonshine8995, 27th October 2017 12:37
    • Replies: 3
    • Views: 465
    27th October 2017, 15:19 Go to last post
  6. Closed: 10 Gig ethernet Packet capture tool

    Started by beginner_EDA, 27th October 2017 12:03
    • Replies: 1
    • Views: 408
    27th October 2017, 12:48 Go to last post
  7. Closed: Convert std_logic_vector to integer

    Started by moonshine8995, 26th October 2017 13:05
    • Replies: 7
    • Views: 636
    27th October 2017, 12:11 Go to last post
  8. Closed: Problem to understand internal architecture of JTAG

    Started by sandy2811, 25th October 2017 05:43
    • Replies: 7
    • Views: 1,107
    27th October 2017, 11:02 Go to last post
  9. Closed: Function 'test' could not be resolved in HLS

    Started by mouhamedmb, 27th October 2017 10:23
    • Replies: 0
    • Views: 396
    27th October 2017, 10:23 Go to last post
  10. [SOLVED]Closed: System Verilog error in modelsim with enum types.

    Started by vipinlal, 26th October 2017 15:06
    • Replies: 3
    • Views: 473
    26th October 2017, 16:52 Go to last post
  11. Closed: Error while running simulation in the vhdl code using when else

    Started by manishpatkar, 26th October 2017 09:13
    • Replies: 1
    • Views: 1,144
    26th October 2017, 09:28 Go to last post
  12. [SOLVED]Closed: Need adpll , vhdl basics sources

    Started by manishpatkar, 25th October 2017 17:39
    • Replies: 1
    • Views: 476
    25th October 2017, 18:45 Go to last post
  13. Closed: Verilog code for mod 3 4 bit asynchronous counter

    Started by sugubai, 25th October 2017 11:52
    • Replies: 5
    • Views: 711
    25th October 2017, 16:23 Go to last post
  14. Closed: Cyclone 5 sockit usb_uart port

    Started by dipin, 30th September 2017 10:47
    • Replies: 7
    • Views: 1,002
    25th October 2017, 12:10 Go to last post
  15. Closed: [moved] How to clear Verilog HDL error

    Started by sugubai, 22nd October 2017 05:57
    • Replies: 7
    • Views: 1,128
    25th October 2017, 11:55 Go to last post
    • Replies: 0
    • Views: 327
    24th October 2017, 23:08 Go to last post
  16. Closed: How to update flash with user logic?

    Started by bravoegg, 24th October 2017 13:27
    • Replies: 4
    • Views: 433
    24th October 2017, 17:11 Go to last post
  17. Closed: Xilinx usb II platform cable driver centos 7.3/vivado 16.3

    Started by beginner_EDA, 20th October 2017 10:13
    • Replies: 6
    • Views: 946
    24th October 2017, 16:14 Go to last post
  18. Closed: How to use T flip flops in vdhl to simulate LED's blinking on/off

    Started by NickDefick, 23rd October 2017 21:16
    • Replies: 2
    • Views: 491
    24th October 2017, 14:42 Go to last post
  19. Closed: Waveform of verilog "reg" inside a task in Vivado

    Started by samg, 24th October 2017 11:00
    • Replies: 0
    • Views: 284
    24th October 2017, 11:00 Go to last post
  20. [SOLVED]Closed: Register space addressing in Xilinx JESD204

    Started by samg, 24th October 2017 05:22
    • Replies: 1
    • Views: 456
    24th October 2017, 08:41 Go to last post
  21. [SOLVED]Closed: Using BRAM by infering and by using IP

    Started by rafimiet, 23rd October 2017 08:05
    • Replies: 10
    • Views: 748
    23rd October 2017, 22:19 Go to last post
  22. Closed: MAX II CPLD performance

    Started by hareeshP, 23rd October 2017 11:09
    • Replies: 1
    • Views: 375
    23rd October 2017, 11:33 Go to last post
  23. [SOLVED]Closed: Two True-Dual-port rams in Zedboard

    Started by rafimiet, 21st October 2017 07:34
    • Replies: 3
    • Views: 526
    21st October 2017, 10:48 Go to last post
  24. Closed: How to find direction of signal travel in a given circuit?

    Started by matrixofdynamism, 20th October 2017 09:09
    • Replies: 1
    • Views: 397
    20th October 2017, 09:37 Go to last post
  25. Closed: YAJT (Yet Another Jtag Thread) - Signal integrity issues?

    Started by alexandicity, 18th October 2017 23:19
    • Replies: 10
    • Views: 1,068
    19th October 2017, 22:23 Go to last post
  26. Closed: Problem facing in Xpower Analyzer

    Started by qaziarbab, 12th October 2017 16:01
    • Replies: 7
    • Views: 1,002
    19th October 2017, 13:10 Go to last post