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Threads 3001 to 3030 of 22052

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: VHDL Synthesis Code help

    Started by Y.SAI SARASWATHI, 25th October 2014 16:05
    • Replies: 12
    • Views: 1,138
    27th October 2014, 05:43 Go to last post
  2. Closed: Frequency devider verilog code (50mhz to 75 micro second)

    Started by no0ona, 22nd October 2014 08:06
    • Replies: 7
    • Views: 1,108
    27th October 2014, 03:59 Go to last post
  3. [SOLVED]Closed: Need help on pipelining in square root using verilog

    Started by dipin, 15th October 2014 12:44
    • Replies: 14
    • Views: 2,566
    26th October 2014, 17:51 Go to last post
  4. Closed: Running 24bit adder at 128mhz, which FPGA to choose

    Started by ahgu, 24th October 2014 20:44
    • Replies: 15
    • Views: 1,399
    26th October 2014, 16:49 Go to last post
  5. Closed: vhdl code for an octal d-type flip flop register with clock enable

    Started by krisdan, 24th October 2014 15:12
    2 Pages
    1 2
    • Replies: 22
    • Views: 3,552
    26th October 2014, 16:45 Go to last post
  6. Closed: VHDL Simulators need help

    Started by Y.SAI SARASWATHI, 25th October 2014 15:44
    • Replies: 7
    • Views: 888
    26th October 2014, 16:11 Go to last post
  7. Closed: verilog code for turbo encoder and decoder

    Started by ksmb, 26th October 2014 08:42
    • Replies: 0
    • Views: 796
    26th October 2014, 08:42 Go to last post
  8. [SOLVED]Closed: Verilog for loop in test bench produces error in ModelSim

    Started by nervecell_23, 24th October 2014 12:07
    • Replies: 8
    • Views: 2,726
    24th October 2014, 18:06 Go to last post
  9. [SOLVED]Closed: Light-cycle game [HELP]

    Started by zilch, 24th October 2014 11:40
    • Replies: 0
    • Views: 404
    24th October 2014, 11:40 Go to last post
  10. Closed: Recomendation for a good VHDL book

    Started by flote21, 23rd October 2014 20:16
    • Replies: 2
    • Views: 1,339
    24th October 2014, 08:31 Go to last post
  11. Closed: mcf5272 coldfire programing?

    Started by arem, 23rd October 2014 22:49
    • Replies: 0
    • Views: 636
    23rd October 2014, 22:49 Go to last post
  12. Closed: Altera Qsys Generated Pci Express Wrapping

    Started by emrelevent, 23rd October 2014 18:31
    • Replies: 1
    • Views: 735
    23rd October 2014, 18:43 Go to last post
  13. Closed: [Moved] cascaded mux implementation using vhdl

    Started by rekhavp, 21st October 2014 09:28
    • Replies: 3
    • Views: 850
    22nd October 2014, 16:06 Go to last post
    • Replies: 0
    • Views: 623
    22nd October 2014, 15:48 Go to last post
  14. Moved: cascaded mux implementation using vhdl language

    Started by rekhavp, 22nd October 2014 15:51
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  15. Closed: vsim 7 Failed to open VHDL file "us2test/mspfiles" in r mode

    Started by abu9022, 21st October 2014 00:34
    • Replies: 5
    • Views: 1,083
    22nd October 2014, 06:36 Go to last post
    • Replies: 0
    • Views: 608
    22nd October 2014, 03:58 Go to last post
  16. Closed: [MOVED] any VHDL code available that implement PCA?

    Started by jmatsushita, 21st October 2014 16:18
    • Replies: 7
    • Views: 699
    21st October 2014, 18:49 Go to last post
    • Replies: 2
    • Views: 1,237
    21st October 2014, 15:28 Go to last post
  17. Closed: Generating a pulse of 100ns

    Started by mehanathan, 17th October 2014 04:28
    • Replies: 8
    • Views: 997
    21st October 2014, 13:01 Go to last post
  18. Closed: Doubt in Modelsim, simulation taking more time, I am doing correctly?

    Started by abu9022, 19th October 2014 17:52
    2 Pages
    1 2
    • Replies: 23
    • Views: 3,553
    20th October 2014, 18:06 Go to last post
  19. Closed: sdf file Error: Failed to find instance

    Started by abu9022, 20th October 2014 06:04
    • Replies: 3
    • Views: 1,746
    20th October 2014, 17:54 Go to last post
    • Replies: 4
    • Views: 949
    20th October 2014, 05:49 Go to last post
  20. Closed: xilinx timing analysis report

    Started by arishsu, 17th October 2014 03:52
    • Replies: 9
    • Views: 1,433
    20th October 2014, 05:35 Go to last post
  21. Closed: Wireless Video starter Kit

    Started by mkrtich.nazaryan, 20th October 2014 02:31
    • Replies: 0
    • Views: 417
    20th October 2014, 02:31 Go to last post
  22. Closed: decoder verilog code

    Started by vead, 17th October 2014 14:41
    • Replies: 9
    • Views: 3,643
    19th October 2014, 18:52 Go to last post
  23. [SOLVED]Closed: Verror 3033 the design unit was not found

    Started by abu9022, 18th October 2014 22:14
    • Replies: 4
    • Views: 1,281
    19th October 2014, 17:25 Go to last post
  24. Closed: Dynamic Reconfigurable CLock Frequency in Virtex FPGAs

    Started by msdarvishi, 19th October 2014 04:42
    • Replies: 3
    • Views: 1,247
    19th October 2014, 17:00 Go to last post
  25. Closed: sin wave multiplication using IP Cores -

    Started by Christian Chetcuti, 19th October 2014 11:25
    • Replies: 2
    • Views: 630
    19th October 2014, 12:20 Go to last post
  26. Closed: do functions synthesize to combinational logic?

    Started by shainky, 2nd October 2014 18:13
    • Replies: 8
    • Views: 1,353
    18th October 2014, 16:38 Go to last post