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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 29,096
    25th March 2007, 08:41 Go to last post
    • Replies: 5
    • Views: 205
    Yesterday, 18:13 Go to last post
  1. DFT & ATPG Tools enquiry

    Started by childs72, 11th January 2018 04:08
    • Replies: 4
    • Views: 429
    Yesterday, 11:10 Go to last post
  2. A small query on this small verilog code ?

    Started by hcu, 18th January 2018 18:24
    • Replies: 2
    • Views: 169
    Yesterday, 00:07 Go to last post
    • Replies: 3
    • Views: 144
    18th January 2018, 09:29 Go to last post
  3. Impedance of Microstrip Line

    Started by tashfeena, 17th January 2018 01:08
    • Replies: 1
    • Views: 207
    17th January 2018, 08:20 Go to last post
  4. Verilog accumulator error

    Started by Derun93, 16th January 2018 13:27
    • Replies: 4
    • Views: 196
    16th January 2018, 16:05 Go to last post
  5. Technology-based wire delay scale factors

    Started by ua6bqg, 26th December 2017 12:07
    • Replies: 6
    • Views: 849
    13th January 2018, 04:09 Go to last post
  6. Bitcoin Mining IC's or controller

    Started by gauravkothari23, 29th November 2017 19:22
    • Replies: 3
    • Views: 1,035
    12th January 2018, 11:32 Go to last post
  7. parallel chain and scan simulation

    Started by palanis29, 3rd January 2018 10:48
    • Replies: 7
    • Views: 979
    8th January 2018, 06:00 Go to last post
  8. Moved: [SOLVED] dft simulation error debugging

    Started by palanis29, 8th January 2018 07:11
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  9. reactive test benches

    Started by ananthan95, 15th December 2017 11:07
    • Replies: 9
    • Views: 1,610
    29th December 2017, 06:40 Go to last post
  10. [SOLVED] CRPR Threshold in PT

    Started by ua6bqg, 27th December 2017 19:10
    • Replies: 1
    • Views: 493
    28th December 2017, 14:42 Go to last post
  11. [SOLVED] Parallel/Serial Processes

    Started by entrepreneer, 26th December 2017 05:57
    • Replies: 4
    • Views: 574
    26th December 2017, 21:53 Go to last post
  12. Replicate the following VHDL into Verilog?

    Started by LearningSoMuch, 25th December 2017 03:06
    • Replies: 2
    • Views: 563
    26th December 2017, 21:49 Go to last post
  13. Best replacement policy for a fully associative cache

    Started by roshan12, 22nd December 2017 06:06
    • Replies: 0
    • Views: 471
    22nd December 2017, 06:06 Go to last post
  14. cadence tool digital design

    Started by 173, 18th December 2017 12:34
    • Replies: 3
    • Views: 783
    19th December 2017, 15:50 Go to last post
    • Replies: 0
    • Views: 476
    19th December 2017, 13:06 Go to last post
  15. about primetime output accuracy(significant digits)

    Started by jmaileh.b, 7th December 2017 08:18
    • Replies: 5
    • Views: 926
    17th December 2017, 15:46 Go to last post
  16. calibre antenna drc rule check warnings

    Started by sanjaysharmaiitk, 15th December 2017 10:52
    • Replies: 2
    • Views: 615
    16th December 2017, 01:57 Go to last post
    • Replies: 4
    • Views: 1,253
    16th December 2017, 01:13 Go to last post
  17. UART softcore testbench

    Started by promach, 7th June 2017 14:40
    • Replies: 10
    • Views: 2,059
    15th December 2017, 23:49 Go to last post
  18. Error in interface connection

    Started by muthu7495, 14th December 2017 06:23
    • Replies: 0
    • Views: 596
    14th December 2017, 06:23 Go to last post
    • Replies: 9
    • Views: 1,083
    13th December 2017, 18:56 Go to last post
  19. What is the definition of macro in Cadence?

    Started by ttxs, 12th December 2017 01:30
    • Replies: 1
    • Views: 793
    12th December 2017, 17:10 Go to last post
  20. 5-bit Sequential Multiplier Design

    Started by jeremeejoseph, 11th December 2017 06:01
    • Replies: 2
    • Views: 931
    11th December 2017, 15:38 Go to last post
  21. creating an one time delay in vhdl test bench

    Started by ananthan95, 9th December 2017 09:56
    • Replies: 3
    • Views: 727
    9th December 2017, 13:27 Go to last post
  22. Help in Alliance synthesis too (SYF)

    Started by Amr_Rashed, 30th November 2017 11:01
    • Replies: 6
    • Views: 2,888
    9th December 2017, 11:46 Go to last post
  23. Hierarchical rail IR drop analysis in Encounter/Voltus

    Started by alphus, 7th December 2017 11:00
    • Replies: 0
    • Views: 1,207
    7th December 2017, 11:00 Go to last post