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Threads 1501 to 1530 of 18959

Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Closed: How to match pmos and nmos current source?

    Started by shanmei, 7th September 2015 15:24
    • Replies: 2
    • Views: 763
    11th September 2015, 18:03 Go to last post
    • Replies: 5
    • Views: 1,105
    10th September 2015, 13:34 Go to last post
  2. Closed: LUP.2g DRC in tsmc 65nm technology

    Started by guruprasadds, 4th August 2015 03:40
    • Replies: 2
    • Views: 1,136
    10th September 2015, 03:23 Go to last post
  3. Closed: Cadence Virtuoso: Unable to write changes in memory to disk for file

    Started by abimana, 7th September 2015 21:43
    • Replies: 0
    • Views: 1,680
    7th September 2015, 21:43 Go to last post
    • Replies: 1
    • Views: 732
    7th September 2015, 15:04 Go to last post
  4. Closed: Cadence Virtuoso DC operating points

    Started by kenambo, 4th September 2015 14:37
    • Replies: 3
    • Views: 1,445
    5th September 2015, 07:45 Go to last post
  5. Closed: skill- layer replace in a bounding box

    Started by Chandan_333, 3rd September 2015 06:24
    • Replies: 3
    • Views: 906
    4th September 2015, 16:29 Go to last post
    • Replies: 11
    • Views: 1,634
    4th September 2015, 11:23 Go to last post
  6. Closed: 110 nm layout technology

    Started by kvidhya, 6th July 2015 11:05
    • Replies: 2
    • Views: 731
    4th September 2015, 09:43 Go to last post
  7. Closed: [Moved] analog layout ( capacitor).

    Started by kvidhya, 10th July 2015 05:00
    • Replies: 3
    • Views: 924
    4th September 2015, 09:37 Go to last post
  8. Closed: Noise figure simulations of an ideal amplifier

    Started by viperpaki007, 3rd September 2015 11:34
    • Replies: 1
    • Views: 571
    3rd September 2015, 13:35 Go to last post
  9. [SOLVED]Closed: Inversion Coefficient and gm/Id relation

    Started by kenambo, 2nd September 2015 13:48
    • Replies: 6
    • Views: 1,694
    3rd September 2015, 12:35 Go to last post
  10. Closed: verilog simulation in cadence

    Started by swapna julakanti, 3rd September 2015 05:19
    • Replies: 2
    • Views: 946
    3rd September 2015, 06:25 Go to last post
  11. Closed: Unable to export cdl netlist

    Started by afujian, 2nd September 2015 03:30
    • Replies: 0
    • Views: 997
    2nd September 2015, 03:30 Go to last post
  12. Closed: parametric analyse in monte carlo simulation

    Started by rey1991, 1st September 2015 15:09
    • Replies: 2
    • Views: 736
    1st September 2015, 20:41 Go to last post
  13. Closed: integrated inductor design and simulation

    Started by amir88, 1st September 2015 18:28
    • Replies: 0
    • Views: 658
    1st September 2015, 18:28 Go to last post
  14. Closed: MOSFET Differential Pair (Analysis)

    Started by farhan89, 1st September 2015 14:50
    • Replies: 1
    • Views: 708
    1st September 2015, 15:06 Go to last post
  15. Closed: regarding beta effective

    Started by swapna julakanti, 28th August 2015 18:11
    • Replies: 2
    • Views: 948
    31st August 2015, 14:37 Go to last post
  16. Closed: regions of operation

    Started by swapna julakanti, 27th August 2015 19:47
    • Replies: 3
    • Views: 878
    28th August 2015, 14:58 Go to last post
  17. Closed: Op amp Common Mode Feedback Design

    Started by Shady Ahmed, 26th August 2015 09:19
    • Replies: 2
    • Views: 1,004
    28th August 2015, 14:39 Go to last post
    • Replies: 3
    • Views: 2,035
    28th August 2015, 13:26 Go to last post
  18. Closed: Chip corner stress in IO ring assembly

    Started by analog_ip, 25th August 2015 13:11
    • Replies: 1
    • Views: 649
    26th August 2015, 16:26 Go to last post
  19. Closed: Analog design: max voltage selector

    Started by maxporter, 21st August 2015 10:09
    • Replies: 4
    • Views: 871
    25th August 2015, 14:31 Go to last post
  20. Closed: ESD cells and grounding

    Started by powerelec, 21st August 2015 11:08
    • Replies: 8
    • Views: 1,060
    25th August 2015, 13:42 Go to last post
  21. Closed: How to do a simultaneous selection in Virtuoso Layout

    Started by abonic, 14th August 2015 04:01
    • Replies: 7
    • Views: 850
    25th August 2015, 09:56 Go to last post
  22. Closed: cluster: eesofg2p, ads momemtum

    Started by moss88, 21st January 2015 12:19
    • Replies: 2
    • Views: 3,174
    24th August 2015, 17:06 Go to last post
  23. Closed: how to start DAC design?

    Started by RAMANATHANDL, 24th August 2015 13:44
    • Replies: 1
    • Views: 557
    24th August 2015, 15:29 Go to last post
  24. Closed: Effects of common mode feed back on stability

    Started by electronics_rama, 21st August 2015 05:04
    • Replies: 1
    • Views: 736
    22nd August 2015, 18:11 Go to last post
  25. Closed: 90 nm technology parameters

    Started by rahul91, 22nd August 2015 14:57
    • Replies: 1
    • Views: 1,045
    22nd August 2015, 17:51 Go to last post
  26. Closed: PVT corners in cadence 6.1.4

    Started by rey1991, 21st August 2015 15:27
    • Replies: 2
    • Views: 1,034
    22nd August 2015, 06:02 Go to last post