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Threads 301 to 330 of 19340

Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Closed: AC / Noise after a tran

    Started by Fabien, 5th April 2019 10:28
    • Replies: 3
    • Views: 461
    FvM
    7th April 2019, 08:46 Go to last post

  2. Closed: Verilog-A platform for windows

    Started by MahmoudHassan, 5th April 2019 17:51
    • Replies: 1
    • Views: 380
    pancho_hideboo
    6th April 2019, 16:57 Go to last post

  3. Closed: Current in bulk cascode device

    Started by maxporter, 4th April 2019 16:07
    1 Attachment(s)
    • Replies: 2
    • Views: 434
    maxporter
    4th April 2019, 22:18 Go to last post

  4. [SOLVED]Closed: Accurate transient setting for DFT and Spectrum in cadence

    Started by Junus2012, 1st April 2019 16:07
    5 Attachment(s)
    • Replies: 15
    • Views: 2,163
    Junus2012
    3rd April 2019, 21:08 Go to last post

  5. Closed: What does it mean to check mismatch and process in ADEXL Monte Carlo?

    Started by Megahed89, 2nd April 2019 22:46
    • Replies: 2
    • Views: 407
    vivekroy
    3rd April 2019, 12:40 Go to last post

  6. Closed: RFESDpads use instead of I/O pads

    Started by student14, 3rd April 2019 08:34
    • Replies: 0
    • Views: 161
    student14
    3rd April 2019, 08:34 Go to last post

  7. Closed: gm of this feedback common source transistor

    Started by shanmei, 30th March 2019 16:28
    2 Attachment(s)
    • Replies: 5
    • Views: 1,180
    shanmei
    2nd April 2019, 16:58 Go to last post

  8. Closed: CMFB compensation using one capacitor at the the CMFB input

    Started by Junus2012, 28th March 2019 13:11
    3 Attachment(s)
    • Replies: 18
    • Views: 2,704
    Junus2012
    1st April 2019, 19:47 Go to last post

  9. Closed: Problem during simulating active inductor with ADS simulator

    Started by noor84, 30th March 2019 00:46
    6 Attachment(s)
    • Replies: 14
    • Views: 1,492
    noor84
    30th March 2019, 22:41 Go to last post

  10. [SOLVED]Closed: HSPICE - Synopsys - SAE Simulations

    Started by EJGC22, 29th March 2019 18:00
    • Replies: 0
    • Views: 279
    EJGC22
    29th March 2019, 18:00 Go to last post

  11. Closed: Use which model of TSMC lib to design in high speed?

    Started by usuikazkou, 23rd March 2019 09:43
    • Replies: 1
    • Views: 316
    dick_freebird
    28th March 2019, 23:00 Go to last post

  12. Closed: Pole Zero analyses in cadence

    Started by Junus2012, 27th March 2019 14:36
    4 Attachment(s)
    • Replies: 9
    • Views: 1,584
    Junus2012
    28th March 2019, 14:40 Go to last post

  13. [SOLVED]Closed: How to simulate a circuit with feedback with a test voltage after making a breakpoint

    Started by rmanalo, 18th March 2019 15:30
    3 Attachment(s)
    • Replies: 9
    • Views: 1,363
    sutapanaki
    28th March 2019, 05:01 Go to last post

  14. Closed: About ICs with high potential differences within ...

    Started by Oveis.Gharan, 27th March 2019 13:51
    • Replies: 2
    • Views: 626
    nitishn5
    28th March 2019, 04:33 Go to last post

  15. Closed: wafer process based on N-substrate

    Started by okguy, 27th March 2019 19:10
    • Replies: 1
    • Views: 628
    dick_freebird
    28th March 2019, 01:22 Go to last post

  16. Closed: Slew rate simulation for fully differential amplifier

    Started by Junus2012, 26th March 2019 17:42
    • Replies: 11
    • Views: 1,703
    sutapanaki
    27th March 2019, 23:50 Go to last post

  17. Closed: Signal to noise ratio of the operational amplifier

    Started by Junus2012, 21st March 2019 00:07
    3 Pages •
    1 2 3
    32 Attachment(s)
    • Replies: 52
    • Views: 6,665
    Junus2012
    26th March 2019, 20:23 Go to last post

  18. [SOLVED]Closed: [moved] Need help writing equations in Verilog A. My first code in Verilog A.

    Started by soursethi17, 19th March 2019 08:33
    1 Attachment(s)
    • Replies: 4
    • Views: 549
    soursethi17
    26th March 2019, 08:52 Go to last post

  19. Closed: DRC Error: N+SD Iso Psub tap spacing must be <=10.0 um

    Started by sp.bhuvana, 26th February 2019 08:23
    3 Attachment(s)
    • Replies: 7
    • Views: 1,002
    sp.bhuvana
    26th March 2019, 06:19 Go to last post

  20. Closed: Mismatch model in Verilog-A in Cadence and Synopsys

    Started by EJGC22, 25th March 2019 14:27
    • Replies: 0
    • Views: 210
    EJGC22
    25th March 2019, 14:27 Go to last post

  21. [SOLVED]Closed: Connect rules are not found in your AMS installation? error

    Started by Chaoping, 18th March 2019 00:46
    5 Attachment(s)
    • Replies: 2
    • Views: 595
    Chaoping
    23rd March 2019, 23:10 Go to last post

  22. Closed: IC layout I/O design------power on control (POC) cell

    Started by AllenD, 17th March 2019 05:08
    1 Attachment(s)
    • Replies: 2
    • Views: 980
    ThisIsNotSam
    22nd March 2019, 20:36 Go to last post

  23. Closed: Nand2 gate in magic vlsi

    Started by abdoboua, 15th March 2019 10:43
    2 Attachment(s)
    • Replies: 1
    • Views: 288
    erikl
    22nd March 2019, 20:21 Go to last post

  24. Closed: Topology of CMOS DC-DC converter for Piezoelectric MEMS

    Started by palmeiras, 20th March 2019 18:05
    • Replies: 1
    • Views: 665
    dick_freebird
    20th March 2019, 22:48 Go to last post

  25. [SOLVED]Closed: CMRR simulation for fully differential amplifier

    Started by Junus2012, 19th March 2019 00:11
    2 Pages •
    1 2
    6 Attachment(s)
    • Replies: 20
    • Views: 2,972
    frankrose
    20th March 2019, 18:56 Go to last post

  26. Closed: Voltage degradation in Hold mode of the bootstrap switch ?

    Started by Electric_Shock, 19th March 2019 13:33
    1 Attachment(s)
    • Replies: 2
    • Views: 274
    sutapanaki
    19th March 2019, 17:52 Go to last post

  27. Closed: Empty ceramic dies/packages for ICs

    Started by Eres_89, 18th March 2019 15:29
    • Replies: 3
    • Views: 297
    Eres_89
    19th March 2019, 00:40 Go to last post

  28. [SOLVED]Closed: CMFB loop bandwidth requirement

    Started by Junus2012, 15th March 2019 12:01
    • Replies: 4
    • Views: 445
    vivekroy
    16th March 2019, 11:00 Go to last post

  29. Closed: Oscillator jitter from the tail current

    Started by shanmei, 14th March 2019 16:26
    • Replies: 1
    • Views: 341
    vivekroy
    15th March 2019, 12:09 Go to last post

  30. Closed: method of phase noise calculation of PLL

    Started by kunalsan, 12th March 2019 18:02
    • Replies: 3
    • Views: 682
    vivekroy
    15th March 2019, 12:03 Go to last post
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