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Threads 301 to 330 of 18959

Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Closed: Layer definition in TSMC 65nm

    Started by AllenD, 18th April 2018 04:49
    • Replies: 2
    • Views: 1,418
    20th April 2018, 10:35 Go to last post
  2. Closed: line regulation of voltage reference problem

    Started by chandlerbing65nm, 19th April 2018 20:58
    • Replies: 3
    • Views: 541
    19th April 2018, 23:13 Go to last post
  3. Closed: Net Connectivity result saved, does not include pin labels!

    Started by DefconNowhere, 3rd November 2017 13:44
    • Replies: 8
    • Views: 2,031
    19th April 2018, 18:31 Go to last post
  4. Closed: Abutting transistors in TSMC65nm

    Started by Puppet123, 17th April 2018 22:35
    • Replies: 2
    • Views: 562
    18th April 2018, 20:04 Go to last post
  5. Closed: layout problems in voltage divider using diode connected mosfet

    Started by gopalece, 18th April 2018 06:47
    • Replies: 2
    • Views: 568
    18th April 2018, 18:55 Go to last post
    • Replies: 4
    • Views: 925
    18th April 2018, 14:26 Go to last post
  6. Closed: Bandgap voltage reference Vref =+0.45 Vdd = +1.2

    Started by chandlerbing65nm, 9th April 2018 10:00
    • Replies: 8
    • Views: 1,324
    18th April 2018, 08:03 Go to last post
  7. Closed: Layout of Transistors with large width and large current draw

    Started by Puppet123, 16th April 2018 02:44
    • Replies: 3
    • Views: 782
    17th April 2018, 22:28 Go to last post
  8. Closed: Long start-up time current reference

    Started by chandlerbing65nm, 17th April 2018 09:03
    • Replies: 2
    • Views: 482
    17th April 2018, 21:06 Go to last post
  9. Closed: offset voltage of opamp

    Started by chandlerbing65nm, 17th April 2018 16:33
    • Replies: 2
    • Views: 416
    17th April 2018, 20:57 Go to last post
  10. Closed: Current Reference SS problem

    Started by chandlerbing65nm, 15th April 2018 23:57
    • Replies: 1
    • Views: 496
    16th April 2018, 19:06 Go to last post
    • Replies: 7
    • Views: 1,433
    16th April 2018, 08:14 Go to last post
    • Replies: 2
    • Views: 542
    16th April 2018, 04:52 Go to last post
  11. Closed: Current Mirror Inaccuracy

    Started by chandlerbing65nm, 15th April 2018 19:58
    • Replies: 2
    • Views: 465
    15th April 2018, 21:22 Go to last post
  12. Closed: Transmission Gate Impedance Problem

    Started by andreneil15, 7th April 2018 05:47
    • Replies: 8
    • Views: 919
    15th April 2018, 03:18 Go to last post
  13. Closed: Common Centroid Layout

    Started by Puppet123, 12th April 2018 20:56
    • Replies: 5
    • Views: 1,093
    14th April 2018, 07:07 Go to last post
  14. Closed: Cadence Layout - Interdigitization

    Started by Puppet123, 13th April 2018 23:46
    • Replies: 1
    • Views: 767
    14th April 2018, 04:28 Go to last post
    • Replies: 1
    • Views: 352
    13th April 2018, 13:04 Go to last post
  15. characterizing semiconductors

    Started by Madbunny1, 12th April 2018 19:10
    • Replies: 2
    • Views: 479
    12th April 2018, 20:41 Go to last post
  16. Closed: Current mirror transistor connection

    Started by akbarza, 26th March 2018 12:56
    • Replies: 2
    • Views: 696
    12th April 2018, 15:09 Go to last post
  17. Closed: Low frequency signals 10-20KS/sec S/H application

    Started by chandlerbing65nm, 10th April 2018 06:11
    • Replies: 1
    • Views: 457
    12th April 2018, 15:04 Go to last post
  18. Closed: How to polarise the Deep N-Well (WB) or tap WB in the layout

    Started by tisheebird, 9th April 2018 19:51
    • Replies: 5
    • Views: 798
    11th April 2018, 17:48 Go to last post
  19. Closed: parameters of clock generators

    Started by chandlerbing65nm, 10th April 2018 18:41
    • Replies: 1
    • Views: 372
    10th April 2018, 21:25 Go to last post
  20. Closed: Hand calculation of PMOS OPA

    Started by chandlerbing65nm, 10th April 2018 04:10
    • Replies: 2
    • Views: 650
    10th April 2018, 18:36 Go to last post
  21. Closed: [Moved]: Cadence coverage database

    Started by nidhi.padiya, 10th April 2018 14:18
    • Replies: 0
    • Views: 376
    10th April 2018, 14:18 Go to last post
  22. [SOLVED]Closed: I can't get high frequency output of my Ramp Generator

    Started by chandlerbing65nm, 5th April 2018 17:35
    2 Pages
    1 2
    • Replies: 21
    • Views: 1,908
    9th April 2018, 21:23 Go to last post
  23. Closed: Gate current of mosfet when used as a switch

    Started by chandlerbing65nm, 9th April 2018 13:01
    • Replies: 2
    • Views: 481
    9th April 2018, 16:14 Go to last post
  24. Closed: Mos sooch cascode current mirror

    Started by electronics_rama, 7th April 2018 12:36
    • Replies: 10
    • Views: 1,332
    8th April 2018, 13:00 Go to last post
  25. Closed: CMOS voltage buffer for driving 500pF cap

    Started by electronics_rama, 7th April 2018 12:33
    • Replies: 4
    • Views: 701
    8th April 2018, 07:50 Go to last post
  26. [SOLVED]Closed: how to convert Current Pulse to Voltage Pulse?

    Started by chandlerbing65nm, 7th April 2018 16:21
    • Replies: 2
    • Views: 670
    7th April 2018, 18:45 Go to last post