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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Closed: ANSYS Totem electromigration check

    Started by frankrose, 11th February 2019 15:40
    • Replies: 3
    • Views: 622
    14th February 2019, 08:35 Go to last post
  2. [SOLVED]Closed: Resistance /impedance looking into the source / drain ?

    Started by Robotduck, 10th February 2019 23:31
    • Replies: 9
    • Views: 631
    14th February 2019, 05:27 Go to last post
  3. Closed: Brokaw Cell Start Up Question

    Started by ljp2706, 12th February 2019 22:10
    • Replies: 1
    • Views: 306
    13th February 2019, 01:47 Go to last post
  4. Closed: transistor state in cadence vertuso

    Started by Junus2012, 3rd February 2019 14:41
    • Replies: 7
    • Views: 480
    8th February 2019, 19:57 Go to last post
  5. [SOLVED]Closed: Post layout Monte-carlo simulation with TSMC 180

    Started by AfonsoPlantes, 25th January 2019 18:33
    • Replies: 5
    • Views: 920
    8th February 2019, 16:31 Go to last post
  6. Closed: SLOT PROPERTIES added to design_Allegro pcb ECO

    Started by Amal.v.s, 7th February 2019 10:22
    • Replies: 2
    • Views: 422
    8th February 2019, 13:41 Go to last post
    • Replies: 0
    • Views: 239
    7th February 2019, 08:38 Go to last post
  7. Closed: GaAs, GaN MMICs in die, package or module form

    Started by optimizers, 5th February 2019 07:32
    • Replies: 2
    • Views: 295
    7th February 2019, 05:39 Go to last post
  8. Closed: Shielding in IC analog layout design

    Started by Green_Ic, 4th February 2019 19:28
    • Replies: 2
    • Views: 522
    5th February 2019, 14:30 Go to last post
  9. Closed: LFoundry layout design rules

    Started by student14, 19th January 2019 18:57
    • Replies: 3
    • Views: 573
    4th February 2019, 20:37 Go to last post
  10. Closed: Slew rate and bandwidth distortion

    Started by Junus2012, 3rd February 2019 14:45
    • Replies: 7
    • Views: 564
    3rd February 2019, 19:52 Go to last post
  11. Closed: synchronize boards with 3 Meter distance

    Started by aminpix, 2nd February 2019 19:26
    • Replies: 5
    • Views: 380
    3rd February 2019, 16:41 Go to last post
  12. Closed: Analog Layout and Dummies

    Started by Puppet123, 20th December 2018 21:18
    • Replies: 3
    • Views: 557
    2nd February 2019, 16:11 Go to last post
  13. Closed: Perl/Python Scripting for Analog/Mixed Signal Design

    Started by Puppet123, 9th January 2019 21:09
    • Replies: 3
    • Views: 661
    2nd February 2019, 16:07 Go to last post
  14. Closed: x snap spacing and y snap spacing

    Started by student14, 24th January 2019 05:40
    • Replies: 18
    • Views: 1,552
    31st January 2019, 05:15 Go to last post
  15. Closed: Dataauditerror in DRC check

    Started by student14, 30th January 2019 10:33
    • Replies: 1
    • Views: 306
    30th January 2019, 19:42 Go to last post
  16. Closed: Rail to rail input stage of current mirror OTA amplifier

    Started by Junus2012, 24th January 2019 20:44
    • Replies: 8
    • Views: 988
    27th January 2019, 11:39 Go to last post
  17. Closed: DAC design for 14- bit SAR ADC

    Started by ajaychowdharykr, 6th January 2019 13:22
    • Replies: 4
    • Views: 629
    26th January 2019, 14:34 Go to last post
  18. Closed: Montocarlo simulation silterra

    Started by student14, 22nd January 2019 11:50
    • Replies: 3
    • Views: 450
    24th January 2019, 05:44 Go to last post
  19. Closed: diodes vs temperature

    Started by part56, 23rd January 2019 17:27
    • Replies: 3
    • Views: 365
    23rd January 2019, 22:23 Go to last post
  20. Closed: The confinement effect in thin(and small width) metal tracks?

    Started by melkord, 7th January 2019 08:18
    • Replies: 3
    • Views: 603
    18th January 2019, 09:32 Go to last post
  21. Closed: How to run .scs netlist file cadence

    Started by npsnpsnps, 16th January 2019 18:55
    • Replies: 6
    • Views: 876
    18th January 2019, 01:31 Go to last post
  22. Closed: ESD and parasitic inductances of bond wire

    Started by ICnow, 15th January 2019 15:48
    • Replies: 3
    • Views: 536
    17th January 2019, 19:40 Go to last post
  23. Closed: SAR logic design for 10-bit SAR ADC ?

    Started by Electric_Shock, 17th January 2019 15:06
    • Replies: 0
    • Views: 359
    17th January 2019, 15:06 Go to last post
  24. Closed: instrumentation amplifier with wide differential input

    Started by Junus2012, 12th January 2019 21:09
    • Replies: 3
    • Views: 516
    14th January 2019, 17:06 Go to last post
  25. Closed: Voltage to current converter of high speed CDR circuit

    Started by usuikazkou, 11th January 2019 08:19
    • Replies: 4
    • Views: 733
    11th January 2019, 19:35 Go to last post
  26. Closed: Source code of skill function of Cadence Virtuoso

    Started by quyleanh, 10th January 2019 01:18
    • Replies: 3
    • Views: 1,041
    11th January 2019, 05:31 Go to last post
  27. Closed: Missing via (M1-substrate)&(M1-nwell) bulk tsmc65N

    Started by bll_hb, 4th January 2019 13:46
    • Replies: 1
    • Views: 424
    4th January 2019, 23:44 Go to last post
  28. Closed: 28nm and Below MOS Layout

    Started by Puppet123, 3rd January 2019 02:20
    • Replies: 0
    • Views: 544
    3rd January 2019, 02:20 Go to last post
  29. Closed: Inter-digitization Pattern and Dummies for MOS Layout

    Started by Puppet123, 22nd December 2018 22:49
    • Replies: 2
    • Views: 502
    2nd January 2019, 13:28 Go to last post