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Forum: Analog Integrated Circuit (IC) Design, Layout and Fabrication

Analog Integrated Circuit Design, Layout & Fabrication Questions. Analog ASIC Design. Semiconductor Technology Issues.

  1. Sticky Thread Sticky: Read this before posting

    Started by klug, 3rd December 2007 18:00
    • Replies: 0
    • Views: 30,946
    3rd December 2007, 18:00 Go to last post
  2. Sticky Thread Sticky: [SOLVED] Tiny but mighty: TLV7011 comparator

    Started by B. David Miyares, 1st May 2018 14:19
    • Replies: 0
    • Views: 3,380
    1st May 2018, 14:19 Go to last post
  1. Closed: What is a trimming circuit ??

    Started by gafsos, 15th May 2006 13:20
    • Replies: 6
    • Views: 10,049
    18th May 2006, 07:25 Go to last post
  2. Closed:

    Started by shanmei, 19th February 2018 17:07
    • Replies: 11
    • Views: 1,846
    26th February 2018, 21:17 Go to last post
  3. Closed: $ sign in extracted hspice netlist

    Started by Milad-D, 17th February 2011 02:32
    • Replies: 3
    • Views: 2,144
    21st February 2011, 11:07 Go to last post
  4. [SOLVED]Closed: ıf some current is injected to drain of the MOSFET, why vds increases?

    Started by Derun93, 11th November 2016 11:49
    • Replies: 3
    • Views: 872
    13th November 2016, 21:21 Go to last post
  5. Closed: 【Q】A question about a bipolar referenc

    Started by leonwang, 30th July 2008 03:17
    • Replies: 0
    • Views: 1,006
    30th July 2008, 03:17 Go to last post
    • Replies: 5
    • Views: 2,715
    12th August 2013, 19:56 Go to last post
    • Replies: 2
    • Views: 905
    8th August 2014, 01:58 Go to last post
  6. Closed: " Calibre + hspice " post-sim netlist pin name problems

    Started by wwwww12345, 17th September 2011 03:56
    • Replies: 1
    • Views: 1,323
    17th September 2011, 06:21 Go to last post
  7. Closed: " Errors in Invoking Assura into Cadence DFII Frame Wor

    Started by Prasanna Kumar, 4th January 2005 12:50
    • Replies: 1
    • Views: 1,819
    22nd January 2005, 04:44 Go to last post
  8. Closed: " | " in front of all nets after IC craftsman impl

    Started by monsieur_2, 9th November 2004 07:45
    • Replies: 0
    • Views: 1,393
    9th November 2004, 07:45 Go to last post
    • Replies: 1
    • Views: 1,383
    19th September 2012, 08:54 Go to last post
  9. Closed: "analog layout automation"

    Started by whizking, 4th August 2004 16:00
    2 Pages
    1 2
    • Replies: 29
    • Views: 5,266
    4th June 2008, 14:03 Go to last post
  10. Closed: "Basics" of Analog Circuit Design

    Started by bunda_bindaas, 8th March 2008 12:25
    • Replies: 13
    • Views: 3,564
    21st March 2008, 00:55 Go to last post
  11. Closed: "Coupling" extraction more accurate than "Dec

    Started by yuwenhuan, 28th February 2009 01:47
    • Replies: 0
    • Views: 1,153
    28th February 2009, 01:47 Go to last post
  12. Closed: "GROUND && ! POWER": no POWER nets present

    Started by casual, 8th March 2010 08:45
    • Replies: 7
    • Views: 12,366
    19th October 2011, 18:04 Go to last post
  13. Closed: "IE.verimix" error when running mix-signal simulat

    Started by lxcpku, 20th September 2007 06:35
    • Replies: 5
    • Views: 2,248
    16th November 2010, 16:04 Go to last post
  14. Closed: "Length of MOSFET" is a design variable or not......

    Started by Ramakrishna_444, 17th September 2012 19:16
    • Replies: 4
    • Views: 984
    9th October 2012, 13:32 Go to last post
  15. Closed: "level" in spice model

    Started by m.azangoo, 29th August 2009 22:25
    • Replies: 3
    • Views: 2,047
    30th August 2009, 22:49 Go to last post
  16. Closed: "No similar net" LVS error HELP!

    Started by tasctasc, 13th September 2011 08:41
    • Replies: 2
    • Views: 2,760
    14th September 2011, 19:08 Go to last post
  17. Closed: "No stamped connections"

    Started by santom, 4th June 2009 05:07
    • Replies: 5
    • Views: 1,845
    8th October 2014, 15:20 Go to last post
  18. Closed: "np" layer and "pp" layer in CMOS circuit

    Started by AllenD, 12th July 2018 04:39
    • Replies: 4
    • Views: 2,024
    15th July 2018, 03:55 Go to last post
  19. [SOLVED]Closed: "only one connection" while simulating av_extracted

    Started by itacool, 23rd August 2016 19:59
    • Replies: 1
    • Views: 611
    23rd August 2016, 20:18 Go to last post
    • Replies: 6
    • Views: 1,449
    14th September 2018, 19:35 Go to last post
  20. Closed: "Problems encountered during simulation" in cadenc

    Started by tshankar501, 9th June 2008 22:59
    • Replies: 3
    • Views: 2,977
    7th August 2008, 21:03 Go to last post
  21. Closed: "Process varition"

    Started by viren_s, 17th November 2006 05:34
    • Replies: 2
    • Views: 1,025
    25th November 2006, 14:16 Go to last post
  22. [SOLVED]Closed: "PSUB" pin in HV 0.35 m AMS

    Started by K4R1, 13th March 2014 14:51
    • Replies: 2
    • Views: 898
    14th March 2014, 09:22 Go to last post
  23. Closed: "Region of operation" parameter and Vdsat

    Started by justanengineer, 16th December 2014 17:04
    • Replies: 4
    • Views: 962
    16th December 2014, 19:04 Go to last post
  24. Closed: "region" field on Cadence

    Started by eransal, 18th January 2009 09:45
    • Replies: 3
    • Views: 1,783
    18th January 2009, 21:28 Go to last post
  25. Closed: "size error" during LVS,urgent, thank you!!!

    Started by foreverloves, 2nd August 2006 03:15
    • Replies: 16
    • Views: 1,995
    5th February 2007, 08:20 Go to last post