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Threads 22021 to 22050 of 22301

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: spartan pin LOC problem

    Started by Tetra, 22nd July 2003 10:25
    • Replies: 7
    • Views: 4,828
    24th July 2003, 08:27 Go to last post
  2. Closed: Multipile and LUT function

    Started by J_expoler2, 23rd July 2003 16:14
    • Replies: 0
    • Views: 1,022
    23rd July 2003, 16:14 Go to last post
  3. Closed: Plugging PCI into PC and SUN

    Started by mystery, 23rd July 2003 13:16
    • Replies: 0
    • Views: 1,132
    23rd July 2003, 13:16 Go to last post
  4. Closed: Comparison of VHDL, Verilog, and System verilog

    Started by niks, 23rd July 2003 09:52
    • Replies: 2
    • Views: 3,513
    23rd July 2003, 12:41 Go to last post
  5. Closed: How to simulate this vhdl code using max plus 2

    Started by mcfly, 22nd July 2003 15:12
    • Replies: 3
    • Views: 2,184
    22nd July 2003, 17:19 Go to last post
  6. Closed: What is the Stratix startup time ?

    Started by kobik, 22nd July 2003 09:03
    • Replies: 1
    • Views: 1,134
    22nd July 2003, 09:30 Go to last post
  7. Closed: how processor can program the EPC16 (@ltera)

    Started by kobik, 22nd July 2003 09:19
    • Replies: 0
    • Views: 1,493
    22nd July 2003, 09:19 Go to last post
  8. Closed: how to design a 74HC245 using verilog?

    Started by vonzhaoqun, 18th July 2003 06:22
    • Replies: 5
    • Views: 2,958
    21st July 2003, 23:18 Go to last post
  9. Closed: How can I specify the division ratio in xilinx DLL?

    Started by Tetra, 20th July 2003 09:20
    • Replies: 2
    • Views: 1,185
    20th July 2003, 21:04 Go to last post
  10. Closed: What is the difference between FPGAs and PLCs?

    Started by you_rock, 8th July 2003 00:09
    • Replies: 3
    • Views: 1,884
    20th July 2003, 20:07 Go to last post
  11. Closed: Help required with Xilinx ISE for SPARTAN device

    Started by sanjay, 13th July 2003 19:08
    • Replies: 5
    • Views: 1,619
    18th July 2003, 14:57 Go to last post
  12. Closed: Delay configuration completion by DLL

    Started by Tetra, 17th July 2003 12:47
    • Replies: 3
    • Views: 1,097
    18th July 2003, 11:09 Go to last post
  13. Closed: Help needed for Pin Allocation for Xilinx ISE4.2

    Started by sanjay, 17th July 2003 09:08
    • Replies: 5
    • Views: 1,447
    17th July 2003, 21:35 Go to last post
  14. Closed: is 44pin 64 microcells enough?

    Started by wwwrabbit, 17th July 2003 19:00
    • Replies: 3
    • Views: 1,265
    17th July 2003, 20:46 Go to last post
  15. Closed: Error Code information needed for Xilinx ISE4.2

    Started by sanjay, 17th July 2003 09:45
    • Replies: 3
    • Views: 1,133
    17th July 2003, 12:51 Go to last post
  16. [SOLVED]Closed: splitting a big mux - how can I access the CSRs

    Started by paash, 14th July 2003 07:16
    • Replies: 2
    • Views: 1,152
    15th July 2003, 05:47 Go to last post
  17. Closed: Best way to build big LUT

    Started by Tetra, 14th July 2003 11:56
    • Replies: 3
    • Views: 1,929
    14th July 2003, 12:33 Go to last post
  18. Closed: problem in modelsim simulation

    Started by ukapil, 14th July 2003 06:48
    • Replies: 1
    • Views: 1,554
    14th July 2003, 08:01 Go to last post
  19. Closed: Where can I download Cam 350 V8?

    Started by concat, 26th March 2003 07:34
    • Replies: 6
    • Views: 3,193
    14th July 2003, 04:01 Go to last post
  20. Closed: New Xilinx EDK 3.2: product description

    Started by ddr, 24th April 2003 08:12
    • Replies: 6
    • Views: 2,569
    13th July 2003, 21:03 Go to last post
  21. Closed: looking for a SERIALISER/DESERIALISER

    Started by geytan, 13th July 2003 14:33
    • Replies: 2
    • Views: 1,351
    13th July 2003, 16:32 Go to last post
  22. Closed: about Xilinx Spartan-III device

    Started by liuqing, 10th July 2003 08:11
    • Replies: 4
    • Views: 1,283
    12th July 2003, 16:25 Go to last post
  23. Closed: Need shematic for ALTERA ByteBlaster II DownLoad Cable!!

    Started by confide, 13th June 2003 02:46
    • Replies: 8
    • Views: 5,303
    12th July 2003, 12:54 Go to last post
  24. Closed: xilinx download schematics

    Started by rntsay, 12th July 2003 08:58
    • Replies: 3
    • Views: 1,780
    12th July 2003, 11:28 Go to last post
  25. Closed: Does anyone use @ltera Nios dev. kit?

    Started by ltg, 11th July 2003 08:04
    • Replies: 2
    • Views: 1,183
    11th July 2003, 17:01 Go to last post
  26. Closed: Use chipscope to capture some signals from my FPGA

    Started by fighter, 12th May 2003 03:16
    • Replies: 7
    • Views: 2,721
    11th July 2003, 16:20 Go to last post
  27. Closed: help with HDL Designer 2003

    Started by xvibe, 11th July 2003 12:01
    • Replies: 2
    • Views: 1,365
    11th July 2003, 14:36 Go to last post
  28. Closed: design works well at fpga but fails in real chip?

    Started by adanshen, 3rd July 2003 02:57
    • Replies: 3
    • Views: 1,272
    11th July 2003, 06:41 Go to last post
  29. Closed: some IP protection software?

    Started by dd2001, 24th June 2003 06:36
    • Replies: 1
    • Views: 1,365
    10th July 2003, 17:47 Go to last post
  30. Closed: Schematic for FPGA/CPLD (students/developers) KIT

    Started by ekhat, 3rd July 2003 09:21
    • Replies: 3
    • Views: 2,451
    10th July 2003, 11:44 Go to last post