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Threads 21871 to 21900 of 22274

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: lattice MA5 with view logic

    Started by brutus, 20th October 2003 21:39
    • Replies: 1
    • Views: 1,155
    22nd October 2003, 04:19 Go to last post
  2. Closed: How to copy a protected PAL, GAL and CPLD

    Started by weeyndha, 19th October 2003 15:44
    • Replies: 3
    • Views: 4,136
    21st October 2003, 19:10 Go to last post
  3. Closed: coding style for verilog and vhdl

    Started by rohit_tech, 16th October 2003 13:24
    • Replies: 2
    • Views: 1,908
    21st October 2003, 02:35 Go to last post
  4. Closed: Prescaler - What is going on?

    Started by Mercury, 20th October 2003 20:55
    • Replies: 2
    • Views: 4,724
    21st October 2003, 01:04 Go to last post
  5. Closed: QDR SRAM Memmory Controller

    Started by mami_hacky, 18th October 2003 07:17
    • Replies: 1
    • Views: 1,753
    20th October 2003, 22:49 Go to last post
  6. Closed: small IP core in altera cpld?

    Started by 7rots51, 19th October 2003 18:18
    • Replies: 1
    • Views: 1,973
    19th October 2003, 19:45 Go to last post
  7. Closed: Why all phases of clock placement operate on GCR in ISE 6.1?

    Started by zcq, 19th October 2003 12:21
    • Replies: 1
    • Views: 1,292
    19th October 2003, 13:24 Go to last post
  8. Closed: VHDL circuit for detecting 8 bit inputs changes

    Started by Mercury, 9th October 2003 20:04
    • Replies: 3
    • Views: 1,416
    19th October 2003, 07:42 Go to last post
  9. Closed: Help: design of the OPB peripheral block for PowerPC..

    Started by seamless, 16th October 2003 20:16
    • Replies: 0
    • Views: 1,213
    16th October 2003, 20:16 Go to last post
  10. Closed: attribute LOC - help needed

    Started by Vonn, 15th October 2003 09:50
    • Replies: 2
    • Views: 3,522
    16th October 2003, 20:03 Go to last post
  11. Closed: Using the NAT9914 Chip with FPGAs for GPIB design

    Started by cssheu, 15th October 2003 17:26
    • Replies: 0
    • Views: 2,288
    15th October 2003, 17:26 Go to last post
    • Replies: 1
    • Views: 1,963
    15th October 2003, 16:46 Go to last post
  12. Closed: how to simulate digital ic

    Started by ash, 10th October 2003 21:16
    • Replies: 6
    • Views: 1,644
    15th October 2003, 10:03 Go to last post
  13. Closed: ByteBlasterII schemes on the net

    Started by isgaspar, 14th October 2003 12:50
    • Replies: 1
    • Views: 1,962
    15th October 2003, 02:57 Go to last post
  14. Closed: Synplicitys Synplify V7.3.3 is out !

    Started by ramesh, 7th October 2003 10:40
    • Replies: 2
    • Views: 1,865
    14th October 2003, 13:22 Go to last post
  15. Closed: Help: IP exchange for DMAC (PL080) from ARM primecell

    Started by IC-SOC, 14th October 2003 12:04
    • Replies: 0
    • Views: 1,392
    14th October 2003, 12:04 Go to last post
  16. Closed: Super Newbie - whats FPGA?

    Started by Bukitoo, 14th October 2003 05:43
    • Replies: 1
    • Views: 1,405
    14th October 2003, 06:41 Go to last post
  17. Closed: MAX+PLUS, compilation statistics.

    Started by elektryk, 13th October 2003 19:25
    • Replies: 1
    • Views: 2,628
    13th October 2003, 21:10 Go to last post
  18. Closed: How to come up with calculation of Xilinx System Gate?

    Started by simon2kk, 13th October 2003 02:02
    • Replies: 3
    • Views: 2,924
    13th October 2003, 09:12 Go to last post
  19. Closed: EDK 6.1i EVAL - xlinic with this pack?

    Started by apollo, 9th October 2003 07:23
    • Replies: 1
    • Views: 1,797
    10th October 2003, 12:42 Go to last post
  20. Closed: Question about Altera EP910 specification

    Started by elektryk, 10th October 2003 11:04
    • Replies: 0
    • Views: 1,395
    10th October 2003, 11:04 Go to last post
  21. Closed: Help with Synplify Modular Design

    Started by fede76pc, 10th October 2003 08:26
    • Replies: 0
    • Views: 1,383
    10th October 2003, 08:26 Go to last post
  22. Closed: How to decrease time slacks in Synplify Pro?

    Started by mycentury2003, 28th September 2003 06:14
    • Replies: 4
    • Views: 1,723
    10th October 2003, 08:16 Go to last post
  23. Closed: X_linx ISE 6.1i Problem - bad nph file

    Started by dingo, 5th October 2003 01:55
    • Replies: 11
    • Views: 3,759
    9th October 2003, 22:36 Go to last post
  24. Closed: How to simulate a digital(or mixed) circuit with Matlab?

    Started by kukurigu, 2nd October 2003 21:19
    • Replies: 5
    • Views: 7,118
    9th October 2003, 17:17 Go to last post
  25. Closed: Xilinx 9500 series CPLD PWM code problem

    Started by Mercury, 7th October 2003 20:13
    • Replies: 3
    • Views: 3,502
    9th October 2003, 11:32 Go to last post
  26. Closed: Implementing lvds mega function

    Started by sul, 28th September 2003 21:30
    • Replies: 1
    • Views: 1,575
    8th October 2003, 10:20 Go to last post
  27. Closed: How to build a programmer for ALTERA EPM7256EQC160-12 ?

    Started by sunjimmy, 5th October 2003 17:51
    • Replies: 4
    • Views: 1,651
    8th October 2003, 07:29 Go to last post
  28. Closed: HOw to split bus in FPGA Adv using "Block Diagram' ent

    Started by always@smart, 3rd October 2003 16:19
    • Replies: 3
    • Views: 1,807
    7th October 2003, 16:32 Go to last post
  29. Closed: Using PAL/GAL as 74C926 IC

    Started by killex, 6th October 2003 12:10
    • Replies: 3
    • Views: 3,210
    6th October 2003, 17:37 Go to last post