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Threads 1501 to 1530 of 22858

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Procedure with sequential process edge detection

    Started by nsgil85, 21st February 2017 09:01
    • Replies: 7
    • Views: 776
    21st February 2017, 13:01 Go to last post
  2. Closed: When is the VHDL pointer useful?

    Started by matrixofdynamism, 20th February 2017 16:45
    • Replies: 5
    • Views: 1,002
    21st February 2017, 10:41 Go to last post
  3. Closed: fpga for dsp in vhdl language

    Started by maryam2015, 19th January 2017 11:34
    • Replies: 10
    • Views: 1,331
    21st February 2017, 06:00 Go to last post
  4. Closed: Help in verilog for MIPS design

    Started by Adnan86, 6th February 2017 10:21
    • Replies: 7
    • Views: 1,694
    21st February 2017, 05:55 Go to last post
  5. Closed: How to see XDC Templates in Vivado 2016.1 ?

    Started by msdarvishi, 21st February 2017 01:12
    • Replies: 1
    • Views: 616
    21st February 2017, 02:37 Go to last post
    • Replies: 4
    • Views: 1,995
    20th February 2017, 08:11 Go to last post
  6. Closed: Clock Synchronization with FPGA

    Started by rayhh27, 7th February 2017 13:58
    • Replies: 7
    • Views: 1,679
    19th February 2017, 09:14 Go to last post
    • Replies: 7
    • Views: 1,103
    18th February 2017, 20:28 Go to last post
  7. Closed: Image rotation algorithm - Forward vs Backward mapping

    Started by shaiko, 17th February 2017 19:53
    • Replies: 4
    • Views: 1,355
    18th February 2017, 03:25 Go to last post
    • Replies: 4
    • Views: 1,223
    16th February 2017, 16:46 Go to last post
  8. Closed: how to interface ADC7656 with altera max

    Started by panimalar, 5th January 2017 11:15
    • Replies: 11
    • Views: 1,224
    16th February 2017, 08:52 Go to last post
  9. Closed: Multiples VHDL processes reading from one file

    Started by shaiko, 14th February 2017 22:57
    • Replies: 5
    • Views: 821
    15th February 2017, 08:11 Go to last post
  10. Closed: Generating 2 clock pulses in VHDL

    Started by MrMuffins, 14th February 2017 20:20
    • Replies: 3
    • Views: 1,032
    14th February 2017, 23:14 Go to last post
  11. Closed: How many LUTs can create a 32:1 MUX?

    Started by bchcodez, 14th February 2017 15:05
    • Replies: 4
    • Views: 2,589
    14th February 2017, 23:11 Go to last post
  12. Closed: USB Blaster altera programming error "Unable to scan device chain"

    Started by rsm9692, 13th February 2017 12:42
    • Replies: 7
    • Views: 6,041
    14th February 2017, 15:20 Go to last post
  13. Closed: How to design a frequency adjustable NCO?

    Started by bravoegg, 13th February 2017 09:31
    • Replies: 6
    • Views: 1,148
    13th February 2017, 17:31 Go to last post
  14. Closed: Debugging KC705 board

    Started by beginner_EDA, 7th February 2017 15:54
    • Replies: 10
    • Views: 1,497
    13th February 2017, 17:08 Go to last post
  15. Closed: string and line exact definitions

    Started by Binome, 10th February 2017 16:29
    • Replies: 10
    • Views: 775
    13th February 2017, 11:35 Go to last post
  16. Closed: Xilinx system generator IP cores in IP integrator and SDK

    Started by sai_shashi, 13th February 2017 11:13
    • Replies: 0
    • Views: 508
    13th February 2017, 11:13 Go to last post
  17. Closed: SPI Flash programming

    Started by Vlad., 13th February 2017 02:00
    • Replies: 3
    • Views: 882
    13th February 2017, 07:58 Go to last post
  18. Closed: Need Some advice to write verilog code for CAM memory

    Started by Adnan86, 12th February 2017 16:57
    • Replies: 6
    • Views: 2,747
    12th February 2017, 20:24 Go to last post
  19. Closed: Round Robin Arbiter with ring counter

    Started by Abhi3005, 9th February 2017 06:47
    • Replies: 10
    • Views: 3,097
    12th February 2017, 17:27 Go to last post
  20. [SOLVED]Closed: FPGA IP cores used in production, Any royalties involved?

    Started by JulianCas, 10th February 2017 18:31
    • Replies: 2
    • Views: 612
    11th February 2017, 02:18 Go to last post
  21. Closed: Advice on usage of Altera FFT IP core

    Started by logari84, 10th February 2017 19:43
    • Replies: 0
    • Views: 885
    10th February 2017, 19:43 Go to last post
  22. Closed: DSP48E1 - Warning: OPMODE Input Warning

    Started by FuzzySNR, 8th February 2017 02:36
    • Replies: 4
    • Views: 2,997
    10th February 2017, 16:28 Go to last post
    • Replies: 9
    • Views: 1,149
    9th February 2017, 22:19 Go to last post
  23. Closed: fsm design for sequance detect (please help me)

    Started by jango123, 3rd February 2017 22:51
    2 Pages
    1 2
    • Replies: 27
    • Views: 3,717
    9th February 2017, 22:19 Go to last post
  24. Closed: Looking for some explanation (VHDL Coding)

    Started by sonika111, 2nd February 2017 20:40
    • Replies: 15
    • Views: 1,175
    8th February 2017, 17:39 Go to last post
  25. Closed: How to extract the net delay of a routed net in Vivado?

    Started by msdarvishi, 7th February 2017 22:37
    • Replies: 1
    • Views: 2,111
    7th February 2017, 23:28 Go to last post
  26. Closed: synthesizing takes too long time

    Started by p11, 7th February 2017 13:07
    • Replies: 6
    • Views: 763
    7th February 2017, 20:18 Go to last post