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Threads 1501 to 1530 of 22389

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: multi microblaze issue.

    Started by coshy, 2nd August 2016 09:13
    • Replies: 3
    • Views: 455
    3rd August 2016, 02:38 Go to last post
  2. Closed: what does explicity specify the ram access type mean ?

    Started by coshy, 2nd August 2016 01:21
    • Replies: 3
    • Views: 572
    2nd August 2016, 08:35 Go to last post
  3. Closed: Cant this vhdl program be viewed in simulation?

    Started by Anwesa Roy, 1st August 2016 11:44
    • Replies: 5
    • Views: 561
    1st August 2016, 14:15 Go to last post
  4. Closed: CPLD USB Jtag Programmer

    Started by 5arid, 27th July 2016 08:46
    • Replies: 1
    • Views: 1,204
    1st August 2016, 08:43 Go to last post
  5. Closed: Can I use vivado HLS instead of synphony c compiler?

    Started by coshy, 1st August 2016 07:09
    • Replies: 0
    • Views: 489
    1st August 2016, 07:09 Go to last post
  6. Closed: Flashing of backlight of 2 line character LCD display

    Started by hobbyiclearner, 29th July 2016 11:25
    • Replies: 3
    • Views: 492
    30th July 2016, 09:51 Go to last post
    • Replies: 7
    • Views: 1,370
    30th July 2016, 00:38 Go to last post
  7. Closed: VHDL SIGNAL sequence timing

    Started by metcal, 29th July 2016 06:14
    • Replies: 2
    • Views: 432
    29th July 2016, 08:09 Go to last post
  8. Closed: Unable to understand a LCD module controller code :(

    Started by hobbyiclearner, 7th June 2016 18:44
    2 Pages
    1 2
    • Replies: 38
    • Views: 2,328
    29th July 2016, 07:09 Go to last post
  9. Closed: Time to Digital Converter

    Started by AymKar, 26th July 2016 04:56
    • Replies: 9
    • Views: 734
    29th July 2016, 05:45 Go to last post
  10. Closed: What is nios ii? (Altera DE0)

    Started by omerysmi, 23rd July 2016 15:53
    • Replies: 6
    • Views: 659
    28th July 2016, 17:04 Go to last post
  11. [SOLVED]Closed: how to use a dma controller with microblaze processor in vivado?

    Started by hamidkavianathar, 25th July 2016 10:23
    • Replies: 6
    • Views: 1,238
    28th July 2016, 01:48 Go to last post
  12. Closed: Resource and execution time estimation without FPGA board

    Started by marcelos, 26th July 2016 18:09
    • Replies: 3
    • Views: 612
    27th July 2016, 22:22 Go to last post
  13. [SOLVED]Closed: Ways to configure Ethernet PHY registers over mdio+mdc interface

    Started by dpaul, 21st July 2016 22:10
    • Replies: 7
    • Views: 2,165
    27th July 2016, 19:19 Go to last post
  14. Closed: Xilinx AXI_LITE_IPIF interface vivado issue

    Started by coshy, 27th July 2016 15:55
    • Replies: 1
    • Views: 668
    27th July 2016, 17:55 Go to last post
  15. Closed: How does this vhdl code for up and down counting work?

    Started by Anwesa Roy, 27th July 2016 09:02
    • Replies: 1
    • Views: 582
    27th July 2016, 09:17 Go to last post
  16. Closed: Microblaze SDK problem

    Started by ya_montazar, 25th July 2016 07:13
    • Replies: 3
    • Views: 696
    27th July 2016, 02:08 Go to last post
  17. Closed: Altera QIP file - is it a must ?

    Started by shaiko, 26th July 2016 15:08
    • Replies: 1
    • Views: 1,255
    26th July 2016, 15:22 Go to last post
  18. Closed: Replicated logic optimization

    Started by rac70, 23rd July 2016 09:42
    • Replies: 11
    • Views: 697
    26th July 2016, 07:20 Go to last post
  19. Closed: Integrating custom coprocessor with ZYNQ

    Started by arkoudinos, 23rd July 2016 19:01
    • Replies: 3
    • Views: 789
    26th July 2016, 06:50 Go to last post
  20. Closed: Altera ALTERA_MULT_ADD registering the multiplier output

    Started by shaiko, 25th July 2016 10:43
    • Replies: 6
    • Views: 721
    26th July 2016, 06:39 Go to last post
    • Replies: 10
    • Views: 1,361
    25th July 2016, 15:40 Go to last post
  21. Closed: Configuration memory readback

    Started by nidhints, 25th July 2016 04:25
    • Replies: 2
    • Views: 537
    25th July 2016, 07:31 Go to last post
  22. [SOLVED]Closed: vhdl coding test vectors for pipe lining

    Started by vishushru, 23rd July 2016 13:44
    • Replies: 3
    • Views: 402
    24th July 2016, 10:53 Go to last post
  23. [SOLVED]Closed: how to read data from a ddr3 sdram?

    Started by hamidkavianathar, 28th June 2016 06:46
    • Replies: 14
    • Views: 1,209
    23rd July 2016, 07:13 Go to last post
  24. Closed: how to find the phase of the signal in fft??

    Started by sandy3129, 14th July 2016 20:15
    • Replies: 7
    • Views: 620
    22nd July 2016, 18:13 Go to last post
  25. Closed: AXI FIFO does not work

    Started by u24c02, 21st July 2016 02:15
    • Replies: 1
    • Views: 449
    22nd July 2016, 04:00 Go to last post
  26. Closed: BPSK mapper for OFDM modulation

    Started by Kosyas41, 20th July 2016 12:13
    • Replies: 3
    • Views: 470
    21st July 2016, 16:45 Go to last post