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Threads 1501 to 1530 of 22239

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Pure Combinational ALU (Tasks : Add,Mul and Sub)

    Started by Morell, 4th June 2016 21:26
    • Replies: 4
    • Views: 619
    5th June 2016, 14:01 Go to last post
  2. Closed: Generating a pulse with 1ns pulse duration in fpga

    Started by vahidsh, 14th May 2016 04:04
    • Replies: 9
    • Views: 1,402
    4th June 2016, 12:59 Go to last post
  3. [SOLVED]Closed: How to solve the unable to detect any supported xilinx cable?

    Started by u24c02, 3rd June 2016 14:14
    • Replies: 4
    • Views: 908
    3rd June 2016, 16:06 Go to last post
  4. Closed: Random question on Verilog

    Started by abhisheknayak95, 30th May 2016 09:30
    • Replies: 14
    • Views: 964
    3rd June 2016, 03:52 Go to last post
  5. Closed: Quartus prime software

    Started by p11, 2nd June 2016 18:16
    • Replies: 5
    • Views: 597
    2nd June 2016, 22:21 Go to last post
  6. Closed: 12 bit counter won't scale up to more bits

    Started by GarryM, 31st May 2016 22:17
    • Replies: 13
    • Views: 743
    2nd June 2016, 19:08 Go to last post
  7. Closed: Where is Timing Analyzer Stanalone in ISE 14.7?

    Started by msdarvishi, 1st June 2016 18:25
    • Replies: 2
    • Views: 404
    2nd June 2016, 00:57 Go to last post
  8. Closed: d-flip flop- post synthesis timing simulation

    Started by preethi19, 30th May 2016 05:50
    • Replies: 3
    • Views: 649
    31st May 2016, 23:52 Go to last post
  9. Closed: timing constraint- output delay

    Started by preethi19, 30th May 2016 05:09
    • Replies: 3
    • Views: 883
    31st May 2016, 23:16 Go to last post
  10. [SOLVED]Closed: Vivado timing constraint

    Started by preethi19, 29th May 2016 06:57
    • Replies: 2
    • Views: 686
    30th May 2016, 21:10 Go to last post
  11. Closed: Could you recommend a SIMULATION-oriented book for VHDL?

    Started by ZX_Spectrum, 28th May 2016 22:14
    • Replies: 6
    • Views: 626
    30th May 2016, 02:02 Go to last post
  12. Closed: modification of braun multiplier

    Started by braun1234, 25th May 2016 08:06
    • Replies: 6
    • Views: 529
    28th May 2016, 16:12 Go to last post
  13. Closed: I want to calculate my kernel ideal execution time with fmax.

    Started by chounght, 28th May 2016 10:10
    • Replies: 0
    • Views: 389
    28th May 2016, 10:10 Go to last post
  14. Closed: How can I use local memory of altera opencl kernel?.

    Started by chounght, 28th May 2016 10:06
    • Replies: 0
    • Views: 375
    28th May 2016, 10:06 Go to last post
  15. Closed: spartan- 3an xc3s700an I/O PINS HELP

    Started by mv09021991, 26th May 2016 07:29
    • Replies: 4
    • Views: 492
    26th May 2016, 16:45 Go to last post
  16. Closed: Basic concept of Transceiver in FPGA

    Started by beginner_EDA, 25th May 2016 13:36
    • Replies: 1
    • Views: 469
    25th May 2016, 16:22 Go to last post
  17. Closed: how to implement ipfilter on fpga?

    Started by hamidkavianathar, 24th May 2016 09:25
    • Replies: 4
    • Views: 569
    25th May 2016, 07:14 Go to last post
  18. Closed: Timing Summary in Xillinx

    Started by MSAKARIM, 23rd May 2016 20:41
    • Replies: 1
    • Views: 402
    24th May 2016, 17:06 Go to last post
    • Replies: 6
    • Views: 804
    24th May 2016, 16:24 Go to last post
  19. Closed: How to characterize the CARRY4 primitive in Virtex-5 FPGA

    Started by msdarvishi, 21st May 2016 00:34
    • Replies: 3
    • Views: 454
    24th May 2016, 16:10 Go to last post
  20. Closed: storing values from vhdl wave

    Started by 214, 22nd May 2016 06:14
    • Replies: 12
    • Views: 865
    24th May 2016, 12:54 Go to last post
  21. [SOLVED]Closed: Unstable state machine

    Started by snipex, 23rd May 2016 12:27
    • Replies: 6
    • Views: 596
    24th May 2016, 09:03 Go to last post
  22. Closed: how to bring up the slave interface port on a microblaze ??

    Started by anilineda, 24th May 2016 06:04
    • Replies: 2
    • Views: 417
    24th May 2016, 07:37 Go to last post
  23. Closed: Two Dimension memory

    Started by Serwan Bamerni, 23rd May 2016 21:06
    • Replies: 3
    • Views: 480
    24th May 2016, 00:14 Go to last post
  24. Closed: Problem to implement the design

    Started by Jaiko, 23rd May 2016 16:28
    • Replies: 3
    • Views: 371
    23rd May 2016, 16:55 Go to last post
  25. Closed: Duty Cycle by using VHDL

    Started by Jaiko, 21st May 2016 14:01
    • Replies: 12
    • Views: 1,982
    22nd May 2016, 20:24 Go to last post
  26. Closed: verilog code to find max and min in an input..

    Started by MR.sam, 22nd May 2016 09:22
    • Replies: 5
    • Views: 1,765
    22nd May 2016, 12:01 Go to last post