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Threads 1501 to 1530 of 22711

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: FPGA Configuration volatile/Flash

    Started by beginner_EDA, 2nd December 2016 10:06
    • Replies: 4
    • Views: 690
    6th December 2016, 11:38 Go to last post
  2. Closed: Help with accessing interal RAM of cyclone II fpga

    Started by PieterDeMan, 1st December 2016 11:48
    • Replies: 4
    • Views: 724
    6th December 2016, 11:34 Go to last post
  3. Closed: FFT code question VHDL

    Started by rayhh27, 3rd December 2016 15:54
    • Replies: 4
    • Views: 842
    5th December 2016, 19:01 Go to last post
    • Replies: 13
    • Views: 1,749
    5th December 2016, 17:49 Go to last post
  4. Closed: implementation function in VHDL using modelsim

    Started by osamahatter, 4th December 2016 19:26
    • Replies: 3
    • Views: 725
    5th December 2016, 05:43 Go to last post
  5. [SOLVED]Closed: Assignment of signal to same signal VHDL

    Started by CataM, 4th December 2016 02:27
    • Replies: 10
    • Views: 1,194
    5th December 2016, 00:08 Go to last post
  6. [SOLVED]Closed: adder output is always at high impedance state

    Started by rakeshk.r, 3rd December 2016 20:26
    • Replies: 5
    • Views: 868
    4th December 2016, 16:37 Go to last post
  7. Closed: ERROR:Place:1239 The following IO are not locked:

    Started by taaha651, 2nd December 2016 21:27
    • Replies: 2
    • Views: 773
    3rd December 2016, 04:58 Go to last post
  8. Closed: FM modulation and demodulation on FPGA

    Started by Kosyas41, 2nd December 2016 11:20
    • Replies: 1
    • Views: 839
    2nd December 2016, 17:26 Go to last post
  9. Closed: how to implement the power of 2 of a floating number?

    Started by milan.km, 2nd December 2016 16:09
    • Replies: 1
    • Views: 716
    2nd December 2016, 17:08 Go to last post
    • Replies: 6
    • Views: 1,035
    1st December 2016, 18:28 Go to last post
    • Replies: 5
    • Views: 1,833
    1st December 2016, 09:54 Go to last post
  10. [SOLVED]Closed: Does adding timing constraints needs rerunning synth and implementation ?

    Started by UltraGreen, 30th November 2016 08:25
    • Replies: 3
    • Views: 747
    1st December 2016, 07:13 Go to last post
  11. Closed: how to reduce congestion in a particular clb

    Started by UltraGreen, 24th November 2016 10:46
    • Replies: 8
    • Views: 852
    30th November 2016, 17:42 Go to last post
  12. Closed: how to use .coe file in xilinx

    Started by emerson_11, 16th November 2016 09:26
    • Replies: 4
    • Views: 3,302
    30th November 2016, 15:29 Go to last post
  13. Closed: to know fpga is faulty or not..

    Started by dipin, 28th November 2016 13:13
    • Replies: 10
    • Views: 1,399
    30th November 2016, 10:28 Go to last post
  14. Closed: VHDL exercise : 256Bytes RAM

    Started by Morell, 25th November 2016 11:20
    • Replies: 12
    • Views: 1,286
    30th November 2016, 06:50 Go to last post
  15. Closed: binary point location after ifft caculation?

    Started by bravoegg, 29th November 2016 09:20
    • Replies: 1
    • Views: 573
    30th November 2016, 04:35 Go to last post
  16. Closed: [VIVADO SDK] Issue founded during debuging

    Started by flote21, 29th November 2016 17:21
    • Replies: 1
    • Views: 712
    29th November 2016, 22:42 Go to last post
  17. [SOLVED]Closed: Design Synchronization question and Verilog Code Review

    Started by redsees, 24th November 2016 18:57
    • Replies: 15
    • Views: 1,614
    29th November 2016, 18:06 Go to last post
  18. [SOLVED]Closed: is it safe to use 2 separate buffer for clock domain crossing?

    Started by LatticeSemiconductor, 29th November 2016 11:35
    • Replies: 2
    • Views: 656
    29th November 2016, 17:18 Go to last post
  19. [SOLVED]Closed: Converted tricell instance critical warning

    Started by flote21, 18th November 2016 12:11
    • Replies: 6
    • Views: 5,184
    29th November 2016, 10:54 Go to last post
  20. Closed: comparing numbers in vhdl

    Started by p11, 26th November 2016 21:55
    • Replies: 11
    • Views: 1,386
    29th November 2016, 09:17 Go to last post
  21. Closed: parallel processing using fpgas

    Started by emerson_11, 29th November 2016 05:40
    • Replies: 2
    • Views: 595
    29th November 2016, 08:10 Go to last post
  22. Closed: Datapath Design Using ROM memory

    Started by Alex_Ivan, 28th November 2016 23:24
    • Replies: 4
    • Views: 593
    29th November 2016, 02:18 Go to last post
  23. Closed: how to use this board?

    Started by RETGT, 24th November 2016 10:03
    • Replies: 8
    • Views: 988
    28th November 2016, 20:21 Go to last post
  24. Closed: [NEED HELP ARGENT] 8-bit CPU system

    Started by kitchong, 27th November 2016 09:57
    • Replies: 3
    • Views: 768
    28th November 2016, 20:04 Go to last post
  25. Closed: Damaged grounding pin of FPGA ACTEL A3P1000

    Started by princez, 28th November 2016 06:41
    • Replies: 2
    • Views: 602
    28th November 2016, 17:47 Go to last post
  26. Closed: Newbie question: PLL on DE2 board (Cyclone 2) and VGA 1920x1200

    Started by iqster, 26th November 2016 06:51
    • Replies: 3
    • Views: 853
    27th November 2016, 04:57 Go to last post
    • Replies: 9
    • Views: 2,040
    25th November 2016, 15:40 Go to last post