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Threads 1501 to 1530 of 22807

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Synthesizable Verilog

    Started by AKSHAYNIMBAL, 28th January 2017 18:52
    • Replies: 4
    • Views: 761
    30th January 2017, 17:58 Go to last post
  2. Closed: How can i simulate this vhdl code?

    Started by jacksparrow93, 30th January 2017 00:06
    • Replies: 6
    • Views: 1,985
    30th January 2017, 17:50 Go to last post
  3. Closed: Reading data from MIPI CSI-2 camera sensor

    Started by malkauns, 28th January 2017 09:21
    • Replies: 1
    • Views: 1,347
    30th January 2017, 17:18 Go to last post
  4. Closed: VHDL Native Maximum function

    Started by shaiko, 27th January 2017 17:18
    • Replies: 4
    • Views: 6,440
    29th January 2017, 18:23 Go to last post
    • Replies: 2
    • Views: 728
    27th January 2017, 17:48 Go to last post
  5. Closed: Describing a state machine in requirements

    Started by Fixed_point, 27th January 2017 10:07
    • Replies: 2
    • Views: 710
    27th January 2017, 13:40 Go to last post
  6. Closed: Reference design to test 10 Gig ethernet on kc705

    Started by beginner_EDA, 26th January 2017 11:37
    • Replies: 0
    • Views: 709
    26th January 2017, 11:37 Go to last post
  7. Closed: Digita audio and FPGA

    Started by andrea_mori, 21st January 2017 18:22
    • Replies: 18
    • Views: 2,726
    26th January 2017, 01:46 Go to last post
    • Replies: 3
    • Views: 1,100
    25th January 2017, 07:03 Go to last post
  8. Closed: help in understanding code (verilog)

    Started by UltraGreen, 25th January 2017 06:41
    • Replies: 1
    • Views: 716
    25th January 2017, 06:45 Go to last post
  9. [SOLVED]Closed: How to PMI in Vivado

    Started by LatticeSemiconductor, 23rd January 2017 18:12
    • Replies: 5
    • Views: 850
    24th January 2017, 09:53 Go to last post
  10. Closed: Next step in learning computer architecture

    Started by zbedoz, 22nd January 2017 15:47
    • Replies: 4
    • Views: 744
    23rd January 2017, 10:25 Go to last post
  11. Closed: Configuration Cyclone V 5CEBA9F23C8N

    Started by Coder_number_13, 22nd January 2017 13:44
    • Replies: 1
    • Views: 747
    22nd January 2017, 14:08 Go to last post
  12. Closed: doubt with cic filter

    Started by dipin, 21st January 2017 08:33
    • Replies: 3
    • Views: 1,081
    21st January 2017, 12:15 Go to last post
  13. [SOLVED]Closed: Verilog Design Question

    Started by redsees, 19th January 2017 16:17
    • Replies: 7
    • Views: 1,081
    21st January 2017, 10:54 Go to last post
  14. Closed: [VHDL NEXYS 3] new to this language, need help

    Started by jacksparrow93, 7th January 2017 15:32
    • Replies: 8
    • Views: 1,117
    21st January 2017, 10:29 Go to last post
  15. Closed: please help in testbench in vhdl

    Started by maryam2015, 20th January 2017 19:36
    • Replies: 5
    • Views: 897
    21st January 2017, 08:51 Go to last post
  16. Closed: Web Server design using Xilinx EDK 10.1

    Started by roshan12, 19th January 2017 10:12
    • Replies: 1
    • Views: 688
    20th January 2017, 13:50 Go to last post
  17. Closed: Very strange simulation behavior

    Started by shaiko, 19th January 2017 17:23
    • Replies: 6
    • Views: 823
    19th January 2017, 23:23 Go to last post
  18. Closed: VHDL 2008 bus inversion

    Started by shaiko, 19th January 2017 11:39
    • Replies: 1
    • Views: 594
    19th January 2017, 13:27 Go to last post
    • Replies: 4
    • Views: 1,111
    18th January 2017, 16:46 Go to last post
  19. Closed: readmemh usage for file size more than 32KB

    Started by ritesh.joshi, 16th January 2017 13:36
    • Replies: 4
    • Views: 1,108
    17th January 2017, 08:21 Go to last post
  20. Closed: vedic multiplier using barrel shifter

    Started by sri4444, 16th January 2017 16:45
    • Replies: 2
    • Views: 861
    17th January 2017, 04:54 Go to last post
  21. Closed: ISE 14.6 - iMPACT crashes everytime it starts

    Started by pigtwo, 7th January 2017 23:29
    • Replies: 5
    • Views: 1,286
    17th January 2017, 01:54 Go to last post
  22. Closed: i need verilog code to filter out ethernet MAC

    Started by vivek_vlsi, 15th January 2017 16:45
    • Replies: 2
    • Views: 1,198
    16th January 2017, 09:50 Go to last post
  23. Closed: FFT core design on FPGA board

    Started by mohamed_shfat, 12th January 2017 19:25
    • Replies: 12
    • Views: 1,871
    16th January 2017, 09:43 Go to last post
  24. Closed: Glitches on counter (Quartus Ii and modelsim)

    Started by AlexisC, 15th January 2017 12:29
    • Replies: 5
    • Views: 906
    15th January 2017, 19:25 Go to last post
  25. Closed: PRBS output values vhdl

    Started by Kosyas41, 15th January 2017 13:23
    • Replies: 3
    • Views: 829
    15th January 2017, 14:51 Go to last post
  26. Closed: I am new to NIOS II. Need help for my requirement.

    Started by niks, 7th January 2017 01:33
    • Replies: 4
    • Views: 1,008
    14th January 2017, 05:25 Go to last post
  27. [SOLVED]Closed: Analizing a VHDL program code

    Started by Janoy66, 11th January 2017 10:56
    • Replies: 13
    • Views: 1,326
    13th January 2017, 20:33 Go to last post