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Threads 1501 to 1530 of 22465

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: how to store values in rom in sys gen and call when required?

    Started by sandy3129, 22nd August 2016 15:34
    • Replies: 18
    • Views: 970
    30th August 2016, 08:28 Go to last post
  2. Closed: Bits to be set for Reverse Loopback Mode in Altera Arria 10

    Started by biju4u90, 30th August 2016 07:14
    • Replies: 0
    • Views: 361
    30th August 2016, 07:14 Go to last post
    • Replies: 3
    • Views: 644
    29th August 2016, 17:27 Go to last post
  3. [SOLVED]Closed: Can someone please tell me the meaning of this verilog code:

    Started by RaviT, 28th August 2016 08:17
    • Replies: 3
    • Views: 453
    29th August 2016, 17:01 Go to last post
  4. Closed: Back annotating QSF into pin-planner

    Started by shaiko, 29th August 2016 16:58
    • Replies: 0
    • Views: 341
    29th August 2016, 16:58 Go to last post
  5. [SOLVED]Closed: Verilog: What is the proper way to synthesis a JK flip flop with reset?

    Started by ammar_kurd, 29th August 2016 15:30
    • Replies: 1
    • Views: 837
    29th August 2016, 16:08 Go to last post
  6. [SOLVED]Closed: Synario FutureNet 6.10

    Started by Zag4cpld, 28th August 2016 17:04
    • Replies: 2
    • Views: 679
    29th August 2016, 14:01 Go to last post
  7. [SOLVED]Closed: Driving MMCM through ibufds_GTE3

    Started by UltraGreen, 29th August 2016 08:15
    • Replies: 1
    • Views: 1,763
    29th August 2016, 13:32 Go to last post
  8. Closed: serial to parallel while maintaining a constant clock

    Started by player80, 29th August 2016 01:15
    • Replies: 1
    • Views: 343
    29th August 2016, 01:42 Go to last post
  9. Closed: VHDL array shift register

    Started by shaiko, 28th August 2016 09:48
    • Replies: 3
    • Views: 1,418
    28th August 2016, 16:27 Go to last post
  10. Closed: [moved] Tutorial of BUS structure and functionality

    Started by sarit8, 25th August 2016 12:53
    • Replies: 6
    • Views: 639
    28th August 2016, 09:23 Go to last post
  11. Closed: is it worth it to learn Chisel HDL

    Started by ammar_kurd, 27th August 2016 13:46
    • Replies: 3
    • Views: 824
    28th August 2016, 03:30 Go to last post
  12. Closed: DP838 PHY transceiver and crc problem!!

    Started by STU_KNTU, 15th August 2016 12:33
    • Replies: 4
    • Views: 613
    27th August 2016, 12:56 Go to last post
  13. Closed: Xilinx HW-130/HW-120 Programming Adapters

    Started by Zag4cpld, 25th August 2016 15:15
    • Replies: 1
    • Views: 501
    27th August 2016, 07:11 Go to last post
  14. Closed: Testbench file in VHDL. Help required

    Started by Vijay Vinay, 23rd August 2016 15:54
    • Replies: 7
    • Views: 907
    26th August 2016, 16:22 Go to last post
  15. Closed: FWFT FIFO performance penalty

    Started by shaiko, 25th August 2016 18:14
    • Replies: 8
    • Views: 672
    26th August 2016, 14:44 Go to last post
  16. [SOLVED]Closed: IOSTANDARDS for clocks

    Started by UltraGreen, 26th August 2016 11:35
    • Replies: 2
    • Views: 263
    26th August 2016, 14:33 Go to last post
    • Replies: 5
    • Views: 762
    26th August 2016, 14:29 Go to last post
  17. Closed: Full adder with 3 input signals (vectors)

    Started by Rorsh14, 25th August 2016 07:20
    • Replies: 7
    • Views: 677
    25th August 2016, 15:56 Go to last post
  18. Closed: set up and hold fixing in FPGA

    Started by biju4u90, 24th August 2016 10:36
    • Replies: 9
    • Views: 991
    25th August 2016, 10:17 Go to last post
  19. Closed: [moved] Creating test bench for AXI bus

    Started by sarit8, 25th August 2016 08:21
    • Replies: 1
    • Views: 795
    25th August 2016, 10:15 Go to last post
  20. Closed: What does this value mean ?

    Started by Anwesa Roy, 23rd August 2016 10:14
    • Replies: 5
    • Views: 543
    24th August 2016, 06:47 Go to last post
  21. [SOLVED]Closed: FT2232H in Sync FIFO Mode - TXE# stuck high

    Started by AlexisB, 4th August 2016 10:30
    2 Pages
    1 2
    • Replies: 24
    • Views: 3,334
    23rd August 2016, 13:16 Go to last post
  22. Closed: latches irregularity and modelsim&signaltap result didn't agree

    Started by bravoegg, 23rd August 2016 04:29
    • Replies: 5
    • Views: 452
    23rd August 2016, 10:21 Go to last post
  23. Closed: Viewing the memory content of a FIFO

    Started by shaiko, 21st August 2016 23:49
    • Replies: 3
    • Views: 598
    23rd August 2016, 07:45 Go to last post
  24. Closed: What are good Design Patterns for FPGA Designs

    Started by vGoodtimes, 21st August 2016 07:41
    • Replies: 4
    • Views: 678
    23rd August 2016, 04:30 Go to last post
  25. Closed: CPLD ADC oscilloscope

    Started by 5282, 16th August 2016 19:17
    • Replies: 7
    • Views: 1,234
    22nd August 2016, 15:52 Go to last post
    • Replies: 2
    • Views: 479
    22nd August 2016, 15:25 Go to last post
  26. [SOLVED]Closed: Techniques for system modeling in FPGAs

    Started by hobbyiclearner, 18th August 2016 09:22
    • Replies: 15
    • Views: 1,256
    21st August 2016, 08:00 Go to last post
  27. Closed: VHDL editor, synthesis tool and simulator for FPGA's

    Started by GhostInABox, 20th August 2016 03:19
    • Replies: 2
    • Views: 1,082
    20th August 2016, 07:12 Go to last post