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Threads 1501 to 1530 of 22301

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: spi transfer in xilinx

    Started by twainerm, 29th June 2016 08:57
    • Replies: 3
    • Views: 914
    30th June 2016, 09:44 Go to last post
  2. Closed: Synthesis support for 3D HDL arrays

    Started by shaiko, 21st June 2016 23:18
    2 Pages
    1 2
    • Replies: 37
    • Views: 2,056
    29th June 2016, 18:08 Go to last post
  3. Closed: FPGA with SDRAM clk speed

    Started by sherif123, 29th June 2016 14:22
    • Replies: 2
    • Views: 730
    29th June 2016, 17:28 Go to last post
  4. Closed: VHDL_structural_modelling

    Started by Vlsi_design_technology, 29th June 2016 05:08
    • Replies: 6
    • Views: 606
    29th June 2016, 16:01 Go to last post
  5. Closed: Xilinx virtex-6 PCIe wrapper 2.5 error

    Started by minho_ha, 28th June 2016 02:04
    • Replies: 2
    • Views: 517
    28th June 2016, 07:39 Go to last post
    • Replies: 0
    • Views: 510
    27th June 2016, 20:57 Go to last post
  6. Closed: Choosing FPGA Based Embedded System Design as Research Area

    Started by hrlabs, 24th June 2016 12:08
    • Replies: 7
    • Views: 652
    27th June 2016, 11:27 Go to last post
    • Replies: 6
    • Views: 726
    27th June 2016, 10:03 Go to last post
  7. Closed: Can I use xilinx's zynq design block in the simvision?

    Started by u24c02, 27th June 2016 03:13
    • Replies: 1
    • Views: 427
    27th June 2016, 08:26 Go to last post
  8. [SOLVED]Closed: microblaze doesn't work.

    Started by hamidkavianathar, 25th June 2016 09:19
    • Replies: 1
    • Views: 414
    25th June 2016, 16:25 Go to last post
  9. Closed: [moved] FPGA Timing Constraints

    Started by beginner_EDA, 22nd June 2016 11:15
    • Replies: 6
    • Views: 756
    24th June 2016, 10:12 Go to last post
  10. Closed: RAM description in vhdl

    Started by Binome, 22nd June 2016 16:20
    2 Pages
    1 2
    • Replies: 25
    • Views: 1,757
    24th June 2016, 09:07 Go to last post
  11. Closed: How to implement floating point numbers in vhdl

    Started by Anwesa Roy, 15th June 2016 08:53
    2 Pages
    1 2
    • Replies: 21
    • Views: 1,951
    24th June 2016, 03:18 Go to last post
  12. Closed: Ethernet100M via Fpga

    Started by STU_KNTU, 17th June 2016 20:09
    • Replies: 14
    • Views: 1,133
    23rd June 2016, 22:25 Go to last post
  13. Closed: Debugging 2 separate JTAG chain with Vivado

    Started by shaiko, 22nd June 2016 15:06
    • Replies: 6
    • Views: 612
    23rd June 2016, 16:14 Go to last post
  14. Closed: How to get ther intraction between different subsystems...

    Started by velu.plg, 22nd June 2016 10:15
    • Replies: 7
    • Views: 503
    23rd June 2016, 02:05 Go to last post
  15. Closed: Using Xilinx ISE 14.7, PCIe core implementation problem

    Started by minho_ha, 22nd June 2016 03:40
    • Replies: 3
    • Views: 1,181
    22nd June 2016, 22:17 Go to last post
  16. Closed: Quartus Prime Lite: object assigned a value but never read

    Started by hornysquid, 18th June 2016 17:26
    • Replies: 11
    • Views: 1,396
    22nd June 2016, 15:30 Go to last post
  17. Closed: Log wave in Questasim

    Started by bilal_oct, 20th June 2016 18:52
    • Replies: 1
    • Views: 595
    22nd June 2016, 07:23 Go to last post
  18. Closed: Electronic Safe-Lock Design

    Started by carlillos61, 22nd June 2016 04:58
    • Replies: 2
    • Views: 352
    22nd June 2016, 07:22 Go to last post
  19. Closed: how to instruct vivado not to add I/O Buffers.

    Started by hamidkavianathar, 21st June 2016 07:29
    • Replies: 7
    • Views: 2,160
    22nd June 2016, 02:11 Go to last post
  20. Closed: speed up simulation in Questasim

    Started by bilal_oct, 20th June 2016 18:55
    • Replies: 7
    • Views: 1,140
    21st June 2016, 07:12 Go to last post
  21. Closed: How to sample a pulse or a clock into memory?

    Started by UsernameIsValid, 20th June 2016 16:01
    • Replies: 3
    • Views: 338
    20th June 2016, 22:26 Go to last post
  22. [SOLVED]Closed: Processing an incoming stream of 8 bits data

    Started by dpaul, 18th June 2016 00:31
    • Replies: 6
    • Views: 640
    20th June 2016, 20:51 Go to last post
  23. Closed: Xilinx FIFO doesn't work as well.

    Started by u24c02, 18th June 2016 14:00
    • Replies: 5
    • Views: 605
    20th June 2016, 17:01 Go to last post
  24. Closed: When are FPGAs preferred over microcontollers

    Started by hobbyiclearner, 19th June 2016 07:52
    • Replies: 5
    • Views: 620
    19th June 2016, 18:42 Go to last post
  25. Closed: Reading from a file for LCD interfacing (in VHDL)

    Started by hobbyiclearner, 19th June 2016 07:49
    • Replies: 3
    • Views: 551
    19th June 2016, 13:07 Go to last post
  26. Closed: Check my CRC32 function output written in System Verilog

    Started by rakeshk.r, 18th June 2016 14:03
    • Replies: 0
    • Views: 723
    18th June 2016, 14:03 Go to last post
  27. [SOLVED]Closed: Connecting two FPGA's together

    Started by catalin560, 16th June 2016 15:47
    • Replies: 7
    • Views: 821
    18th June 2016, 09:58 Go to last post