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Threads 1501 to 1530 of 22273

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Check my CRC32 function output written in System Verilog

    Started by rakeshk.r, 18th June 2016 14:03
    • Replies: 0
    • Views: 667
    18th June 2016, 14:03 Go to last post
  2. [SOLVED]Closed: Connecting two FPGA's together

    Started by catalin560, 16th June 2016 15:47
    • Replies: 7
    • Views: 800
    18th June 2016, 09:58 Go to last post
  3. [SOLVED]Closed: Query on if else statement in VHDL

    Started by hobbyiclearner, 14th June 2016 16:53
    • Replies: 7
    • Views: 559
    16th June 2016, 17:39 Go to last post
  4. [SOLVED]Closed: Anyone used redpitayta board

    Started by shahbaz.ele, 15th June 2016 06:33
    • Replies: 3
    • Views: 455
    16th June 2016, 10:06 Go to last post
  5. Closed: Some problems due to Altera megafunctions

    Started by shenyiliu, 7th June 2016 02:24
    • Replies: 2
    • Views: 656
    16th June 2016, 05:47 Go to last post
  6. Closed: Problem in verilog coding of a noise shaping filter

    Started by hamidyadegaramin, 15th June 2016 13:45
    • Replies: 1
    • Views: 397
    15th June 2016, 16:08 Go to last post
  7. [SOLVED]Closed: SystemVerilog access members of multidimensional array of struct

    Started by logari84, 15th June 2016 10:32
    • Replies: 1
    • Views: 524
    15th June 2016, 14:39 Go to last post
  8. Closed: [moved] rfid reader 125khz in vhdl

    Started by o-man, 1st June 2016 17:44
    • Replies: 11
    • Views: 848
    15th June 2016, 14:31 Go to last post
  9. Closed: Convert BRAM to DRAM for Virtex -7 FPGA

    Started by velu.plg, 6th April 2016 08:09
    • Replies: 10
    • Views: 834
    15th June 2016, 14:17 Go to last post
  10. Closed: BRAM read delay.............

    Started by velu.plg, 14th June 2016 12:58
    • Replies: 6
    • Views: 728
    15th June 2016, 09:42 Go to last post
  11. Closed: GSM ATCOMMANDS in VHDL

    Started by o-man, 28th May 2016 21:23
    • Replies: 3
    • Views: 761
    15th June 2016, 09:25 Go to last post
  12. Closed: Project suggestions for a De0-Nano Board

    Started by zerovirus123, 15th June 2016 04:37
    • Replies: 0
    • Views: 405
    15th June 2016, 04:37 Go to last post
  13. Closed: Graphical IDEs for FPGAs

    Started by garvind25, 14th June 2016 17:23
    • Replies: 7
    • Views: 395
    14th June 2016, 18:14 Go to last post
  14. [SOLVED]Closed: In vhdl, should for loop be always used inside process?

    Started by Anwesa Roy, 10th June 2016 08:48
    • Replies: 4
    • Views: 822
    14th June 2016, 17:11 Go to last post
  15. Closed: DDR3 Memories on SOC of Xilinx FPGAs

    Started by Mehdi1357, 14th June 2016 12:11
    • Replies: 0
    • Views: 360
    14th June 2016, 12:11 Go to last post
  16. [SOLVED]Closed: HDLs for micro-contoller programming

    Started by garvind25, 12th June 2016 16:11
    • Replies: 1
    • Views: 619
    12th June 2016, 19:21 Go to last post
  17. Closed: Practical exercises for Xilinx FPGA inbuilt features

    Started by garvind25, 6th June 2016 17:46
    • Replies: 7
    • Views: 710
    12th June 2016, 16:04 Go to last post
  18. [SOLVED]Closed: Verilog implementation for d/dt time derivative

    Started by star_golden, 4th May 2016 11:17
    • Replies: 7
    • Views: 1,026
    11th June 2016, 11:22 Go to last post
  19. Closed: ROM and RAM connection

    Started by Kosyas41, 10th June 2016 07:34
    • Replies: 10
    • Views: 1,040
    10th June 2016, 16:55 Go to last post
  20. Closed: to or downto for index

    Started by Binome, 8th June 2016 09:57
    • Replies: 6
    • Views: 557
    10th June 2016, 08:26 Go to last post
  21. [SOLVED]Closed: Source-synchronous data output (Spartan-6)

    Started by hornysquid, 9th June 2016 21:28
    • Replies: 1
    • Views: 385
    9th June 2016, 22:09 Go to last post
  22. Closed: VHDL newbie - VHDL construct question

    Started by arve9066, 9th June 2016 00:11
    • Replies: 8
    • Views: 600
    9th June 2016, 19:44 Go to last post
  23. Closed: Plotting in VGA : help required

    Started by aguntuk, 8th June 2016 16:15
    • Replies: 7
    • Views: 469
    9th June 2016, 17:03 Go to last post
  24. Closed: UART 16550 in Vivado

    Started by Sunayana Chakradhar, 31st May 2016 07:11
    • Replies: 6
    • Views: 751
    9th June 2016, 14:44 Go to last post
    • Replies: 0
    • Views: 359
    8th June 2016, 11:12 Go to last post
  25. Closed: 28byj-48 stepper motor frequency

    Started by alphonsjp, 8th June 2016 09:46
    • Replies: 1
    • Views: 566
    8th June 2016, 10:30 Go to last post
  26. Closed: Application of Digital filters.

    Started by RITESH KAKKAR, 7th June 2016 09:52
    • Replies: 10
    • Views: 618
    8th June 2016, 10:27 Go to last post
  27. Closed: Quartus schematic errors

    Started by AndrewBB, 6th June 2016 15:18
    • Replies: 17
    • Views: 1,586
    7th June 2016, 19:03 Go to last post
    • Replies: 2
    • Views: 432
    7th June 2016, 16:30 Go to last post
  28. Closed: ROM and FFT relation

    Started by Kosyas41, 6th June 2016 08:04
    • Replies: 4
    • Views: 429
    7th June 2016, 08:10 Go to last post