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Threads 15031 to 15060 of 22273

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Changing Baud rate from 9600 to 115200

    Started by missbirdie, 30th June 2008 15:36
    • Replies: 2
    • Views: 5,655
    1st July 2008, 17:13 Go to last post
  2. Closed: VHDL source code availability request

    Started by TekUT, 1st July 2008 17:05
    • Replies: 0
    • Views: 770
    1st July 2008, 17:05 Go to last post
  3. Closed: Combination of VHDL and Verilog codes?

    Started by vishwa, 28th June 2008 06:28
    • Replies: 3
    • Views: 1,580
    1st July 2008, 08:47 Go to last post
  4. Closed: USB 2 IP core needed urgently

    Started by m_3aziz, 29th June 2008 14:40
    • Replies: 2
    • Views: 2,052
    30th June 2008, 23:00 Go to last post
  5. Closed: EDK 10.1 error: mpmc_v4_01_a was not found

    Started by voho, 27th June 2008 15:18
    • Replies: 1
    • Views: 1,157
    30th June 2008, 21:29 Go to last post
  6. Closed: Discussion regarding Clock constraints

    Started by cherjier, 30th June 2008 17:39
    • Replies: 0
    • Views: 793
    30th June 2008, 17:39 Go to last post
  7. Closed: Which stores in Europe sell FPGAs chips in retail?

    Started by mitsos, 30th June 2008 12:46
    • Replies: 1
    • Views: 883
    30th June 2008, 14:17 Go to last post
    • Replies: 3
    • Views: 904
    30th June 2008, 08:16 Go to last post
  8. Closed: error occured while downloading the code?

    Started by wajahat, 28th June 2008 20:37
    • Replies: 1
    • Views: 1,499
    28th June 2008, 23:47 Go to last post
  9. Closed: i can't activate a signal after 12 cycles

    Started by aris12, 27th June 2008 09:38
    • Replies: 6
    • Views: 2,847
    28th June 2008, 19:31 Go to last post
  10. Closed: How do you get your FPGA development board?

    Started by staraimm, 28th June 2008 10:43
    • Replies: 3
    • Views: 1,189
    28th June 2008, 17:51 Go to last post
    • Replies: 0
    • Views: 871
    28th June 2008, 13:58 Go to last post
  11. Closed: VHDL vector integer conversion question

    Started by 555lin, 25th September 2007 11:44
    • Replies: 14
    • Views: 59,227
    28th June 2008, 13:55 Go to last post
  12. Closed: modelsim simulaion problem

    Started by pwq1999, 21st June 2008 00:26
    • Replies: 6
    • Views: 1,928
    28th June 2008, 05:22 Go to last post
  13. Closed: Need help in this verilog code

    Started by victoria_jitesh, 27th June 2008 14:39
    • Replies: 1
    • Views: 939
    28th June 2008, 01:09 Go to last post
  14. Closed: Manual Place and route

    Started by sandeep_sggs, 21st June 2008 10:27
    • Replies: 3
    • Views: 2,753
    27th June 2008, 15:00 Go to last post
  15. Closed: case statement(verilog)

    Started by pwq1999, 22nd June 2008 15:53
    • Replies: 2
    • Views: 18,921
    27th June 2008, 13:26 Go to last post
  16. Closed: How to make Spartan 3E Xilinx take sample every 8ns?

    Started by Zhane, 25th June 2008 04:03
    • Replies: 9
    • Views: 1,888
    26th June 2008, 15:41 Go to last post
  17. Closed: DSPCon 9100 model-urgent help

    Started by vinodkumar, 26th June 2008 10:42
    • Replies: 0
    • Views: 776
    26th June 2008, 10:42 Go to last post
  18. Closed: Links to a PCM boards, 8 channels of PCM in., VME bus baseed

    Started by vinodkumar, 26th June 2008 10:33
    • Replies: 0
    • Views: 877
    26th June 2008, 10:33 Go to last post
  19. Closed: Help me choose VLSI degree courses

    Started by Nikolai, 17th June 2008 17:59
    • Replies: 2
    • Views: 983
    26th June 2008, 09:16 Go to last post
  20. Closed: thermal fpga simulation

    Started by omar-malek, 24th June 2008 21:42
    • Replies: 1
    • Views: 886
    25th June 2008, 00:57 Go to last post
    • Replies: 0
    • Views: 1,068
    23rd June 2008, 23:28 Go to last post
  21. Closed: Best FPGA kit for Wireless Applications

    Started by omara007, 7th February 2008 06:54
    • Replies: 4
    • Views: 1,299
    23rd June 2008, 23:18 Go to last post
  22. Closed: VHDL implementation of Digital IF in WiMAX

    Started by missbirdie, 23rd June 2008 11:26
    • Replies: 9
    • Views: 1,686
    23rd June 2008, 17:55 Go to last post
  23. Closed: Parallel to Serial 36 bits Shift Register

    Started by missbirdie, 23rd June 2008 13:33
    • Replies: 3
    • Views: 1,586
    23rd June 2008, 15:28 Go to last post
  24. Closed: Inferring Vs Instantiation ??

    Started by vishwa, 3rd June 2008 11:37
    • Replies: 5
    • Views: 3,466
    23rd June 2008, 12:10 Go to last post
  25. Closed: Can we convert composite into analoge RGB using fpga

    Started by synq, 29th March 2004 02:28
    • Replies: 16
    • Views: 6,592
    23rd June 2008, 03:10 Go to last post
  26. Closed: VHDL CODING STYPE FOR STATE MACHINES.

    Started by Mirzaaur, 11th June 2008 09:32
    • Replies: 4
    • Views: 1,463
    22nd June 2008, 10:00 Go to last post
    • Replies: 4
    • Views: 1,057
    21st June 2008, 23:09 Go to last post