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Threads 15001 to 15030 of 22807

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 0
    • Views: 1,671
    10th November 2008, 13:06 Go to last post
  1. Closed: JTAG programming for Xilinx spartan 3E ...

    Started by hm_fa_da, 3rd November 2008 18:45
    • Replies: 1
    • Views: 4,253
    10th November 2008, 11:29 Go to last post
  2. Closed: Row/Column open/close in SDRAM?

    Started by cafukarfoo, 10th November 2008 10:44
    • Replies: 2
    • Views: 1,747
    10th November 2008, 11:20 Go to last post
  3. Closed: I/O Buffer (IOB) vs. Global Clock I/O Buffer (GCLKIOB)

    Started by farrokhiyan, 1st November 2008 12:15
    • Replies: 4
    • Views: 8,040
    10th November 2008, 11:13 Go to last post
  4. Closed: Maximum burst pulse calculation for SDRAM

    Started by cafukarfoo, 10th November 2008 10:56
    • Replies: 0
    • Views: 868
    10th November 2008, 10:56 Go to last post
  5. Closed: Warnings when simulate RAM based Shiftreg

    Started by sivarajm, 3rd November 2008 13:10
    • Replies: 1
    • Views: 918
    9th November 2008, 18:41 Go to last post
  6. Closed: Discussion on System Verilog!

    Started by deepu_s_s, 3rd November 2008 06:35
    • Replies: 5
    • Views: 1,093
    9th November 2008, 07:43 Go to last post
  7. Closed: Using LWIP of Xilinx EDK

    Started by atena, 20th October 2008 13:41
    • Replies: 1
    • Views: 5,713
    8th November 2008, 14:51 Go to last post
  8. Closed: error:"Instance instance... FIFO.... has no lut_functio

    Started by jeremylbt, 8th November 2008 09:11
    • Replies: 2
    • Views: 1,776
    8th November 2008, 14:18 Go to last post
  9. Closed: Optimization of registers

    Started by jeremylbt, 7th November 2008 14:44
    • Replies: 2
    • Views: 1,087
    8th November 2008, 14:01 Go to last post
  10. Closed: I need these papers soon...........

    Started by mkanimozhivlsi, 8th November 2008 12:22
    • Replies: 0
    • Views: 1,294
    8th November 2008, 12:22 Go to last post
  11. Closed: who is developer of SPI protocol

    Started by mkanimozhivlsi, 8th November 2008 08:07
    • Replies: 2
    • Views: 1,233
    8th November 2008, 12:05 Go to last post
  12. Closed: What is the difference between DLL and PLL?

    Started by jakin, 31st October 2008 21:58
    • Replies: 4
    • Views: 12,097
    8th November 2008, 08:34 Go to last post
  13. Closed: Sensor Interfacing to a Xinlinx Spartan 3

    Started by sht11help, 5th November 2008 16:47
    • Replies: 6
    • Views: 5,825
    6th November 2008, 19:52 Go to last post
  14. Closed: DDR SDRAM Operation Documentation

    Started by cafukarfoo, 6th November 2008 04:07
    • Replies: 1
    • Views: 2,290
    6th November 2008, 11:19 Go to last post
  15. Closed: Xilinx ISE FPGA editor

    Started by richardwli, 5th November 2008 16:10
    • Replies: 0
    • Views: 1,972
    5th November 2008, 16:10 Go to last post
  16. Closed: FPGA design detail questions

    Started by tzushky, 31st October 2008 14:45
    • Replies: 4
    • Views: 1,450
    5th November 2008, 11:16 Go to last post
  17. Closed: Generate bit in same conditions,but differents results, why?

    Started by yhua.tang, 5th November 2008 06:46
    • Replies: 0
    • Views: 796
    5th November 2008, 06:46 Go to last post
  18. Closed: Warning : ConstraintSystem:119

    Started by chetan.deokar, 5th November 2008 05:46
    • Replies: 0
    • Views: 2,945
    5th November 2008, 05:46 Go to last post
  19. Closed: Boundary Scan Test for Altera MAX

    Started by Singapura, 3rd November 2008 10:04
    • Replies: 1
    • Views: 1,121
    4th November 2008, 12:45 Go to last post
  20. Closed: What's the difference between LVCMOS, LVTTL and LVDS?

    Started by satishkumar, 3rd November 2008 12:02
    • Replies: 2
    • Views: 26,046
    4th November 2008, 07:56 Go to last post
  21. Closed: any systemverilog lectures?

    Started by THUNDERRr, 27th October 2008 10:48
    • Replies: 5
    • Views: 1,875
    3rd November 2008, 06:28 Go to last post
  22. Closed: needs help on CLOCK with FPGA

    Started by pantho, 3rd November 2008 05:35
    • Replies: 0
    • Views: 908
    3rd November 2008, 05:35 Go to last post
  23. Closed: Quartus 2 error (10482): VHDL error at mux_8x8.vhd(71)

    Started by danesh, 2nd November 2008 15:41
    • Replies: 2
    • Views: 8,459
    2nd November 2008, 20:50 Go to last post
  24. Closed: resource utilization factor from a top-level design

    Started by balasub, 2nd November 2008 12:48
    • Replies: 0
    • Views: 1,395
    2nd November 2008, 12:48 Go to last post
  25. Closed: suggest some low-jitter techniques...

    Started by jadedfox, 2nd November 2008 08:39
    • Replies: 0
    • Views: 749
    2nd November 2008, 08:39 Go to last post
  26. Closed: Need of lcd commands for 20x4LCD

    Started by Mkanimozhi, 31st October 2008 07:45
    • Replies: 1
    • Views: 1,247
    1st November 2008, 01:59 Go to last post
  27. Closed: "wait for" statement inside process with a sensiti

    Started by carbon9, 19th May 2008 13:42
    • Replies: 8
    • Views: 6,839
    31st October 2008, 20:09 Go to last post
  28. Closed: tan sigmoid with vhdl code

    Started by zayodi, 31st October 2008 15:28
    • Replies: 0
    • Views: 2,467
    31st October 2008, 15:28 Go to last post
  29. Closed: two phase clock register in Verilog

    Started by Sadegh.j, 31st October 2008 05:15
    • Replies: 0
    • Views: 1,215
    31st October 2008, 05:15 Go to last post