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Threads 15001 to 15030 of 22387

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: paper needed from sciencdirect

    Started by gurucharan, 7th August 2008 06:33
    • Replies: 0
    • Views: 1,773
    7th August 2008, 06:33 Go to last post
  2. Closed: IR length info for non-xilinx devices?

    Started by Renjith, 6th August 2008 13:38
    • Replies: 2
    • Views: 1,636
    6th August 2008, 15:28 Go to last post
  3. Closed: Good books from which you can learn Verilog HDL

    Started by arjunpcet, 5th August 2008 20:34
    • Replies: 4
    • Views: 2,306
    6th August 2008, 06:53 Go to last post
  4. Closed: how to estimate the logic cell from c-code

    Started by trashbox, 5th August 2008 10:48
    • Replies: 1
    • Views: 834
    5th August 2008, 16:17 Go to last post
  5. Closed: lvcmos33 io maping fails while lvcmose 25 pass(ise8) why???

    Started by gauz, 4th August 2008 14:49
    • Replies: 2
    • Views: 1,938
    5th August 2008, 08:43 Go to last post
  6. Closed: Suggest me some useful proposals

    Started by usmanstar2, 5th August 2008 07:33
    • Replies: 0
    • Views: 703
    5th August 2008, 07:33 Go to last post
  7. Closed: Help me understand the process of secam encoding

    Started by sridhar_m, 5th August 2008 06:43
    • Replies: 0
    • Views: 868
    5th August 2008, 06:43 Go to last post
  8. Closed: How to convert XC9536XL jed file to Boolean equations?

    Started by yangyunxing, 5th August 2008 00:55
    • Replies: 0
    • Views: 1,372
    5th August 2008, 00:55 Go to last post
  9. Closed: Needed help.. regard my final year project

    Started by visitmoorthy, 4th August 2008 22:13
    • Replies: 0
    • Views: 669
    4th August 2008, 22:13 Go to last post
    • Replies: 1
    • Views: 1,179
    4th August 2008, 09:30 Go to last post
  10. Closed: block memory access prob (ISE & Quartus)

    Started by childs, 25th July 2008 08:11
    • Replies: 4
    • Views: 1,460
    4th August 2008, 09:29 Go to last post
  11. Closed: why PLLs are placed at boundary of FPGA?

    Started by hasitri, 3rd August 2008 23:00
    • Replies: 1
    • Views: 822
    4th August 2008, 08:45 Go to last post
  12. Closed: vhdl code for pulse generation of pw=1ms

    Started by kk_victory, 4th August 2008 07:52
    • Replies: 1
    • Views: 4,246
    4th August 2008, 08:23 Go to last post
  13. Closed: what is the FPGA I/O status before configuration ?

    Started by dolby.yang, 2nd August 2008 07:52
    • Replies: 2
    • Views: 765
    4th August 2008, 02:04 Go to last post
  14. Closed: ERROR message: Resolution function required

    Started by snakyfactory, 3rd August 2008 08:16
    • Replies: 2
    • Views: 4,355
    3rd August 2008, 11:26 Go to last post
  15. Closed: How Security algorithm??

    Started by khamitkar.ravikant, 31st July 2008 14:58
    • Replies: 2
    • Views: 904
    3rd August 2008, 07:35 Go to last post
  16. Closed: How to simulate my memory model

    Started by EDA_hg81, 2nd August 2008 02:17
    • Replies: 1
    • Views: 1,025
    2nd August 2008, 15:09 Go to last post
  17. Closed: Looking for information about Spartan 3e FPGA

    Started by gurucharan, 1st August 2008 06:27
    • Replies: 2
    • Views: 1,139
    2nd August 2008, 12:27 Go to last post
  18. Closed: Interfacing Micron DDR Memories to Xilinx VIRTEX4

    Started by voho, 1st August 2008 10:27
    • Replies: 0
    • Views: 928
    1st August 2008, 10:27 Go to last post
  19. Closed: Looking for detailed info about BMM and MEM files

    Started by vijayvlsivhdl, 1st August 2008 07:38
    • Replies: 0
    • Views: 865
    1st August 2008, 07:38 Go to last post
  20. Closed: Reasoning behind active low signals

    Started by abhihegde, 31st July 2008 06:11
    • Replies: 2
    • Views: 1,148
    31st July 2008, 10:02 Go to last post
  21. Closed: Implementing an soft core inside FPGA

    Started by sadid, 30th July 2008 08:10
    • Replies: 2
    • Views: 1,186
    31st July 2008, 09:26 Go to last post
  22. Closed: signal names problem when viewing waveform in Chipscope

    Started by pwq1999, 31st July 2008 09:08
    • Replies: 0
    • Views: 1,014
    31st July 2008, 09:08 Go to last post
  23. Closed: How to generate a bitstream for a custom CLB.

    Started by steadymind, 31st July 2008 06:41
    • Replies: 0
    • Views: 1,034
    31st July 2008, 06:41 Go to last post
  24. Closed: Video format converter

    Started by muralicrl, 31st July 2008 04:50
    • Replies: 0
    • Views: 754
    31st July 2008, 04:50 Go to last post
  25. Closed: Dont understand the meaning of this LOOP (VHDL)

    Started by BlackOps, 24th July 2008 10:17
    • Replies: 1
    • Views: 1,166
    30th July 2008, 22:04 Go to last post
  26. Closed: XUP Virtex-II Pro board - access with DLP

    Started by suquid29, 30th July 2008 21:56
    • Replies: 0
    • Views: 784
    30th July 2008, 21:56 Go to last post
  27. Closed: using $monitor and $fmonitor in verilog

    Started by andersod2, 30th July 2008 20:47
    • Replies: 0
    • Views: 6,383
    30th July 2008, 20:47 Go to last post
  28. Closed: vhdl code for pulse generator

    Started by kk_victory, 30th July 2008 10:30
    • Replies: 1
    • Views: 3,015
    30th July 2008, 11:01 Go to last post
  29. Closed: Looking for CMOS cell design

    Started by ashishvdeshpande, 20th September 2006 16:13
    • Replies: 3
    • Views: 1,200
    30th July 2008, 08:15 Go to last post