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Threads 15001 to 15030 of 22301

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: classification of VLSI?maximum operating speed of FPGA.

    Started by braveprasanna, 16th July 2008 04:35
    • Replies: 0
    • Views: 911
    16th July 2008, 04:35 Go to last post
  2. Closed: Issues in vhdl coding...plz let me know if u r aware.....

    Started by vidyaredy, 11th July 2008 08:53
    • Replies: 10
    • Views: 3,755
    15th July 2008, 20:17 Go to last post
  3. Closed: Help require on Booth multiplier

    Started by victoria_jitesh, 12th July 2008 12:01
    • Replies: 3
    • Views: 1,241
    15th July 2008, 16:39 Go to last post
  4. Closed: Ideas on Verilog project topics!

    Started by anandanips, 10th January 2008 13:41
    • Replies: 6
    • Views: 2,878
    15th July 2008, 16:35 Go to last post
  5. Closed: Convert IF-THEN-ELSE statements to the STATE MACHINE

    Started by BlackOps, 9th July 2008 15:50
    • Replies: 2
    • Views: 2,250
    15th July 2008, 10:32 Go to last post
  6. Closed: VLSI INDUSTRY -FIRING EMPLOYEES

    Started by muralinelavalli, 12th July 2008 11:34
    • Replies: 2
    • Views: 1,163
    15th July 2008, 08:16 Go to last post
  7. Closed: Adding Libraries in FPGAdvantage

    Started by niche, 14th July 2008 14:34
    • Replies: 0
    • Views: 1,087
    14th July 2008, 14:34 Go to last post
  8. Closed: help needed for mti functions in modelsim

    Started by kishorkk, 14th July 2008 13:07
    • Replies: 0
    • Views: 860
    14th July 2008, 13:07 Go to last post
  9. Closed: How to implement watchdog timer for 8051?

    Started by babaganoosh, 14th July 2008 12:07
    • Replies: 0
    • Views: 2,197
    14th July 2008, 12:07 Go to last post
  10. Closed: Help require from INTERVIEW point

    Started by victoria_jitesh, 7th July 2008 13:02
    • Replies: 1
    • Views: 872
    14th July 2008, 09:47 Go to last post
  11. Closed: A question about Modelsim Waveform

    Started by bigyellow, 14th July 2008 08:55
    • Replies: 0
    • Views: 812
    14th July 2008, 08:55 Go to last post
  12. Closed: Any easy demo of ddr sdram of spartan 3e

    Started by chillimillii, 14th July 2008 08:26
    • Replies: 0
    • Views: 902
    14th July 2008, 08:26 Go to last post
  13. Closed: Details about WLM- Wire load Model

    Started by kumar_eee, 9th December 2005 03:28
    • Replies: 5
    • Views: 8,352
    14th July 2008, 07:53 Go to last post
  14. Closed: Can i use Matlab(Simulink)as data source to FPGAVirtexII pro

    Started by m_3aziz, 23rd June 2008 22:25
    • Replies: 5
    • Views: 1,822
    13th July 2008, 10:21 Go to last post
  15. Closed: help needed regarding "Address Generation"

    Started by himadrisinghraghav, 13th July 2008 07:25
    • Replies: 0
    • Views: 652
    13th July 2008, 07:25 Go to last post
  16. Closed: need help to choose a PLD 4 a project

    Started by madusnk, 11th July 2008 10:24
    • Replies: 7
    • Views: 1,096
    11th July 2008, 13:50 Go to last post
  17. Closed: Problem with connecting Virtex-E FPGA to JTAG

    Started by EDA_hg81, 10th July 2008 16:28
    • Replies: 4
    • Views: 1,133
    11th July 2008, 13:46 Go to last post
  18. Closed: Is Altium good for Xilinx FPGA/CPLD designs?

    Started by 7rots51, 11th July 2008 12:07
    • Replies: 0
    • Views: 2,041
    11th July 2008, 12:07 Go to last post
  19. Closed: Help needed in writing FSM for ethernet.

    Started by atif.india, 10th July 2008 19:36
    • Replies: 2
    • Views: 1,305
    11th July 2008, 08:15 Go to last post
  20. Closed: What is RPS verification in System verilog

    Started by rockgird, 8th July 2008 07:39
    • Replies: 1
    • Views: 1,231
    11th July 2008, 07:47 Go to last post
  21. Closed: Multicycle and falsepath fixing in Xilinx

    Started by kil, 11th July 2008 04:55
    • Replies: 0
    • Views: 934
    11th July 2008, 04:55 Go to last post
  22. Closed: simulation tricks using modelsim

    Started by pwq1999, 9th July 2008 15:29
    • Replies: 3
    • Views: 2,236
    11th July 2008, 00:22 Go to last post
  23. Closed: How to use Xilinx coregen FIFOs?

    Started by Zhane, 4th July 2008 08:05
    • Replies: 6
    • Views: 4,386
    10th July 2008, 16:58 Go to last post
  24. Closed: sending data to a hardware acclerator

    Started by snake0204, 8th July 2008 21:15
    • Replies: 2
    • Views: 843
    10th July 2008, 09:30 Go to last post
  25. Closed: What is important about antenna in GSM communication?

    Started by m_bakhtiarie, 5th July 2008 05:34
    • Replies: 1
    • Views: 796
    10th July 2008, 08:54 Go to last post
  26. Closed: Spartan 3E Starter Kit, Spartan Starter Kit, Cyclone II.

    Started by malaylah, 9th July 2008 22:29
    • Replies: 1
    • Views: 2,234
    10th July 2008, 08:30 Go to last post
  27. Closed: Alternative part for QL2007-1PQ208I

    Started by tpj, 9th July 2008 10:50
    • Replies: 0
    • Views: 774
    9th July 2008, 10:50 Go to last post
    • Replies: 6
    • Views: 1,768
    9th July 2008, 10:18 Go to last post
  28. Closed: NIOSII audio core help

    Started by fasmatikos, 19th February 2008 16:26
    • Replies: 2
    • Views: 1,345
    9th July 2008, 00:28 Go to last post
  29. Closed: Simple 3-band equalizer in NIOS

    Started by fasmatikos, 18th April 2008 11:05
    • Replies: 2
    • Views: 1,137
    9th July 2008, 00:27 Go to last post