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Threads 15001 to 15030 of 22273

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: NIOSII audio core help

    Started by fasmatikos, 19th February 2008 16:26
    • Replies: 2
    • Views: 1,332
    9th July 2008, 00:28 Go to last post
  2. Closed: Simple 3-band equalizer in NIOS

    Started by fasmatikos, 18th April 2008 11:05
    • Replies: 2
    • Views: 1,121
    9th July 2008, 00:27 Go to last post
  3. Closed: usage of non-volatile memory

    Started by childs, 8th July 2008 10:20
    • Replies: 1
    • Views: 941
    8th July 2008, 21:18 Go to last post
  4. Closed: VHDL question, what is the better architecture for this task

    Started by TekUT, 8th July 2008 12:35
    • Replies: 3
    • Views: 1,008
    8th July 2008, 16:01 Go to last post
  5. Closed: How to set spartan 3 mode pins

    Started by EDA_hg81, 7th July 2008 15:51
    • Replies: 2
    • Views: 1,064
    8th July 2008, 14:41 Go to last post
  6. Closed: question about this.ports in systemverilog

    Started by THUNDERRr, 19th June 2008 13:53
    • Replies: 2
    • Views: 871
    8th July 2008, 10:24 Go to last post
  7. Closed: help me with function in verilog

    Started by deepu_s_s, 6th July 2008 07:37
    • Replies: 1
    • Views: 907
    7th July 2008, 13:47 Go to last post
  8. Closed: Somethinng wrong with my code

    Started by deepu_s_s, 30th June 2008 06:42
    • Replies: 5
    • Views: 1,207
    7th July 2008, 11:11 Go to last post
  9. Closed: Video controller IP project

    Started by BlackOps, 30th June 2008 12:02
    • Replies: 1
    • Views: 1,277
    7th July 2008, 11:05 Go to last post
  10. Closed: Reference Design for FPGA-Based Smart Camera Design

    Started by ehsan_noroz, 7th July 2008 10:44
    • Replies: 0
    • Views: 1,452
    7th July 2008, 10:44 Go to last post
  11. Closed: Synchronizers on FPGA

    Started by suquid29, 4th July 2008 13:21
    • Replies: 4
    • Views: 2,313
    6th July 2008, 23:04 Go to last post
  12. Closed: Where to find some VHDL exercises?

    Started by brunokasimin, 4th July 2008 23:18
    • Replies: 2
    • Views: 1,383
    6th July 2008, 10:47 Go to last post
  13. Closed: What is the Electronic System Level (ESL)?

    Started by gck, 4th July 2008 04:02
    • Replies: 1
    • Views: 877
    6th July 2008, 08:12 Go to last post
  14. Closed: ISE 9.2 with xilinx virtex-4

    Started by m_pourfathi, 2nd July 2008 14:59
    • Replies: 4
    • Views: 1,526
    5th July 2008, 12:05 Go to last post
  15. Closed: what is distributed address decoding

    Started by victoria_jitesh, 5th July 2008 10:19
    • Replies: 0
    • Views: 709
    5th July 2008, 10:19 Go to last post
  16. Closed: lasert light modulation

    Started by m_bakhtiarie, 5th July 2008 05:40
    • Replies: 0
    • Views: 680
    5th July 2008, 05:40 Go to last post
  17. Closed: help in verilog coding

    Started by deepu_s_s, 3rd July 2008 20:43
    • Replies: 3
    • Views: 12,064
    5th July 2008, 04:50 Go to last post
  18. Closed: What is the difference between Verilog and Verilog XL?

    Started by gck, 22nd May 2008 08:38
    • Replies: 1
    • Views: 1,053
    5th July 2008, 02:54 Go to last post
  19. Closed: Multiply-Accumulate (MAC) Rounding Precision in Spartan3

    Started by omara007, 4th July 2008 22:06
    • Replies: 0
    • Views: 952
    4th July 2008, 22:06 Go to last post
  20. Closed: VHDL question (process implementation as FSM)

    Started by TekUT, 4th July 2008 13:05
    • Replies: 1
    • Views: 926
    4th July 2008, 17:50 Go to last post
  21. Closed: Recommend Digital Design Handbook

    Started by cafukarfoo, 3rd July 2008 06:39
    • Replies: 4
    • Views: 1,099
    4th July 2008, 04:12 Go to last post
  22. Closed: Help me design a new FPGA card

    Started by voho, 2nd July 2008 13:58
    • Replies: 1
    • Views: 888
    3rd July 2008, 22:01 Go to last post
  23. Closed: serial or parallel communication b/w PC and FPGA

    Started by kzirshan, 3rd July 2008 04:49
    • Replies: 1
    • Views: 1,606
    3rd July 2008, 11:53 Go to last post
  24. Closed: Modelsim Simulation Problem

    Started by Zhane, 3rd July 2008 10:33
    • Replies: 0
    • Views: 713
    3rd July 2008, 10:33 Go to last post
  25. Closed: Need platform cable usb sch

    Started by pigyong801, 3rd July 2008 02:16
    • Replies: 0
    • Views: 906
    3rd July 2008, 02:16 Go to last post
  26. Closed: need fpga jtag program circuit

    Started by hamed_sotoudi, 30th June 2008 17:43
    • Replies: 2
    • Views: 1,840
    2nd July 2008, 18:37 Go to last post
  27. Closed: XNF (Xilinx Netlist Format) to EDIF conversion

    Started by cherukukeshav, 2nd July 2008 09:36
    • Replies: 1
    • Views: 1,840
    2nd July 2008, 18:32 Go to last post
  28. Closed: Synthesis Error - Spartan 3E

    Started by Zhane, 30th June 2008 09:06
    • Replies: 5
    • Views: 2,142
    2nd July 2008, 14:43 Go to last post
  29. Closed: DC motoros Controller With strobe logic circuit

    Started by tannazii, 2nd July 2008 10:04
    • Replies: 0
    • Views: 900
    2nd July 2008, 10:04 Go to last post