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Threads 15001 to 15030 of 22788

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Boundary Scan Test for Altera MAX

    Started by Singapura, 3rd November 2008 10:04
    • Replies: 1
    • Views: 1,095
    4th November 2008, 12:45 Go to last post
  2. Closed: What's the difference between LVCMOS, LVTTL and LVDS?

    Started by satishkumar, 3rd November 2008 12:02
    • Replies: 2
    • Views: 25,728
    4th November 2008, 07:56 Go to last post
  3. Closed: any systemverilog lectures?

    Started by THUNDERRr, 27th October 2008 10:48
    • Replies: 5
    • Views: 1,837
    3rd November 2008, 06:28 Go to last post
  4. Closed: needs help on CLOCK with FPGA

    Started by pantho, 3rd November 2008 05:35
    • Replies: 0
    • Views: 891
    3rd November 2008, 05:35 Go to last post
  5. Closed: Quartus 2 error (10482): VHDL error at mux_8x8.vhd(71)

    Started by danesh, 2nd November 2008 15:41
    • Replies: 2
    • Views: 8,427
    2nd November 2008, 20:50 Go to last post
  6. Closed: resource utilization factor from a top-level design

    Started by balasub, 2nd November 2008 12:48
    • Replies: 0
    • Views: 1,370
    2nd November 2008, 12:48 Go to last post
  7. Closed: suggest some low-jitter techniques...

    Started by jadedfox, 2nd November 2008 08:39
    • Replies: 0
    • Views: 728
    2nd November 2008, 08:39 Go to last post
  8. Closed: Need of lcd commands for 20x4LCD

    Started by Mkanimozhi, 31st October 2008 07:45
    • Replies: 1
    • Views: 1,222
    1st November 2008, 01:59 Go to last post
  9. Closed: "wait for" statement inside process with a sensiti

    Started by carbon9, 19th May 2008 13:42
    • Replies: 8
    • Views: 6,771
    31st October 2008, 20:09 Go to last post
  10. Closed: tan sigmoid with vhdl code

    Started by zayodi, 31st October 2008 15:28
    • Replies: 0
    • Views: 2,435
    31st October 2008, 15:28 Go to last post
  11. Closed: two phase clock register in Verilog

    Started by Sadegh.j, 31st October 2008 05:15
    • Replies: 0
    • Views: 1,194
    31st October 2008, 05:15 Go to last post
  12. Closed: Project Directory Structure / files organising in xilinx

    Started by muralinmail, 31st October 2008 04:16
    • Replies: 0
    • Views: 1,197
    31st October 2008, 04:16 Go to last post
  13. Closed: Xilinx virtex 4 I\O specification

    Started by gmittal, 30th October 2008 16:58
    • Replies: 0
    • Views: 992
    30th October 2008, 16:58 Go to last post
  14. Closed: about CPLD and EPLD - request for resources

    Started by Mkanimozhi, 30th October 2008 13:06
    • Replies: 0
    • Views: 903
    30th October 2008, 13:06 Go to last post
  15. Closed: problem in programming XC3S700AN

    Started by 20037100, 29th October 2008 11:11
    • Replies: 2
    • Views: 1,807
    30th October 2008, 07:59 Go to last post
  16. Closed: example ucf file required

    Started by pantho, 26th October 2008 08:43
    • Replies: 2
    • Views: 2,773
    30th October 2008, 05:13 Go to last post
  17. Closed: loading of Memory Initialization File in FpgAdv

    Started by brunokasimin, 29th October 2008 18:08
    • Replies: 0
    • Views: 1,687
    29th October 2008, 18:08 Go to last post
  18. Closed: warning message in precision

    Started by brunokasimin, 29th October 2008 17:59
    • Replies: 0
    • Views: 957
    29th October 2008, 17:59 Go to last post
  19. Closed: looking for both quartus and FpgAdv expert(urgent)

    Started by brunokasimin, 29th October 2008 16:22
    • Replies: 0
    • Views: 876
    29th October 2008, 16:22 Go to last post
  20. Closed: need help SPARTAN 3E's DDR SDRAM

    Started by quer, 23rd October 2008 15:48
    • Replies: 5
    • Views: 5,335
    29th October 2008, 14:30 Go to last post
  21. Closed: Basic VHDL Question about Edges

    Started by dohzer, 25th October 2008 15:50
    • Replies: 4
    • Views: 7,284
    29th October 2008, 13:23 Go to last post
  22. Closed: I2C Improper SDA in the Hardware

    Started by rush2sami, 29th October 2008 12:51
    • Replies: 0
    • Views: 949
    29th October 2008, 12:51 Go to last post
  23. Closed: modelsim 6.2g - looking inside RAM

    Started by popa, 25th October 2008 10:15
    • Replies: 2
    • Views: 1,090
    29th October 2008, 11:59 Go to last post
  24. Closed: displaying waveforms on LCD using FPGAs

    Started by muhammad_ali, 27th October 2008 14:49
    • Replies: 2
    • Views: 1,528
    29th October 2008, 11:57 Go to last post
  25. Closed: Please help me debug my vhdl code of 4 bit ALU

    Started by RollingEEE, 27th October 2008 13:35
    • Replies: 2
    • Views: 8,392
    29th October 2008, 10:26 Go to last post
  26. Closed: special software to deal with ASM charts in VISIO

    Started by Alkakkali, 27th October 2008 06:03
    • Replies: 0
    • Views: 1,904
    27th October 2008, 06:03 Go to last post
  27. Closed: Do you guys really use the function & Procedure in VHDL?

    Started by spriteice, 28th October 2004 07:57
    2 Pages
    1 2
    • Replies: 25
    • Views: 9,050
    26th October 2008, 22:18 Go to last post
  28. Closed: finite state machine - request for resources

    Started by amriths04, 25th October 2008 04:38
    • Replies: 1
    • Views: 1,374
    25th October 2008, 15:36 Go to last post
  29. Closed: Virtex4 ISERDES and DCM configuration problem

    Started by saikat, 25th October 2008 15:04
    • Replies: 0
    • Views: 1,241
    25th October 2008, 15:04 Go to last post
  30. Closed: Speech Recognition VHDL

    Started by tarang, 21st October 2008 04:35
    • Replies: 2
    • Views: 4,063
    24th October 2008, 14:17 Go to last post