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Threads 15001 to 15030 of 22858

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Platform Studio and the EDK tools ?

    Started by khamitkar.ravikant, 3rd August 2008 10:57
    • Replies: 9
    • Views: 2,983
    24th November 2008, 14:52 Go to last post
  2. Closed: Multisource Error during VHDL Synthesis

    Started by sgil, 23rd November 2008 19:07
    • Replies: 5
    • Views: 14,056
    24th November 2008, 09:40 Go to last post
  3. Closed: What is the difference of CPLD and FPGA?

    Started by bunalmis, 1st December 2003 09:24
    2 Pages
    1 2
    • Replies: 24
    • Views: 81,828
    24th November 2008, 08:54 Go to last post
  4. Closed: Audio Feature Extraction in VHDL

    Started by tarang, 23rd November 2008 06:59
    • Replies: 3
    • Views: 1,999
    23rd November 2008, 16:45 Go to last post
  5. Closed: I have problem with FPGA JTAG chain please help me

    Started by hamed_sotoudi, 22nd November 2008 12:51
    • Replies: 0
    • Views: 1,146
    22nd November 2008, 12:51 Go to last post
  6. Closed: Problem with $readmemb in Modelsim 6.3

    Started by qingmian, 26th October 2008 14:49
    • Replies: 1
    • Views: 3,211
    22nd November 2008, 09:03 Go to last post
  7. Closed: 100% free PLD compiler ?

    Started by elektryk, 7th November 2008 01:50
    • Replies: 3
    • Views: 11,039
    21st November 2008, 23:15 Go to last post
  8. Closed: how to display on LCD of FPGA board?

    Started by pantho, 21st November 2008 04:52
    • Replies: 3
    • Views: 3,104
    21st November 2008, 18:41 Go to last post
  9. Closed: Verilog to switch pictures for VGA display

    Started by alin9980, 17th November 2008 19:58
    • Replies: 2
    • Views: 4,503
    20th November 2008, 18:42 Go to last post
  10. Closed: testing an Emulator board - JTAG signal levels problem

    Started by sandhya.im, 20th November 2008 09:18
    • Replies: 1
    • Views: 1,148
    20th November 2008, 16:36 Go to last post
  11. Closed: xilinx platform(VHDL),want to implement 8 processor in FPGA

    Started by ramzitligue, 20th November 2008 13:16
    • Replies: 1
    • Views: 965
    20th November 2008, 14:13 Go to last post
  12. Closed: need information on How PLL Locks the clock comming on bus

    Started by vinod_g, 20th November 2008 06:44
    • Replies: 1
    • Views: 1,095
    20th November 2008, 09:50 Go to last post
  13. Closed: AMBA ADVANCED HIGH PERFORMANCE BUS(AHB)PROTOCOL VERILOG CODE

    Started by ataullah, 20th November 2008 08:10
    • Replies: 0
    • Views: 6,750
    20th November 2008, 08:10 Go to last post
  14. Closed: verilog : conditional assign statement

    Started by ashishnetam, 20th November 2008 07:03
    • Replies: 1
    • Views: 36,613
    20th November 2008, 07:53 Go to last post
  15. Closed: microblaze spartan 3 vhdl routines needed!!

    Started by sht11help, 19th November 2008 17:32
    • Replies: 5
    • Views: 1,807
    19th November 2008, 21:53 Go to last post
  16. Closed: Does any one have experience with opb to wishbone

    Started by lince, 19th November 2008 20:07
    • Replies: 0
    • Views: 932
    19th November 2008, 20:07 Go to last post
  17. Closed: fifo of xilinx(.vhd) 511 words of 36 bits, 127 words 64 bits

    Started by ramzitligue, 18th November 2008 23:33
    • Replies: 2
    • Views: 1,628
    19th November 2008, 08:45 Go to last post
  18. Closed: about LVDS - request for resources

    Started by abcyin, 18th November 2008 08:54
    • Replies: 2
    • Views: 952
    19th November 2008, 08:14 Go to last post
  19. Closed: Question:High speed dsp (about 350MHz) on virtex5

    Started by soheyl, 17th November 2008 14:10
    • Replies: 6
    • Views: 1,475
    19th November 2008, 08:06 Go to last post
  20. Closed: Minimum Of N Numbers using verilog or VHDL

    Started by kalyansumankv, 13th November 2008 06:11
    • Replies: 12
    • Views: 11,021
    19th November 2008, 05:26 Go to last post
  21. Closed: timing analysis ? - request for resources

    Started by Fergu, 13th November 2008 04:46
    • Replies: 2
    • Views: 1,117
    19th November 2008, 02:40 Go to last post
  22. Closed: Design Issue of clock recovery technique

    Started by vinod_g, 18th November 2008 09:46
    • Replies: 0
    • Views: 832
    18th November 2008, 09:46 Go to last post
  23. Closed: [Cadence NCVHDL] Generate several libraries and use them

    Started by tzushky, 18th November 2008 09:14
    • Replies: 0
    • Views: 1,180
    18th November 2008, 09:14 Go to last post
  24. Closed: does any body know about the SDIO?

    Started by ravi4all, 13th November 2008 13:28
    • Replies: 3
    • Views: 1,430
    18th November 2008, 09:05 Go to last post
  25. Closed: Using MIG design for virtex4 DDR2 SDRAM

    Started by yasamin, 9th November 2008 09:02
    • Replies: 5
    • Views: 3,334
    18th November 2008, 08:47 Go to last post
  26. Closed: PCB testing with FPGA (giving test vectors from FPGA)

    Started by vinod_g, 18th November 2008 04:28
    • Replies: 1
    • Views: 1,423
    18th November 2008, 07:01 Go to last post
  27. Closed: Problem in testbench with INOUT port

    Started by ashishnetam, 18th November 2008 05:42
    • Replies: 0
    • Views: 1,532
    18th November 2008, 05:42 Go to last post
  28. Closed: Read data from a ADC channel to PC via PCI on XtemeDSP Kit

    Started by xilinxgirl, 18th November 2008 01:47
    • Replies: 0
    • Views: 1,033
    18th November 2008, 01:47 Go to last post
  29. Closed: who can share the ampp ips (alera)?

    Started by niko_zhang, 16th November 2008 10:20
    • Replies: 0
    • Views: 771
    16th November 2008, 10:20 Go to last post
  30. Closed: DVI Controller for Xilinx FPGA

    Started by ehsan_noroz, 14th November 2008 06:12
    • Replies: 1
    • Views: 3,409
    16th November 2008, 01:34 Go to last post