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Threads 31 to 60 of 22858

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 10
    • Views: 773
    25th February 2020, 02:09 Go to last post
  1. Understanding Skid Buffer Mechanism

    Started by promach, 17th February 2020 06:53
    • Replies: 18
    • Views: 1,339
    24th February 2020, 17:43 Go to last post
  2. [SOLVED] Changing the ModelSim version that comes with Libero SoC v12.3

    Started by dpaul, 28th January 2020 10:47
    • Replies: 14
    • Views: 1,600
    24th February 2020, 12:07 Go to last post
  3. Error correction for video on microcontroller

    Started by Andrew2, 21st February 2020 22:27
    • Replies: 0
    • Views: 290
    21st February 2020, 22:27 Go to last post
  4. [SOLVED] Values of set/ reset when Instantiating ODDR?

    Started by ankit rajput, 20th February 2020 08:26
    • Replies: 3
    • Views: 443
    20th February 2020, 11:48 Go to last post
  5. Data transfer between HPS - FPGA using Python on HPS

    Started by johnny2231, 20th February 2020 08:59
    • Replies: 0
    • Views: 277
    20th February 2020, 08:59 Go to last post
    • Replies: 0
    • Views: 242
    20th February 2020, 03:07 Go to last post
  6. Problem in reading W5300 registers with Spartan6

    Started by tandis, 9th February 2020 10:07
    • Replies: 5
    • Views: 707
    19th February 2020, 17:08 Go to last post
  7. Is such goal achiveable - AVR Soft-Core

    Started by FlyingDutch, 16th February 2020 15:07
    • Replies: 3
    • Views: 659
    18th February 2020, 01:42 Go to last post
  8. 14 bit adc output to 5 bit data conversion in VHDL

    Started by prem ranjan, 17th February 2020 11:54
    • Replies: 3
    • Views: 613
    17th February 2020, 23:11 Go to last post
  9. Changing frequency of input clock port

    Started by kang78691, 17th February 2020 04:27
    • Replies: 1
    • Views: 334
    17th February 2020, 09:58 Go to last post
  10. Recommendations for Beginner

    Started by rafauy, 12th February 2020 10:32
    • Replies: 10
    • Views: 1,043
    16th February 2020, 10:05 Go to last post
  11. Problems about DFT and ADC in Impedance Converter

    Started by RoyYuen, 11th February 2020 09:17
    • Replies: 1
    • Views: 379
    11th February 2020, 09:54 Go to last post
  12. Receiving incorrect output at receiver FPGA

    Started by ankit rajput, 5th February 2020 10:48
    • Replies: 3
    • Views: 566
    9th February 2020, 08:48 Go to last post
  13. Quartus error 12006 'undefined entity'

    Started by barry, 7th February 2020 18:17
    • Replies: 6
    • Views: 734
    8th February 2020, 17:44 Go to last post
  14. How to create an IP core based on a project in ISE?

    Started by Cesar0182, 6th February 2020 15:13
    • Replies: 3
    • Views: 469
    6th February 2020, 23:17 Go to last post
  15. [SOLVED] Take different output value from array every clock cycle

    Started by Mai89, 4th February 2020 19:51
    • Replies: 2
    • Views: 386
    4th February 2020, 23:09 Go to last post
  16. [SOLVED] VHDL Simulation error using Xilinx ISE14.7

    Started by MSAKARIM, 28th January 2020 17:38
    • Replies: 15
    • Views: 1,260
    31st January 2020, 19:18 Go to last post
    • Replies: 1
    • Views: 334
    30th January 2020, 23:22 Go to last post
  17. Array storage in an FPGA, How is it handled?

    Started by FPGAwarrior, 28th January 2020 18:03
    • Replies: 5
    • Views: 562
    28th January 2020, 22:45 Go to last post
  18. ZYNQ Power Requirement

    Started by joniengr, 24th January 2020 17:57
    • Replies: 5
    • Views: 753
    27th January 2020, 17:16 Go to last post
    • Replies: 1
    • Views: 380
    26th January 2020, 11:09 Go to last post
    • Replies: 5
    • Views: 565
    24th January 2020, 14:02 Go to last post
    • Replies: 7
    • Views: 615
    23rd January 2020, 18:12 Go to last post
  19. Modelsim Microsemi Pro 2019.2

    Started by dpaul, 22nd January 2020 11:59
    • Replies: 3
    • Views: 562
    23rd January 2020, 12:18 Go to last post
    • Replies: 2
    • Views: 563
    16th January 2020, 16:51 Go to last post
  20. question regarding timing analysis or slack time

    Started by dayana42200, 13th January 2020 00:11
    • Replies: 3
    • Views: 602
    13th January 2020, 17:09 Go to last post
    • Replies: 2
    • Views: 625
    13th January 2020, 16:11 Go to last post
  21. ZYNQ 7Z030 LVDS IO - 910 Mbps and Ethernet

    Started by joniengr, 13th January 2020 11:45
    • Replies: 3
    • Views: 490
    13th January 2020, 15:00 Go to last post
  22. Free image fro PYNQ Z1

    Started by adwnis123, 22nd December 2019 20:30
    • Replies: 3
    • Views: 677
    9th January 2020, 13:13 Go to last post