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Threads 31 to 60 of 22789

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Reduce Net delay in FPGA synthesis?

    Started by Zerox100, 28th October 2019 15:29
    • Replies: 6
    • Views: 415
    28th October 2019, 23:02 Go to last post
    • Replies: 2
    • Views: 310
    23rd October 2019, 23:50 Go to last post
    • Replies: 2
    • Views: 290
    23rd October 2019, 06:45 Go to last post
  2. help please tosimulate this file

    Started by michael 1978, 21st October 2019 19:53
    • Replies: 6
    • Views: 594
    22nd October 2019, 21:17 Go to last post
    • Replies: 4
    • Views: 384
    21st October 2019, 22:48 Go to last post
  3. Open source RGMII Phy core for xilinx microblaze

    Started by aminpix, 21st October 2019 05:38
    • Replies: 0
    • Views: 263
    21st October 2019, 05:38 Go to last post
    • Replies: 5
    • Views: 699
    18th October 2019, 18:48 Go to last post
  4. Miller Decoder State machine

    Started by ejleiss, 17th October 2019 18:43
    • Replies: 0
    • Views: 275
    17th October 2019, 18:43 Go to last post
    • Replies: 2
    • Views: 383
    17th October 2019, 08:38 Go to last post
  5. Hardware implementation of problem

    Started by rrucha, 15th October 2019 17:27
    • Replies: 3
    • Views: 339
    16th October 2019, 01:06 Go to last post
    • Replies: 6
    • Views: 671
    15th October 2019, 17:47 Go to last post
    • Replies: 7
    • Views: 649
    14th October 2019, 16:56 Go to last post
  6. LTSSM state of PCIe and USR_LNK_UP assertion

    Started by vishnuk, 12th October 2019 11:38
    • Replies: 0
    • Views: 375
    12th October 2019, 11:38 Go to last post
  7. [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Started by yashjain, 2nd October 2019 15:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,296
    12th October 2019, 07:32 Go to last post
  8. Implementation of ADC

    Started by student21, 10th October 2019 11:07
    • Replies: 8
    • Views: 939
    11th October 2019, 21:39 Go to last post
  9. parameterized MUX implementation

    Started by rrucha, 9th October 2019 00:18
    • Replies: 3
    • Views: 375
    11th October 2019, 20:13 Go to last post
    • Replies: 11
    • Views: 808
    11th October 2019, 16:01 Go to last post
    • Replies: 14
    • Views: 950
    10th October 2019, 09:19 Go to last post
  10. Netlist Verilog to RTL or structrual to behavioral

    Started by s002wjhw, 9th October 2019 16:14
    • Replies: 0
    • Views: 215
    9th October 2019, 16:14 Go to last post
  11. Clock Skew problem in oserdes

    Started by beginner_EDA, 8th October 2019 15:31
    • Replies: 1
    • Views: 289
    9th October 2019, 12:23 Go to last post
    • Replies: 4
    • Views: 427
    7th October 2019, 23:12 Go to last post
    • Replies: 2
    • Views: 364
    5th October 2019, 10:14 Go to last post
  12. Testbench input stimulus

    Started by rogger201, 30th September 2019 19:14
    • Replies: 3
    • Views: 439
    4th October 2019, 22:45 Go to last post
    • Replies: 14
    • Views: 821
    4th October 2019, 18:48 Go to last post
  13. Help!! with MUX and Shift Registers in an architecture

    Started by Mai89, 29th September 2019 19:18
    • Replies: 3
    • Views: 364
    4th October 2019, 15:55 Go to last post
    • Replies: 3
    • Views: 464
    4th October 2019, 05:42 Go to last post
  14. Difference between TRN and AXI4-Stream

    Started by buenos, 3rd October 2019 21:37
    • Replies: 2
    • Views: 358
    3rd October 2019, 23:37 Go to last post
    • Replies: 14
    • Views: 898
    3rd October 2019, 19:30 Go to last post
  15. Data string length to be send out from FPGA

    Started by Vlad., 2nd October 2019 10:44
    • Replies: 4
    • Views: 422
    2nd October 2019, 17:03 Go to last post