1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    108,951
Page 2 of 744 FirstFirst 1 2 3 4 12 52 102 502 ... LastLast
Threads 31 to 60 of 22302

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 6
    • Views: 481
    23rd June 2018, 07:23 Go to last post
    • Replies: 11
    • Views: 623
    22nd June 2018, 15:30 Go to last post
  1. selection of devboard for hobby project

    Started by theUltimateSource, 18th June 2018 16:37
    • Replies: 7
    • Views: 389
    21st June 2018, 15:22 Go to last post
    • Replies: 4
    • Views: 268
    20th June 2018, 07:16 Go to last post
  2. Verilog code for BCD to Floating point representation

    Started by adhul, 11th June 2018 07:32
    2 Pages
    1 2
    • Replies: 32
    • Views: 1,067
    20th June 2018, 06:30 Go to last post
  3. [SOLVED] Is there a way to change default programmer port?

    Started by Mohammad Amin Nili, 20th May 2018 23:22
    • Replies: 4
    • Views: 477
    18th June 2018, 11:44 Go to last post
  4. [moved] appropriate algorithm for video encryption

    Started by amin5659, 14th June 2018 17:45
    • Replies: 6
    • Views: 470
    16th June 2018, 07:51 Go to last post
  5. FPGA development Kit

    Started by alikhan968, 12th June 2018 19:26
    • Replies: 7
    • Views: 438
    14th June 2018, 09:17 Go to last post
  6. [SOLVED] this code for interfacing ADC 122S101 is not working

    Started by adhul, 15th May 2018 07:44
    • Replies: 14
    • Views: 1,001
    13th June 2018, 10:23 Go to last post
    •  
    •  
  7. key scheduling present-80 vhdl cryptography

    Started by kumatul123, 12th June 2018 14:57
    • Replies: 2
    • Views: 169
    12th June 2018, 16:33 Go to last post
  8. Moved: Verilog code for BCD to Floating point representation

    Started by adhul, 12th June 2018 11:10
    •  
    •  
  9. Help - ATM With VHDL (to store passwords)

    Started by OmegaRazr, 9th June 2018 05:25
    • Replies: 6
    • Views: 467
    12th June 2018, 07:05 Go to last post
  10. Implementing a computer vision algorithm on a FPGA

    Started by synths, 10th June 2018 04:18
    • Replies: 6
    • Views: 385
    11th June 2018, 13:48 Go to last post
    • Replies: 17
    • Views: 799
    10th June 2018, 14:44 Go to last post
    • Replies: 5
    • Views: 333
    9th June 2018, 00:55 Go to last post
    • Replies: 7
    • Views: 961
    8th June 2018, 15:26 Go to last post
  11. Hardware Utilization Efficiency

    Started by rafimiet, 6th June 2018 18:17
    • Replies: 1
    • Views: 173
    6th June 2018, 18:40 Go to last post
  12. Implemtation Mapper Error

    Started by sandhiyaselvaraj, 31st May 2018 05:55
    • Replies: 3
    • Views: 246
    5th June 2018, 14:09 Go to last post
  13. Mux exercise. Is it right?

    Started by Romadness, 30th May 2018 14:56
    • Replies: 16
    • Views: 1,016
    5th June 2018, 07:27 Go to last post
  14. [SOLVED] ModelSim tcl directory path

    Started by nsgil85, 4th June 2018 14:28
    • Replies: 2
    • Views: 237
    4th June 2018, 16:12 Go to last post
  15. Creating real-time data log of FPGA sensor readings

    Started by JaySeo, 14th May 2018 00:43
    • Replies: 5
    • Views: 513
    4th June 2018, 15:24 Go to last post
    • Replies: 1
    • Views: 261
    4th June 2018, 10:13 Go to last post
  16. PL to PS interrupt:how to acess in arm processor

    Started by dipin, 31st May 2018 14:08
    • Replies: 3
    • Views: 334
    4th June 2018, 08:47 Go to last post
  17. Bidirectional overhead arrays

    Started by Saltwater, 27th May 2018 13:30
    • Replies: 18
    • Views: 882
    31st May 2018, 14:33 Go to last post