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Threads 31 to 60 of 22750

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] Shift register implementation and use of its value

    Started by rogger201, 23rd September 2019 21:27
    2 Pages
    1 2
    • Replies: 22
    • Views: 809
    26th September 2019, 17:48 Go to last post
  2. MMCM Clocking Wizard

    Started by Roronoa137, 26th September 2019 08:20
    • Replies: 1
    • Views: 183
    26th September 2019, 15:55 Go to last post
  3. VHDL integer to integer multiplication

    Started by shaiko, 25th September 2019 11:48
    • Replies: 3
    • Views: 213
    25th September 2019, 13:22 Go to last post
    • Replies: 5
    • Views: 225
    25th September 2019, 13:06 Go to last post
  4. Moved: Shift register implementation without load signal

    Started by rogger201, 23rd September 2019 22:29
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  5. SPI communication in SDK

    Started by Roronoa137, 13th September 2019 14:36
    • Replies: 9
    • Views: 758
    22nd September 2019, 02:05 Go to last post
  6. parameterized insertion of bits to data

    Started by rrucha, 18th September 2019 22:44
    • Replies: 10
    • Views: 555
    21st September 2019, 08:45 Go to last post
  7. Multiplexer output width depends on SELECT

    Started by rrucha, 13th September 2019 18:10
    • Replies: 17
    • Views: 955
    20th September 2019, 08:40 Go to last post
    • Replies: 2
    • Views: 236
    18th September 2019, 10:50 Go to last post
  8. [SOLVED] Need help creating Vivado Timing Constraint

    Started by wesleytaylor, 17th September 2019 12:27
    • Replies: 6
    • Views: 299
    17th September 2019, 18:05 Go to last post
  9. [SOLVED] Suppressing the spacing in $fwrite command of Verilog

    Started by tahirsengine, 17th September 2019 09:17
    • Replies: 3
    • Views: 207
    17th September 2019, 15:52 Go to last post
  10. PLDA drivers needed Windows x64

    Started by paradapa, 15th September 2019 12:24
    • Replies: 0
    • Views: 168
    15th September 2019, 12:24 Go to last post
    • Replies: 5
    • Views: 377
    14th September 2019, 06:53 Go to last post
  11. Using calculated CRC as seed for the next CRC calculation

    Started by rrucha, 12th September 2019 00:27
    • Replies: 4
    • Views: 367
    12th September 2019, 22:06 Go to last post
  12. [moved] VHDL of input capture and output compare

    Started by natalfra, 12th September 2019 14:51
    • Replies: 8
    • Views: 388
    12th September 2019, 21:58 Go to last post
    • Replies: 1
    • Views: 130
    12th September 2019, 21:19 Go to last post
    • Replies: 9
    • Views: 626
    12th September 2019, 18:12 Go to last post
  13. Unable to run the simulation correctly ( Modelsim )

    Started by bravo1234, 11th September 2019 08:44
    • Replies: 2
    • Views: 230
    11th September 2019, 16:16 Go to last post
    • Replies: 5
    • Views: 368
    11th September 2019, 12:00 Go to last post
  14. [SOLVED] VHDL scope vs visibility vs visibility by selection

    Started by wesleytaylor, 10th September 2019 09:23
    • Replies: 3
    • Views: 252
    10th September 2019, 16:16 Go to last post
  15. [SOLVED] problem with programming the xilinx fpga

    Started by hamidkavianathar, 25th August 2019 13:23
    • Replies: 4
    • Views: 833
    8th September 2019, 13:23 Go to last post
    • Replies: 2
    • Views: 440
    7th September 2019, 09:49 Go to last post
  16. CDC - How make merge data after conversion?

    Started by arkadyy, 5th September 2019 13:25
    • Replies: 10
    • Views: 611
    6th September 2019, 22:15 Go to last post
  17. Sine function generator (VHDL)

    Started by FlyingDutch, 11th August 2019 15:33
    • Replies: 6
    • Views: 717
    5th September 2019, 17:35 Go to last post
  18. Inferred VHDL dual port RAM template

    Started by shaiko, 30th August 2019 00:01
    • Replies: 7
    • Views: 581
    5th September 2019, 11:56 Go to last post
  19. ERROR:HDLParsers:709

    Started by abimann, 4th September 2019 08:05
    • Replies: 2
    • Views: 324
    4th September 2019, 09:04 Go to last post
  20. HELP ME the newbie with Verilog Code

    Started by ridhohrnf, 3rd September 2019 18:07
    • Replies: 3
    • Views: 297
    4th September 2019, 08:28 Go to last post
    • Replies: 12
    • Views: 1,275
    3rd September 2019, 15:48 Go to last post
  21. pcie hard ip altera- latency problem

    Started by manush30, 3rd September 2019 09:04
    • Replies: 3
    • Views: 450
    3rd September 2019, 13:26 Go to last post
  22. Switching between more bit-streams on FPGA

    Started by MSAKARIM, 29th August 2019 20:58
    • Replies: 2
    • Views: 555
    1st September 2019, 14:40 Go to last post