1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    115,140
Page 2 of 750 FirstFirst 1 2 3 4 12 52 102 502 ... LastLast
Threads 31 to 60 of 22487

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 4
    • Views: 529
    12th December 2018, 09:29 Go to last post
  1. Xilinx XPower Analyzer Confidence Level

    Started by dayana42200, 10th December 2018 02:38
    • Replies: 4
    • Views: 420
    12th December 2018, 00:09 Go to last post
  2. Fixed point complex numbers in sdSOC

    Started by Radhikamkr, 10th December 2018 13:34
    • Replies: 0
    • Views: 220
    10th December 2018, 13:34 Go to last post
  3. Design a 4-core processor on FPGA

    Started by adwnis123, 7th December 2018 15:11
    • Replies: 9
    • Views: 629
    8th December 2018, 18:02 Go to last post
  4. Why Quarus Prime is uninstalled after restart a Windows?

    Started by frdm90, 5th December 2018 16:40
    • Replies: 4
    • Views: 295
    6th December 2018, 17:01 Go to last post
  5. Generating SAIF file

    Started by dayana42200, 3rd December 2018 02:43
    • Replies: 7
    • Views: 521
    6th December 2018, 01:43 Go to last post
    • Replies: 4
    • Views: 289
    4th December 2018, 18:03 Go to last post
  6. VHDL unconstrained array in VCS

    Started by shaiko, 4th December 2018 13:13
    • Replies: 2
    • Views: 199
    4th December 2018, 14:31 Go to last post
  7. Spartan-6 Servo Control

    Started by prakash_kadri, 28th November 2018 12:04
    • Replies: 6
    • Views: 528
    30th November 2018, 02:54 Go to last post
  8. Best Way to Implement Shared RAM

    Started by groover, 26th November 2018 21:46
    2 Pages
    1 2
    • Replies: 25
    • Views: 878
    29th November 2018, 23:17 Go to last post
  9. Propper clock generation for SPI protocol

    Started by Ironlord, 27th November 2018 13:05
    • Replies: 14
    • Views: 616
    29th November 2018, 13:24 Go to last post
  10. Using different time units in Verilog simulation

    Started by shaiko, 25th November 2018 00:09
    • Replies: 2
    • Views: 332
    26th November 2018, 16:52 Go to last post
  11. [SOLVED] Instantiating module with inout

    Started by ranayehya, 26th November 2018 08:03
    • Replies: 4
    • Views: 262
    26th November 2018, 15:23 Go to last post
  12. Definitions for a Memory in Verilog

    Started by groover, 25th November 2018 20:49
    • Replies: 0
    • Views: 243
    25th November 2018, 20:49 Go to last post
    • Replies: 2
    • Views: 232
    25th November 2018, 20:40 Go to last post
  13. System Verilog - default type of a declared variable

    Started by shaiko, 24th November 2018 18:53
    • Replies: 7
    • Views: 424
    25th November 2018, 15:39 Go to last post
  14. Parameter location in a Verilog Module

    Started by shaiko, 24th November 2018 20:12
    • Replies: 1
    • Views: 181
    24th November 2018, 20:28 Go to last post
  15. Verilog & System Verilog - port sizing by inheritance

    Started by shaiko, 24th November 2018 13:43
    • Replies: 1
    • Views: 204
    24th November 2018, 15:48 Go to last post
  16. Implement I2C in VHDL

    Started by Ironlord, 16th October 2018 07:47
    3 Pages
    1 2 3
    • Replies: 55
    • Views: 2,423
    23rd November 2018, 13:02 Go to last post
    • Replies: 3
    • Views: 233
    22nd November 2018, 21:16 Go to last post
  17. reorder queue mechanism

    Started by promach, 18th September 2018 04:33
    • Replies: 10
    • Views: 962
    20th November 2018, 09:10 Go to last post
  18. FPGA ALM or LAB estimated size

    Started by PablodlR, 29th October 2018 13:14
    • Replies: 6
    • Views: 543
    20th November 2018, 07:26 Go to last post
  19. Verilog Synchronize with External Signal

    Started by groover, 18th November 2018 21:44
    • Replies: 4
    • Views: 350
    20th November 2018, 00:36 Go to last post
    • Replies: 4
    • Views: 349
    18th November 2018, 01:19 Go to last post
  20. ZYNQ - XADC example ZedBoard or ZYBO

    Started by joniengr, 15th November 2018 16:42
    • Replies: 1
    • Views: 270
    16th November 2018, 10:38 Go to last post
  21. Tracking 'X' in the gate lavel simulation

    Started by filip.amator, 10th November 2018 11:32
    • Replies: 5
    • Views: 451
    14th November 2018, 18:11 Go to last post
  22. Design of a PCIe card with USB and Ethernet

    Started by HasHx, 7th November 2018 19:29
    • Replies: 7
    • Views: 732
    14th November 2018, 05:59 Go to last post
  23. [SOLVED] VHDL Aliases advanced usecase of name signment

    Started by wesleytaylor, 6th November 2018 18:01
    • Replies: 6
    • Views: 410
    9th November 2018, 20:00 Go to last post
  24. Initial value depending on the input

    Started by bremenpl, 8th November 2018 08:53
    • Replies: 10
    • Views: 620
    9th November 2018, 09:03 Go to last post
  25. SPI verilog testbench code

    Started by promach, 21st October 2018 16:30
    • Replies: 6
    • Views: 754
    9th November 2018, 04:54 Go to last post