1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    107,967
Page 2 of 743 FirstFirst 1 2 3 4 12 52 102 502 ... LastLast
Threads 31 to 60 of 22273

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Moved: [SOLVED] Logic Gates with MUX: 2 XOR, 1AND

    Started by Romadness, 2nd June 2018 17:50
    •  
    •  
  2. Xilinx Virtex 5 vs. Xilinx Spartan 3e 500k

    Started by adwnis123, 29th May 2018 18:37
    • Replies: 8
    • Views: 450
    30th May 2018, 19:23 Go to last post
  3. how to poll a status bit in verilog

    Started by gary36, 28th May 2018 15:12
    • Replies: 6
    • Views: 317
    29th May 2018, 17:44 Go to last post
  4. [SOLVED] Controlling a servomotor " SG90 9g Mirco Servo " with Basys 3

    Started by vlad97, 28th May 2018 13:34
    • Replies: 1
    • Views: 194
    28th May 2018, 19:04 Go to last post
  5. [moved] Simulator and synthesis tool required

    Started by sky_above, 24th May 2018 14:14
    • Replies: 13
    • Views: 604
    28th May 2018, 17:11 Go to last post
    • Replies: 4
    • Views: 310
    27th May 2018, 11:00 Go to last post
    • Replies: 4
    • Views: 225
    24th May 2018, 20:01 Go to last post
  6. Bipolar stepper motor code in VHDL ?

    Started by abimann, 24th May 2018 08:48
    • Replies: 1
    • Views: 153
    24th May 2018, 08:55 Go to last post
  7. Simulink VFC via FPGA on matlab

    Started by skyfall_133, 23rd May 2018 18:12
    • Replies: 0
    • Views: 146
    23rd May 2018, 18:12 Go to last post
    • Replies: 2
    • Views: 234
    22nd May 2018, 07:20 Go to last post
    • Replies: 5
    • Views: 325
    21st May 2018, 15:24 Go to last post
  8. [SOLVED] problem simulating a simple counter in VHDL with Vivado

    Started by joseMiguel, 19th May 2018 21:56
    • Replies: 5
    • Views: 333
    21st May 2018, 14:19 Go to last post
  9. [SOLVED] Best way to decodebits and attribute 0 to not used registers.

    Started by pbernardi, 19th May 2018 17:32
    • Replies: 3
    • Views: 215
    19th May 2018, 23:06 Go to last post
  10. Learning SystemVerilog

    Started by Peddro, 17th May 2018 10:59
    • Replies: 7
    • Views: 490
    18th May 2018, 08:26 Go to last post
  11. VHDL Design Verification

    Started by expertengr, 15th May 2018 13:57
    • Replies: 5
    • Views: 351
    15th May 2018, 18:02 Go to last post
  12. UVC for FPGA Internal side

    Started by paulr127, 15th May 2018 17:03
    • Replies: 1
    • Views: 138
    15th May 2018, 18:00 Go to last post
  13. Unknown Clock Signal

    Started by sandy2811, 14th May 2018 07:13
    • Replies: 5
    • Views: 332
    14th May 2018, 21:17 Go to last post
  14. Numerical computation in FPGA

    Started by gary36, 9th May 2018 16:25
    • Replies: 10
    • Views: 585
    12th May 2018, 09:38 Go to last post
  15. simulation problem in verilog

    Started by NEHA12345, 11th May 2018 13:06
    • Replies: 2
    • Views: 208
    11th May 2018, 15:12 Go to last post
  16. MachXO2 and SFP transceiver data issues

    Started by juanMco, 11th May 2018 13:21
    • Replies: 2
    • Views: 221
    11th May 2018, 13:57 Go to last post
  17. Spartan-3AN Nor Flash problem

    Started by m_farahani, 10th May 2018 20:05
    • Replies: 0
    • Views: 191
    10th May 2018, 20:05 Go to last post
    • Replies: 8
    • Views: 409
    10th May 2018, 17:52 Go to last post
  18. Is sGDMA integration correct in this SoC ??

    Started by hcu, 9th May 2018 14:48
    • Replies: 4
    • Views: 244
    10th May 2018, 05:49 Go to last post
    • Replies: 1
    • Views: 206
    8th May 2018, 18:37 Go to last post
  19. Tracing internal signals in Modelsim

    Started by mjuneja, 1st May 2018 10:55
    • Replies: 10
    • Views: 662
    8th May 2018, 11:18 Go to last post
  20. Creating an FPGA accelerator in 15 minutes

    Started by dipin, 4th May 2018 12:23
    • Replies: 2
    • Views: 339
    4th May 2018, 14:26 Go to last post
  21. Programmer and Logic Analyzer question

    Started by kkeeley, 2nd May 2018 01:00
    • Replies: 11
    • Views: 622
    3rd May 2018, 15:55 Go to last post