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Threads 31 to 60 of 22390

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Calling VHDL code in Verilog Code

    Started by manjunath_crl, 7th September 2018 08:17
    • Replies: 4
    • Views: 252
    8th September 2018, 14:00 Go to last post
  2. lookup table implementation in verilog

    Started by krishvamsi, 30th August 2018 07:22
    • Replies: 16
    • Views: 712
    8th September 2018, 00:30 Go to last post
  3. Pynq: Python productivity for zynq

    Started by adwnis123, 7th September 2018 23:01
    • Replies: 2
    • Views: 216
    7th September 2018, 23:26 Go to last post
    • Replies: 8
    • Views: 341
    7th September 2018, 13:36 Go to last post
    • Replies: 5
    • Views: 583
    5th September 2018, 23:08 Go to last post
  4. Verilog : synthesis Error

    Started by AbinayaSivam, 4th September 2018 08:37
    • Replies: 11
    • Views: 451
    5th September 2018, 15:37 Go to last post
  5. Moved: Floating point representation in Verilog

    Started by krishvamsi, 4th September 2018 07:22
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  6. Writing a ROM in verilog

    Started by ranayehya, 1st September 2018 21:35
    • Replies: 10
    • Views: 501
    3rd September 2018, 23:50 Go to last post
    • Replies: 8
    • Views: 283
    3rd September 2018, 22:19 Go to last post
  7. OSERDES implementation and connections

    Started by Alauddin123, 3rd September 2018 06:08
    • Replies: 2
    • Views: 169
    3rd September 2018, 21:52 Go to last post
    • Replies: 19
    • Views: 797
    31st August 2018, 05:40 Go to last post
    • Replies: 2
    • Views: 174
    30th August 2018, 07:32 Go to last post
  8. [SOLVED] Which simulator supports unconstrained record elements?

    Started by theUltimateSource, 29th August 2018 09:40
    • Replies: 4
    • Views: 218
    29th August 2018, 23:46 Go to last post
  9. FRAM with DDR interface

    Started by Raguvaran, 29th August 2018 15:53
    • Replies: 1
    • Views: 165
    29th August 2018, 18:38 Go to last post
  10. Transition Probability

    Started by kshirod_vlsi, 28th August 2018 11:50
    • Replies: 6
    • Views: 266
    29th August 2018, 14:18 Go to last post
  11. ADV7619 detection by PC

    Started by PablodlR, 29th August 2018 10:37
    • Replies: 0
    • Views: 129
    29th August 2018, 10:37 Go to last post
  12. Warning in Vivado Design Suite during synthesis

    Started by Radhikamkr, 27th August 2018 23:22
    • Replies: 1
    • Views: 239
    28th August 2018, 04:08 Go to last post
    • Replies: 0
    • Views: 126
    28th August 2018, 03:04 Go to last post
  13. Number of FIFOs in ALTERA De2-115

    Started by fatimamaz, 27th August 2018 08:16
    • Replies: 3
    • Views: 244
    27th August 2018, 11:01 Go to last post
  14. Lookup table implementation in Verilog

    Started by krishvamsi, 25th August 2018 17:49
    • Replies: 5
    • Views: 477
    26th August 2018, 18:34 Go to last post
  15. [SOLVED] record issue with quartus 15.1

    Started by nsgil85, 21st August 2018 15:31
    • Replies: 7
    • Views: 452
    26th August 2018, 11:27 Go to last post
  16. [SOLVED] FSM model in verilog

    Started by jasmine123, 23rd August 2018 09:27
    • Replies: 9
    • Views: 662
    26th August 2018, 10:08 Go to last post
  17. [SOLVED] Using Xilinx fft core

    Started by Radhikamkr, 23rd July 2018 05:26
    • Replies: 11
    • Views: 809
    24th August 2018, 23:46 Go to last post
    • Replies: 1
    • Views: 183
    22nd August 2018, 11:10 Go to last post
  18. Support for "Jagged" array in modern HDLs

    Started by shaiko, 20th August 2018 22:32
    • Replies: 14
    • Views: 540
    22nd August 2018, 10:58 Go to last post
  19. XML file generation from VHDL/Verilog

    Started by tahirsengine, 21st August 2018 09:34
    • Replies: 7
    • Views: 303
    22nd August 2018, 08:11 Go to last post
  20. Video codec IC selection

    Started by kiransbaddi, 19th August 2018 12:10
    • Replies: 1
    • Views: 161
    21st August 2018, 20:20 Go to last post
  21. [SOLVED] while condition in verilog

    Started by jasmine123, 20th August 2018 08:41
    • Replies: 2
    • Views: 207
    20th August 2018, 15:27 Go to last post
    • Replies: 1
    • Views: 280
    20th August 2018, 14:04 Go to last post
  22. [SOLVED] std_logic conversion

    Started by nsgil85, 19th August 2018 13:10
    • Replies: 9
    • Views: 365
    19th August 2018, 18:31 Go to last post