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Threads 331 to 360 of 22273

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Xilinx ISE - readmemh system task taking too much time

    Started by NikosTS, 14th November 2017 11:36
    • Replies: 1
    • Views: 695
    17th November 2017, 07:11 Go to last post
    • Replies: 1
    • Views: 816
    16th November 2017, 17:04 Go to last post
  2. Closed: VHDL coding techniques

    Started by manishpatkar, 13th November 2017 12:55
    • Replies: 16
    • Views: 1,849
    16th November 2017, 15:01 Go to last post
  3. Closed: Missing JESD parameters in Xilinx JESD204 IP Rx!!

    Started by samg, 15th November 2017 05:46
    • Replies: 2
    • Views: 722
    15th November 2017, 11:31 Go to last post
  4. Closed: SEM IP instantiation on Zedboard and rx-tx ports problem

    Started by msdarvishi, 14th November 2017 02:00
    • Replies: 5
    • Views: 1,017
    14th November 2017, 23:20 Go to last post
    • Replies: 1
    • Views: 521
    14th November 2017, 18:17 Go to last post
  5. Closed: Sending data sequentially

    Started by beginner_EDA, 8th November 2017 12:42
    • Replies: 6
    • Views: 894
    14th November 2017, 13:24 Go to last post
  6. Closed: Can anyone suggest a paper, materials about ( IoT Hardware Security )

    Started by Morhaf, 12th November 2017 08:44
    • Replies: 3
    • Views: 1,207
    13th November 2017, 21:38 Go to last post
  7. Closed: [Moved]How to convert a vhdl code to verilog code

    Started by nagulapatigirireddy, 11th November 2017 18:58
    • Replies: 3
    • Views: 1,602
    13th November 2017, 12:00 Go to last post
  8. Closed: Configuring JESD parameters in Xilinx JESD204

    Started by samg, 13th November 2017 07:01
    • Replies: 0
    • Views: 673
    13th November 2017, 07:01 Go to last post
  9. Closed: How to implement FSK modulator/demodulator on FPGA?

    Started by hamidkavianathar, 11th November 2017 07:01
    • Replies: 1
    • Views: 1,252
    11th November 2017, 13:03 Go to last post
  10. [SOLVED]Closed: Programmable Priority Encoder

    Started by RatedR, 13th July 2017 17:00
    2 Pages
    1 2
    • Replies: 31
    • Views: 4,887
    10th November 2017, 17:33 Go to last post
  11. Closed: Signal ignoring initializers and initializing to random state

    Started by alexandicity, 8th November 2017 03:07
    • Replies: 12
    • Views: 1,850
    9th November 2017, 20:04 Go to last post
  12. Closed: UCF file conversion from Spartan-6 to Virtex-5 XC5VLX20T ff323

    Started by qaziarbab, 9th November 2017 15:23
    • Replies: 1
    • Views: 614
    9th November 2017, 17:10 Go to last post
  13. Closed: ModelSim Equivalent of Active-HDL's Path Coverage Option

    Started by derelaut, 7th November 2017 19:10
    • Replies: 3
    • Views: 782
    8th November 2017, 18:49 Go to last post
    • Replies: 2
    • Views: 517
    8th November 2017, 13:03 Go to last post
  14. Closed: Unable to interface a VGA screen with a FPGA development board

    Started by garvind25, 27th October 2017 10:29
    • Replies: 14
    • Views: 2,558
    8th November 2017, 02:58 Go to last post
  15. Closed: How to Run C application on MC 8051 design using Xilinix isim.

    Started by qaziarbab, 7th November 2017 15:00
    • Replies: 3
    • Views: 586
    7th November 2017, 18:30 Go to last post
  16. Closed: LCD code for fpga virtex 6

    Started by moonshine8995, 6th November 2017 12:39
    • Replies: 3
    • Views: 883
    7th November 2017, 13:08 Go to last post
  17. Closed: Verilog basic coding/naming conventions

    Started by pigtwo, 4th November 2017 21:53
    • Replies: 7
    • Views: 1,353
    6th November 2017, 04:44 Go to last post
  18. [SOLVED]Closed: Latches create in verilog code

    Started by tayyab786, 3rd November 2017 06:03
    • Replies: 6
    • Views: 1,371
    5th November 2017, 16:47 Go to last post
  19. [SOLVED]Closed: inout port in an inner component

    Started by rafimiet, 4th November 2017 06:07
    • Replies: 9
    • Views: 1,162
    5th November 2017, 00:32 Go to last post
    • Replies: 4
    • Views: 778
    3rd November 2017, 17:34 Go to last post
  20. Closed: Active HDL vs Models performance

    Started by shaiko, 3rd November 2017 15:45
    • Replies: 1
    • Views: 612
    3rd November 2017, 16:22 Go to last post
  21. Closed: Modelsim console configuration

    Started by wesleytaylor, 2nd November 2017 18:16
    • Replies: 0
    • Views: 813
    2nd November 2017, 18:16 Go to last post
  22. [SOLVED]Closed: VHDL - Unknown identify

    Started by wesleytaylor, 30th October 2017 12:13
    • Replies: 4
    • Views: 886
    2nd November 2017, 00:08 Go to last post
  23. Closed: embedded Atmel and virtex-4 Using iMPACT tool over ICSP

    Started by sami_melish, 31st October 2017 13:11
    • Replies: 3
    • Views: 890
    1st November 2017, 19:08 Go to last post
  24. Closed: Concatination problem in port map in vhdl

    Started by moonshine8995, 28th October 2017 07:24
    • Replies: 3
    • Views: 735
    1st November 2017, 15:38 Go to last post
  25. [SOLVED]Closed: VHDL - Illegal choice in record aggregate.

    Started by wesleytaylor, 30th October 2017 14:02
    • Replies: 5
    • Views: 944
    1st November 2017, 15:37 Go to last post
  26. Closed: FX3 Watermark calculation

    Started by player80, 1st November 2017 11:50
    • Replies: 0
    • Views: 678
    1st November 2017, 11:50 Go to last post