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Threads 301 to 330 of 22858

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Time multiplexing with LED

    Started by eengr, 29th March 2019 18:41
    • Replies: 4
    • Views: 1,075
    2nd April 2019, 20:58 Go to last post
    • Replies: 5
    • Views: 976
    2nd April 2019, 15:43 Go to last post
  2. Closed: Posit Arithmetic VS Floating-Point (IEEE 754) Arithmetic

    Started by promach, 23rd March 2019 03:14
    • Replies: 8
    • Views: 1,847
    1st April 2019, 11:16 Go to last post
  3. Closed: Pipelining 32 Bit Multiplier in Verilog

    Started by AlinParcalab, 27th March 2019 17:04
    • Replies: 9
    • Views: 1,800
    1st April 2019, 09:35 Go to last post
  4. [SOLVED]Closed: Using if-else generate to make dynamic hardware implementation using FPGA

    Started by MSAKARIM, 22nd March 2019 11:54
    • Replies: 18
    • Views: 3,629
    1st April 2019, 08:08 Go to last post
  5. Closed: Buffer backpressure for on-off flow control

    Started by promach, 1st April 2019 04:58
    • Replies: 0
    • Views: 341
    1st April 2019, 04:58 Go to last post
  6. Closed: Stochastic rounding for floating point

    Started by oAwad, 31st March 2019 00:19
    • Replies: 3
    • Views: 1,320
    31st March 2019, 20:49 Go to last post
  7. Closed: Need USB3 FTDI or cypress HDL code

    Started by jalalba, 30th March 2019 09:44
    • Replies: 1
    • Views: 344
    31st March 2019, 07:57 Go to last post
  8. [SOLVED]Closed: RGMII problem with MAX 10 Development board

    Started by Humusk, 28th March 2019 19:08
    • Replies: 4
    • Views: 1,199
    29th March 2019, 13:19 Go to last post
  9. Closed: How to interface 1.2V FPGA IO bank to 0.6V DDR style memory

    Started by rob2966, 28th March 2019 05:37
    • Replies: 2
    • Views: 561
    28th March 2019, 14:36 Go to last post
  10. Closed: Parent signal when alias is accessed

    Started by shaiko, 26th March 2019 20:20
    • Replies: 7
    • Views: 1,626
    27th March 2019, 08:38 Go to last post
  11. Closed: Color sensor and Basys3 with VHDL

    Started by kmesne, 18th March 2019 19:18
    • Replies: 5
    • Views: 1,530
    26th March 2019, 17:42 Go to last post
  12. Closed: Verilog code to find modular inverse value

    Started by Poomagal, 21st March 2019 08:09
    • Replies: 7
    • Views: 1,710
    26th March 2019, 09:30 Go to last post
  13. [SOLVED]Closed: VHDL coding Status register read problem

    Started by eengr, 15th March 2019 18:35
    • Replies: 6
    • Views: 1,819
    25th March 2019, 15:13 Go to last post
  14. Closed: Cadence aging model for aging simulation

    Started by antlhem, 23rd March 2019 18:39
    • Replies: 1
    • Views: 870
    24th March 2019, 03:15 Go to last post
  15. [SOLVED]Closed: VHDL Counter Clock issue

    Started by eengr, 21st March 2019 18:59
    • Replies: 1
    • Views: 496
    23rd March 2019, 16:20 Go to last post
    • Replies: 7
    • Views: 1,624
    22nd March 2019, 19:15 Go to last post
  16. Closed: CDC for constant signal

    Started by achaleus, 21st March 2019 14:18
    • Replies: 4
    • Views: 786
    22nd March 2019, 16:04 Go to last post
  17. [SOLVED]Closed: VHDL-2008 Support simulation and implementation

    Started by MSAKARIM, 22nd March 2019 11:41
    • Replies: 1
    • Views: 413
    22nd March 2019, 12:08 Go to last post
    • Replies: 18
    • Views: 2,409
    19th March 2019, 00:18 Go to last post
  18. Closed: Green/Red detector and button controlled car (BASYS3/VHDL)

    Started by kmesne, 13th March 2019 21:39
    • Replies: 4
    • Views: 726
    18th March 2019, 14:19 Go to last post
  19. Closed: Negative Slack / Report Analysis

    Started by player80, 9th March 2019 05:37
    2 Pages
    1 2
    • Replies: 21
    • Views: 1,747
    16th March 2019, 18:00 Go to last post
  20. [SOLVED]Closed: VHDL code Counter problem

    Started by eengr, 13th March 2019 19:20
    • Replies: 5
    • Views: 1,397
    15th March 2019, 18:00 Go to last post
  21. Closed: Triangular wave generator in FPGA

    Started by Ironlord, 15th March 2019 09:14
    • Replies: 2
    • Views: 994
    15th March 2019, 13:32 Go to last post
  22. Closed: Spidergon Networks-on-Chips verilog code implementation

    Started by promach, 13th March 2019 05:44
    • Replies: 0
    • Views: 509
    13th March 2019, 05:44 Go to last post
    • Replies: 4
    • Views: 2,571
    12th March 2019, 23:29 Go to last post
  23. Closed: Why my 2-digit counter w/VHDL didn't work?

    Started by huytergan, 12th March 2019 12:44
    • Replies: 5
    • Views: 538
    12th March 2019, 15:28 Go to last post
  24. Closed: Looking for XABEL-CPLD package DS-571-PC1 for XACT software

    Started by Zag4cpld, 12th March 2019 01:52
    • Replies: 0
    • Views: 236
    12th March 2019, 01:52 Go to last post
  25. Closed: FPGA vendors outside USA

    Started by bga72, 11th March 2019 17:59
    • Replies: 3
    • Views: 713
    11th March 2019, 20:48 Go to last post
    • Replies: 3
    • Views: 1,118
    11th March 2019, 14:22 Go to last post