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Threads 301 to 330 of 22389

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Send Serial data through RS-232

    Started by fatimamaz, 29th January 2018 14:56
    • Replies: 5
    • Views: 975
    12th February 2018, 10:59 Go to last post
  2. Closed: Test bench for simple Register file

    Started by fadia, 11th February 2018 04:52
    • Replies: 0
    • Views: 766
    11th February 2018, 04:52 Go to last post
  3. Closed: Altera DE4 PCIe linux driver

    Started by promach, 8th February 2018 13:37
    • Replies: 4
    • Views: 657
    9th February 2018, 17:21 Go to last post
  4. Closed: Idelayctrl, idelay, odelay....

    Started by velu.plg, 9th February 2018 10:54
    • Replies: 1
    • Views: 617
    9th February 2018, 12:58 Go to last post
  5. Closed: Questions on Asynchronous FIFO

    Started by promach, 30th January 2018 03:44
    • Replies: 8
    • Views: 863
    9th February 2018, 05:51 Go to last post
  6. Closed: Why FPGA Development boards are cheaper than actual FPGA Chip

    Started by anandpv2009, 8th February 2018 19:35
    • Replies: 6
    • Views: 819
    9th February 2018, 02:52 Go to last post
  7. Closed: 1 HZ square wave generation without giving clock as input signal.

    Started by jasi, 4th February 2018 14:20
    • Replies: 11
    • Views: 1,297
    8th February 2018, 22:52 Go to last post
    • Replies: 1
    • Views: 568
    8th February 2018, 08:42 Go to last post
  8. Closed: How to reduce the Data Delay time constraint?

    Started by Hugo17, 8th February 2018 08:28
    • Replies: 0
    • Views: 483
    8th February 2018, 08:28 Go to last post
  9. Closed: Digital circuit to divide larger bits into smaller bits

    Started by mthakur, 30th January 2018 07:34
    • Replies: 12
    • Views: 1,408
    8th February 2018, 04:21 Go to last post
  10. [SOLVED]Closed: How I/Os are realized inside FPGA

    Started by mjuneja, 3rd February 2018 17:22
    • Replies: 10
    • Views: 1,202
    7th February 2018, 17:28 Go to last post
  11. Closed: verilog-problem write text file

    Started by jalal.baba, 7th February 2018 10:59
    • Replies: 1
    • Views: 521
    7th February 2018, 13:25 Go to last post
  12. Closed: Conversion of octal to decimal

    Started by sugubai, 31st January 2018 18:44
    • Replies: 13
    • Views: 1,763
    6th February 2018, 00:00 Go to last post
  13. Closed: verilog-problem read decimal value in text file

    Started by jalal.baba, 5th February 2018 17:04
    • Replies: 3
    • Views: 884
    5th February 2018, 23:05 Go to last post
  14. Closed: Vivado error please help with library

    Started by abimann, 5th February 2018 15:56
    • Replies: 1
    • Views: 512
    5th February 2018, 17:08 Go to last post
  15. Closed: Clock generator in psoc by using verilog

    Started by jasi, 23rd January 2018 10:29
    • Replies: 6
    • Views: 1,069
    4th February 2018, 18:52 Go to last post
  16. Closed: Help in simulating ALU with register file

    Started by fadia, 4th February 2018 00:55
    • Replies: 0
    • Views: 501
    4th February 2018, 00:55 Go to last post
  17. Closed: is nested for loop supported in verilog

    Started by tayyab786, 3rd February 2018 19:36
    • Replies: 1
    • Views: 1,059
    3rd February 2018, 20:37 Go to last post
  18. Closed: Unconstrained FPGA ADC-Outputs

    Started by Hugo17, 2nd February 2018 10:40
    • Replies: 3
    • Views: 669
    2nd February 2018, 16:14 Go to last post
    • Replies: 0
    • Views: 471
    2nd February 2018, 08:28 Go to last post
  19. Closed: Altera Embedded Evaluation kit (NEEK), Cyclone III edition

    Started by Greedy_Altera, 31st January 2018 14:48
    • Replies: 3
    • Views: 628
    1st February 2018, 11:41 Go to last post
  20. Closed: Latch over flip flop

    Started by shweta.bphc, 31st January 2018 18:12
    • Replies: 4
    • Views: 572
    1st February 2018, 03:05 Go to last post
  21. Closed: Standard Path Delays vs. Critical Path Delays

    Started by msdarvishi, 1st February 2018 02:02
    • Replies: 1
    • Views: 362
    1st February 2018, 03:00 Go to last post
  22. Closed: Spartan 6 and flash memory data transferring

    Started by JAVADHABIBI, 28th January 2018 14:52
    • Replies: 9
    • Views: 747
    31st January 2018, 14:20 Go to last post
  23. Closed: process sensitivity list problem in FSM (VHDL)

    Started by EceWoman, 27th January 2018 21:44
    • Replies: 7
    • Views: 871
    31st January 2018, 13:27 Go to last post
  24. [SOLVED]Closed: Gated reset for register

    Started by mjuneja, 29th January 2018 07:44
    • Replies: 8
    • Views: 798
    31st January 2018, 13:17 Go to last post
  25. Closed: ISE Does not Recognize Defined Signal

    Started by RosesAreRed, 30th January 2018 21:22
    • Replies: 6
    • Views: 573
    31st January 2018, 12:05 Go to last post
  26. Closed: Problem with timing, Back annotation and FPGA chip

    Started by ibrahima, 31st January 2018 02:18
    • Replies: 2
    • Views: 542
    31st January 2018, 08:26 Go to last post
  27. Closed: Stucked at UART formal verification

    Started by promach, 29th January 2018 01:29
    • Replies: 8
    • Views: 715
    30th January 2018, 11:29 Go to last post
  28. Closed: Need help with implementing a FIR filter using vhdl

    Started by hamid123, 23rd January 2018 14:17
    • Replies: 7
    • Views: 854
    27th January 2018, 21:28 Go to last post