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Threads 301 to 330 of 22789

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: HPS-FPGA issues on Intel Cyclone V

    Started by Ironlord, 11th January 2019 13:10
    • Replies: 1
    • Views: 769
    24th January 2019, 11:57 Go to last post
  2. Closed: Using Verilog Tasks in VHDL Code

    Started by mertberkea, 23rd January 2019 08:40
    • Replies: 3
    • Views: 495
    23rd January 2019, 19:16 Go to last post
  3. Closed: Serial by Parallel Booth Multiplier

    Started by promach, 22nd January 2019 03:53
    • Replies: 8
    • Views: 941
    23rd January 2019, 12:03 Go to last post
  4. Closed: Mismatched pcie lanes ip core vs hardware.

    Started by wesleytaylor, 15th January 2019 10:59
    • Replies: 1
    • Views: 381
    23rd January 2019, 06:10 Go to last post
  5. Closed: Formal verification of mutiplier verilog code

    Started by promach, 17th January 2019 07:10
    • Replies: 7
    • Views: 1,089
    22nd January 2019, 06:56 Go to last post
  6. Closed: Unable to allocate all 2GB of DDR4_PL in ZCU106

    Started by msdarvishi, 21st January 2019 23:39
    • Replies: 0
    • Views: 403
    21st January 2019, 23:39 Go to last post
  7. [SOLVED]Closed: Simulation in questa

    Started by ranayehya, 16th January 2019 14:58
    • Replies: 1
    • Views: 502
    16th January 2019, 17:29 Go to last post
  8. Closed: What does CPU_RESET pin exactly do in ZCU106 MPSoC board?

    Started by msdarvishi, 15th January 2019 19:33
    • Replies: 1
    • Views: 468
    16th January 2019, 13:24 Go to last post
  9. Closed: Converting Verilog to VHDL

    Started by joniengr, 6th December 2018 11:45
    2 Pages
    1 2
    • Replies: 29
    • Views: 2,813
    15th January 2019, 16:48 Go to last post
  10. Closed: ISE Project navigator while implementation is turned off

    Started by frdm90, 3rd January 2019 12:23
    • Replies: 7
    • Views: 1,178
    15th January 2019, 09:24 Go to last post
  11. Closed: Spartan 6 - OSERDES2 to ODDR - Unroutable signals

    Started by pigtwo, 12th January 2019 17:22
    • Replies: 4
    • Views: 763
    13th January 2019, 23:28 Go to last post
  12. Closed: USB Softcore for FPGA

    Started by promach, 1st December 2018 05:29
    2 Pages
    1 2
    • Replies: 36
    • Views: 3,390
    7th January 2019, 17:48 Go to last post
  13. Closed: XC9536XL programing by DLC9G

    Started by frdm90, 7th January 2019 10:53
    • Replies: 1
    • Views: 478
    7th January 2019, 15:23 Go to last post
  14. Closed: Help to get Answer in VHDL code for use Floting point and RAM

    Started by Adnan86, 31st December 2018 14:22
    • Replies: 2
    • Views: 516
    4th January 2019, 14:36 Go to last post
    • Replies: 1
    • Views: 880
    4th January 2019, 12:07 Go to last post
  15. Closed: Best way to interface with 14-bit 20MSample/s ADC

    Started by Palpurul, 2nd January 2019 14:50
    • Replies: 13
    • Views: 1,070
    4th January 2019, 10:41 Go to last post
  16. Closed: HDL simulation help to understand the function of verilog file

    Started by joniengr, 2nd January 2019 10:33
    • Replies: 7
    • Views: 770
    4th January 2019, 09:42 Go to last post
  17. Closed: TKEEP and TSTRB in AXI Stream

    Started by joniengr, 30th December 2018 23:02
    • Replies: 5
    • Views: 2,443
    3rd January 2019, 01:35 Go to last post
  18. [SOLVED]Closed: Hierarchical block is unconnected

    Started by jasmine123, 30th December 2018 11:12
    • Replies: 3
    • Views: 474
    31st December 2018, 07:52 Go to last post
  19. Closed: Input port and input output port declaration in top module

    Started by sandy2811, 30th December 2018 13:09
    • Replies: 2
    • Views: 476
    30th December 2018, 16:40 Go to last post
  20. Closed: registered vs non registered?

    Started by player80, 25th December 2018 12:28
    • Replies: 1
    • Views: 456
    25th December 2018, 15:46 Go to last post
  21. Closed: Timing analysis guidance

    Started by dayana42200, 22nd December 2018 01:57
    • Replies: 4
    • Views: 783
    24th December 2018, 06:46 Go to last post
  22. Closed: SerDes - architecture and applications

    Started by FlyingDutch, 21st December 2018 15:53
    • Replies: 3
    • Views: 741
    21st December 2018, 17:29 Go to last post
  23. Closed: Correct design to work with MIPI and SPI

    Started by Ironlord, 18th December 2018 08:33
    • Replies: 13
    • Views: 2,535
    21st December 2018, 13:19 Go to last post
  24. [SOLVED]Closed: Techniques for logic cell estimation - FPGA

    Started by mjuneja, 21st December 2018 05:13
    • Replies: 1
    • Views: 308
    21st December 2018, 12:27 Go to last post
    • Replies: 1
    • Views: 440
    16th December 2018, 20:03 Go to last post
  25. Closed: PLS explain how to make BRAM

    Started by abimann, 2nd December 2018 07:00
    • Replies: 10
    • Views: 1,377
    15th December 2018, 21:41 Go to last post
  26. Closed: Input and output delay values for FPGA

    Started by Alauddin123, 15th December 2018 06:47
    • Replies: 1
    • Views: 415
    15th December 2018, 20:06 Go to last post
  27. Closed: clocking issues in capturing debug signals in ILA

    Started by Alauddin123, 15th November 2018 06:57
    • Replies: 3
    • Views: 767
    15th December 2018, 06:39 Go to last post
  28. [SOLVED]Closed: Verilog Interview Question

    Started by rahdirs, 6th December 2018 23:06
    • Replies: 5
    • Views: 1,023
    15th December 2018, 01:36 Go to last post