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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Verilog Interview Question

    Started by rahdirs, 6th December 2018 23:06
    • Replies: 5
    • Views: 960
    15th December 2018, 01:36 Go to last post
  2. Closed: Where is a high-frequency clock capable IO pin in ZCU106 board?

    Started by msdarvishi, 14th December 2018 21:52
    • Replies: 1
    • Views: 338
    14th December 2018, 22:09 Go to last post
    • Replies: 2
    • Views: 477
    14th December 2018, 12:35 Go to last post
  3. Closed: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    Started by msdarvishi, 19th November 2018 17:00
    • Replies: 4
    • Views: 1,333
    12th December 2018, 09:29 Go to last post
  4. Closed: Xilinx XPower Analyzer Confidence Level

    Started by dayana42200, 10th December 2018 02:38
    • Replies: 4
    • Views: 617
    12th December 2018, 00:09 Go to last post
  5. Closed: Fixed point complex numbers in sdSOC

    Started by Radhikamkr, 10th December 2018 13:34
    • Replies: 0
    • Views: 368
    10th December 2018, 13:34 Go to last post
  6. Closed: Design a 4-core processor on FPGA

    Started by adwnis123, 7th December 2018 15:11
    • Replies: 9
    • Views: 1,469
    8th December 2018, 18:02 Go to last post
  7. Closed: Why Quarus Prime is uninstalled after restart a Windows?

    Started by frdm90, 5th December 2018 16:40
    • Replies: 4
    • Views: 485
    6th December 2018, 17:01 Go to last post
  8. Closed: Generating SAIF file

    Started by dayana42200, 3rd December 2018 02:43
    • Replies: 7
    • Views: 924
    6th December 2018, 01:43 Go to last post
  9. Closed: 3-bit adder w 4 bit sum; connect to 2 "7 segment" displays

    Started by jinformations, 4th December 2018 08:10
    • Replies: 4
    • Views: 703
    4th December 2018, 18:03 Go to last post
  10. Closed: VHDL unconstrained array in VCS

    Started by shaiko, 4th December 2018 13:13
    • Replies: 2
    • Views: 492
    4th December 2018, 14:31 Go to last post
  11. Closed: Spartan-6 Servo Control

    Started by prakash_kadri, 28th November 2018 12:04
    • Replies: 6
    • Views: 919
    30th November 2018, 02:54 Go to last post
  12. Closed: Best Way to Implement Shared RAM

    Started by groover, 26th November 2018 21:46
    2 Pages
    1 2
    • Replies: 25
    • Views: 1,357
    29th November 2018, 23:17 Go to last post
  13. Closed: Propper clock generation for SPI protocol

    Started by Ironlord, 27th November 2018 13:05
    • Replies: 14
    • Views: 1,055
    29th November 2018, 13:24 Go to last post
  14. Closed: Using different time units in Verilog simulation

    Started by shaiko, 25th November 2018 00:09
    • Replies: 2
    • Views: 676
    26th November 2018, 16:52 Go to last post
  15. [SOLVED]Closed: Instantiating module with inout

    Started by ranayehya, 26th November 2018 08:03
    • Replies: 4
    • Views: 435
    26th November 2018, 15:23 Go to last post
  16. Closed: Definitions for a Memory in Verilog

    Started by groover, 25th November 2018 20:49
    • Replies: 0
    • Views: 350
    25th November 2018, 20:49 Go to last post
  17. Closed: How to show a full adder output on a 7 segment display

    Started by jinformations, 24th November 2018 23:37
    • Replies: 2
    • Views: 607
    25th November 2018, 20:40 Go to last post
  18. Closed: System Verilog - default type of a declared variable

    Started by shaiko, 24th November 2018 18:53
    • Replies: 7
    • Views: 1,071
    25th November 2018, 15:39 Go to last post
  19. Closed: Parameter location in a Verilog Module

    Started by shaiko, 24th November 2018 20:12
    • Replies: 1
    • Views: 377
    24th November 2018, 20:28 Go to last post
  20. Closed: Verilog & System Verilog - port sizing by inheritance

    Started by shaiko, 24th November 2018 13:43
    • Replies: 1
    • Views: 377
    24th November 2018, 15:48 Go to last post
  21. Closed: Implement I2C in VHDL

    Started by Ironlord, 16th October 2018 07:47
    3 Pages
    1 2 3
    • Replies: 55
    • Views: 4,260
    23rd November 2018, 13:02 Go to last post
    • Replies: 3
    • Views: 407
    22nd November 2018, 21:16 Go to last post
  22. Closed: reorder queue mechanism

    Started by promach, 18th September 2018 04:33
    • Replies: 10
    • Views: 1,235
    20th November 2018, 09:10 Go to last post
  23. Closed: FPGA ALM or LAB estimated size

    Started by PablodlR, 29th October 2018 13:14
    • Replies: 6
    • Views: 959
    20th November 2018, 07:26 Go to last post
  24. Closed: Verilog Synchronize with External Signal

    Started by groover, 18th November 2018 21:44
    • Replies: 4
    • Views: 606
    20th November 2018, 00:36 Go to last post
  25. Closed: Noob's question about sensitivity list and timing of signals

    Started by EceWoman, 17th November 2018 16:19
    • Replies: 4
    • Views: 529
    18th November 2018, 01:19 Go to last post
  26. Closed: ZYNQ - XADC example ZedBoard or ZYBO

    Started by joniengr, 15th November 2018 16:42
    • Replies: 1
    • Views: 535
    16th November 2018, 10:38 Go to last post
  27. Closed: Tracking 'X' in the gate lavel simulation

    Started by filip.amator, 10th November 2018 11:32
    • Replies: 5
    • Views: 913
    14th November 2018, 18:11 Go to last post
  28. Closed: Design of a PCIe card with USB and Ethernet

    Started by HasHx, 7th November 2018 19:29
    • Replies: 7
    • Views: 1,860
    14th November 2018, 05:59 Go to last post