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Threads 301 to 330 of 22465

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: declaring a constant value for all modules in verilog

    Started by dipin, 6th April 2018 06:12
    • Replies: 3
    • Views: 556
    6th April 2018, 07:39 Go to last post
  2. Closed: Usage of HP and HR IO banks and their selection

    Started by Alauddin123, 5th April 2018 06:54
    • Replies: 1
    • Views: 723
    5th April 2018, 07:29 Go to last post
  3. Closed: 12 Hour Clock using VHDL

    Started by triplel06, 3rd April 2018 01:12
    • Replies: 8
    • Views: 1,278
    4th April 2018, 16:59 Go to last post
  4. Closed: [MOVED] Need Verilog code for Ethernet protocol

    Started by mhafdhia, 4th April 2018 01:30
    • Replies: 2
    • Views: 923
    4th April 2018, 08:52 Go to last post
  5. Closed: Interfacing a buzzer with CPLD

    Started by garvind25, 25th March 2018 16:56
    • Replies: 9
    • Views: 1,148
    3rd April 2018, 18:45 Go to last post
  6. Closed: Concurrent constructs in Verilog?

    Started by samg, 2nd April 2018 10:56
    • Replies: 2
    • Views: 530
    3rd April 2018, 10:18 Go to last post
  7. Closed: copying a file from fpga to pc without modem

    Started by dipin, 30th March 2018 15:45
    • Replies: 2
    • Views: 612
    1st April 2018, 22:43 Go to last post
  8. Closed: Converting an array of std_logic to string

    Started by shaiko, 30th March 2018 11:45
    • Replies: 9
    • Views: 1,367
    30th March 2018, 23:16 Go to last post
  9. Closed: AXI4 stream bus and arbitration

    Started by filip.amator, 30th March 2018 22:47
    • Replies: 0
    • Views: 635
    30th March 2018, 22:47 Go to last post
  10. Closed: Queries on JTAG interface for a CPLD based system

    Started by garvind25, 10th March 2018 18:31
    • Replies: 7
    • Views: 993
    29th March 2018, 11:36 Go to last post
  11. Closed: Want to convert 32 bit data into 4 group of 8 bit data for UART

    Started by Krishna_k, 22nd March 2018 07:14
    • Replies: 10
    • Views: 1,476
    28th March 2018, 14:02 Go to last post
  12. Closed: Overflow pointer cell

    Started by nsgil85, 27th March 2018 17:09
    • Replies: 3
    • Views: 568
    28th March 2018, 11:17 Go to last post
  13. [SOLVED]Closed: Modelsim do not provide output for module with delay more than 1ns

    Started by Anklon, 26th March 2018 07:32
    • Replies: 3
    • Views: 550
    26th March 2018, 15:58 Go to last post
  14. Closed: ADC on DEO nano board

    Started by Chinmaye, 22nd March 2018 17:54
    • Replies: 4
    • Views: 798
    25th March 2018, 09:02 Go to last post
  15. Closed: Question about RIFFA interface between FPGA and linux driver

    Started by promach, 24th March 2018 12:39
    • Replies: 1
    • Views: 541
    24th March 2018, 23:11 Go to last post
  16. Closed: Write leveling for single dram DDR3 device

    Started by Alosevskoy, 24th March 2018 12:36
    • Replies: 0
    • Views: 382
    24th March 2018, 12:36 Go to last post
    • Replies: 2
    • Views: 696
    22nd March 2018, 01:47 Go to last post
  17. Closed: How to "ARCTAN" Function in VHDL

    Started by Krishna_k, 13th March 2018 10:33
    • Replies: 7
    • Views: 1,617
    21st March 2018, 19:32 Go to last post
  18. Closed: What is the best method for finding adjacency?

    Started by jalal.baba, 20th March 2018 21:24
    • Replies: 0
    • Views: 489
    20th March 2018, 21:24 Go to last post
    • Replies: 4
    • Views: 839
    20th March 2018, 05:50 Go to last post
  19. Closed: architecture of pipelined for searching in memory

    Started by jalal.baba, 18th March 2018 20:50
    • Replies: 5
    • Views: 852
    20th March 2018, 05:44 Go to last post
  20. Closed: [moved] ADC in DEO_NANO board

    Started by Chinmaye, 19th March 2018 18:41
    • Replies: 2
    • Views: 629
    19th March 2018, 20:50 Go to last post
  21. Closed: AXI4 to AXI Stream conversion for Ultrascale PCIe EP support

    Started by sreevenkjan, 13th March 2018 11:04
    • Replies: 5
    • Views: 1,131
    19th March 2018, 12:28 Go to last post
  22. Closed: Work window is Altera Quartus II software

    Started by vedika, 15th March 2018 05:19
    • Replies: 2
    • Views: 617
    19th March 2018, 10:21 Go to last post
    • Replies: 3
    • Views: 824
    19th March 2018, 10:20 Go to last post
  23. Verilog testbench help!! (bit urgent)

    Started by sonika111, 8th March 2018 14:43
    4 Pages
    1 2 3 ... 4
    • Replies: 62
    • Views: 3,938
    16th March 2018, 16:56 Go to last post
  24. [SOLVED]Closed: PCIE PIO example design

    Started by sreevenkjan, 13th March 2018 10:37
    • Replies: 7
    • Views: 1,216
    16th March 2018, 15:02 Go to last post
  25. Closed: .dev library for JED2AHDL

    Started by dk_spb, 16th March 2018 11:08
    • Replies: 0
    • Views: 466
    16th March 2018, 11:53 Go to last post
    • Replies: 8
    • Views: 1,623
    16th March 2018, 05:55 Go to last post