1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    126,998
Page 11 of 761 FirstFirst ... 9 10 11 12 13 21 61 111 511 ... LastLast
Threads 301 to 330 of 22808

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: Help to translate verilog code lines to vhdl

    Started by Cesar0182, 18th February 2019 15:56
    • Replies: 9
    • Views: 673
    19th February 2019, 16:51 Go to last post
  2. Closed: FPGA neural network training

    Started by adwnis123, 28th January 2019 16:16
    • Replies: 14
    • Views: 2,043
    18th February 2019, 22:04 Go to last post
  3. Closed: How to begin development on SOC (xilinx)

    Started by tajiknomi, 18th February 2019 10:39
    • Replies: 3
    • Views: 463
    18th February 2019, 17:00 Go to last post
  4. [SOLVED]Closed: Reed solomon encoder in vhdl

    Started by Saurabhmale, 17th February 2019 14:15
    • Replies: 5
    • Views: 486
    18th February 2019, 16:53 Go to last post
  5. Closed: Kintex & FPGA signal integrity for SERDES Signal

    Started by chamarnadh, 16th February 2019 09:14
    • Replies: 1
    • Views: 552
    18th February 2019, 16:46 Go to last post
  6. Closed: Speed of RC Servo VHDL code

    Started by prakash_kadri, 18th February 2019 06:12
    • Replies: 3
    • Views: 468
    18th February 2019, 12:42 Go to last post
  7. Closed: Verilog shifter synthesis in Design Compiler

    Started by oAwad, 17th February 2019 00:39
    • Replies: 2
    • Views: 466
    17th February 2019, 01:54 Go to last post
  8. Closed: Unknown formal identifier in VHDL

    Started by sarmadmahmood969, 16th February 2019 01:49
    • Replies: 5
    • Views: 868
    16th February 2019, 15:48 Go to last post
    • Replies: 2
    • Views: 605
    14th February 2019, 09:21 Go to last post
  9. Closed: mutlplty verilog code does not multiply

    Started by promach, 9th February 2019 01:40
    • Replies: 12
    • Views: 1,594
    13th February 2019, 07:58 Go to last post
  10. [SOLVED]Closed: VHDL Counter FPGA Spartan-6

    Started by prakash_kadri, 4th February 2019 20:10
    • Replies: 8
    • Views: 1,425
    11th February 2019, 09:02 Go to last post
  11. Closed: USB multiplexer via FPGA

    Started by orso135, 10th February 2019 19:01
    • Replies: 1
    • Views: 464
    10th February 2019, 21:59 Go to last post
  12. Closed: Verification for VHDL keeping FPGA in mind

    Started by dpaul, 4th February 2019 12:33
    • Replies: 3
    • Views: 741
    6th February 2019, 10:32 Go to last post
  13. Closed: Order of Execution of taking "NOT" and multiplication

    Started by akh_power, 4th February 2019 01:19
    • Replies: 4
    • Views: 564
    4th February 2019, 10:12 Go to last post
  14. Closed: Couldn't find design package

    Started by ranayehya, 26th January 2019 13:48
    • Replies: 1
    • Views: 641
    3rd February 2019, 07:09 Go to last post
  15. [SOLVED]Closed: VHDL : Sine Wave Lookup Table Not Working

    Started by akh_power, 28th January 2019 13:25
    • Replies: 10
    • Views: 1,258
    31st January 2019, 17:01 Go to last post
  16. Closed: 2M multiplication method

    Started by promach, 29th January 2019 04:59
    • Replies: 2
    • Views: 557
    31st January 2019, 04:35 Go to last post
  17. Closed: Wallace Tree Multiplier Questions

    Started by promach, 25th January 2019 04:39
    • Replies: 1
    • Views: 711
    25th January 2019, 06:43 Go to last post
  18. Closed: LPC data transfer Method

    Started by beginner_EDA, 22nd January 2019 15:58
    • Replies: 12
    • Views: 1,203
    24th January 2019, 17:12 Go to last post
  19. [SOLVED]Closed: HPS-FPGA issues on Intel Cyclone V

    Started by Ironlord, 11th January 2019 13:10
    • Replies: 1
    • Views: 804
    24th January 2019, 11:57 Go to last post
  20. Closed: Using Verilog Tasks in VHDL Code

    Started by mertberkea, 23rd January 2019 08:40
    • Replies: 3
    • Views: 526
    23rd January 2019, 19:16 Go to last post
  21. Closed: Serial by Parallel Booth Multiplier

    Started by promach, 22nd January 2019 03:53
    • Replies: 8
    • Views: 1,007
    23rd January 2019, 12:03 Go to last post
  22. Closed: Mismatched pcie lanes ip core vs hardware.

    Started by wesleytaylor, 15th January 2019 10:59
    • Replies: 1
    • Views: 409
    23rd January 2019, 06:10 Go to last post
  23. Closed: Formal verification of mutiplier verilog code

    Started by promach, 17th January 2019 07:10
    • Replies: 7
    • Views: 1,153
    22nd January 2019, 06:56 Go to last post
  24. Closed: Unable to allocate all 2GB of DDR4_PL in ZCU106

    Started by msdarvishi, 21st January 2019 23:39
    • Replies: 0
    • Views: 441
    21st January 2019, 23:39 Go to last post
  25. [SOLVED]Closed: Simulation in questa

    Started by ranayehya, 16th January 2019 14:58
    • Replies: 1
    • Views: 530
    16th January 2019, 17:29 Go to last post
  26. Closed: What does CPU_RESET pin exactly do in ZCU106 MPSoC board?

    Started by msdarvishi, 15th January 2019 19:33
    • Replies: 1
    • Views: 516
    16th January 2019, 13:24 Go to last post
  27. Closed: Converting Verilog to VHDL

    Started by joniengr, 6th December 2018 11:45
    2 Pages
    1 2
    • Replies: 29
    • Views: 2,924
    15th January 2019, 16:48 Go to last post
  28. Closed: ISE Project navigator while implementation is turned off

    Started by frdm90, 3rd January 2019 12:23
    • Replies: 7
    • Views: 1,226
    15th January 2019, 09:24 Go to last post
  29. Closed: Spartan 6 - OSERDES2 to ODDR - Unroutable signals

    Started by pigtwo, 12th January 2019 17:22
    • Replies: 4
    • Views: 826
    13th January 2019, 23:28 Go to last post