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Threads 301 to 330 of 22274

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Multiple users of a DDR interface

    Started by shaiko, 29th November 2017 21:08
    • Replies: 14
    • Views: 1,809
    2nd December 2017, 09:31 Go to last post
  2. Closed: Coding help in Verilog

    Started by josephine1234, 1st December 2017 06:04
    • Replies: 4
    • Views: 672
    1st December 2017, 13:18 Go to last post
  3. Closed: Implementation of output wrt clock in verilog

    Started by kapaa, 30th November 2017 08:24
    • Replies: 5
    • Views: 852
    1st December 2017, 07:01 Go to last post
  4. Closed: Interfacing a VGA port with a PLD

    Started by garvind25, 25th October 2017 07:16
    • Replies: 10
    • Views: 1,603
    1st December 2017, 06:10 Go to last post
  5. Closed: modelsim error during RTL simulation

    Started by hareeshP, 30th November 2017 15:07
    • Replies: 8
    • Views: 1,086
    30th November 2017, 19:33 Go to last post
  6. Closed: Data not appearing in waveform window

    Started by athuluri_mounika, 28th November 2017 13:08
    • Replies: 5
    • Views: 768
    30th November 2017, 19:22 Go to last post
  7. Closed: FPGA Vertex -6 ML605

    Started by tayyab786, 29th November 2017 03:04
    • Replies: 4
    • Views: 904
    30th November 2017, 17:06 Go to last post
  8. Closed: KCU105 configuration

    Started by wesleytaylor, 30th November 2017 12:14
    • Replies: 0
    • Views: 475
    30th November 2017, 12:14 Go to last post
  9. Closed: Programming an fpga board

    Started by moonshine8995, 29th November 2017 14:17
    • Replies: 2
    • Views: 574
    30th November 2017, 11:39 Go to last post
  10. Closed: using chipscope to check signals in a design

    Started by moonshine8995, 29th November 2017 09:00
    • Replies: 2
    • Views: 563
    29th November 2017, 19:47 Go to last post
  11. Closed: Microsemi FPGA, remove clock buffer

    Started by cocopa, 29th November 2017 12:12
    • Replies: 1
    • Views: 576
    29th November 2017, 19:41 Go to last post
  12. Closed: VHDL or Verilog What is best for nested generate statement

    Started by Zerox100, 29th November 2017 14:34
    • Replies: 1
    • Views: 636
    29th November 2017, 17:49 Go to last post
  13. Closed: coding help needed in verilog

    Started by josephine1234, 29th November 2017 05:53
    • Replies: 3
    • Views: 586
    29th November 2017, 08:29 Go to last post
  14. Closed: BRAM vs LUTRAM resources

    Started by rafimiet, 27th November 2017 07:16
    • Replies: 1
    • Views: 1,088
    27th November 2017, 07:45 Go to last post
  15. Closed: DAQ system with FPGA and 1KHz sampling rate

    Started by Vlad., 25th November 2017 17:16
    • Replies: 14
    • Views: 1,889
    26th November 2017, 13:15 Go to last post
  16. [SOLVED]Closed: [Netlist 29-101] Netlist 'b0_decision' is not ideal for floorplanning

    Started by rafimiet, 25th November 2017 06:04
    • Replies: 4
    • Views: 1,444
    25th November 2017, 20:48 Go to last post
  17. Closed: Mapping block RAMs to specific address space

    Started by sajjad.hussain, 23rd November 2017 00:08
    • Replies: 4
    • Views: 1,507
    24th November 2017, 16:49 Go to last post
  18. Closed: Asynchronous fifo cdc question

    Started by promach, 21st November 2017 06:51
    • Replies: 1
    • Views: 1,034
    24th November 2017, 02:00 Go to last post
  19. Closed: Can victim caches be used adjacent to the L2 cache or LLC?

    Started by roshan12, 23rd November 2017 05:26
    • Replies: 0
    • Views: 919
    23rd November 2017, 05:26 Go to last post
  20. Closed: Error in verilog code

    Started by josephine1234, 21st November 2017 07:25
    • Replies: 5
    • Views: 1,095
    22nd November 2017, 22:22 Go to last post
    • Replies: 1
    • Views: 534
    22nd November 2017, 16:34 Go to last post
  21. [SOLVED]Closed: IOBUF primative doesn't behave the way i want

    Started by wesleytaylor, 21st November 2017 16:25
    • Replies: 3
    • Views: 1,187
    22nd November 2017, 14:31 Go to last post
  22. Closed: MachXO2 DDR and PCLK routing issue

    Started by juanMco, 20th November 2017 17:32
    • Replies: 4
    • Views: 1,262
    21st November 2017, 17:48 Go to last post
  23. Closed: MAX10 PLL External Clock Output

    Started by Yorki, 9th November 2017 14:35
    • Replies: 7
    • Views: 1,407
    21st November 2017, 09:55 Go to last post
  24. Closed: FPGA interface with 100Mbps Ethernet

    Started by fouwad, 17th November 2017 07:10
    • Replies: 3
    • Views: 1,541
    20th November 2017, 14:26 Go to last post
  25. Closed: Help tracking down very long synthesis time

    Started by whaleeee, 13th November 2017 19:51
    • Replies: 13
    • Views: 1,999
    20th November 2017, 08:48 Go to last post
  26. [SOLVED]Closed: concurrent vhdl code generating latches

    Started by rafimiet, 19th November 2017 10:10
    • Replies: 4
    • Views: 1,125
    19th November 2017, 11:43 Go to last post
  27. Closed: [moved] ZedBoard HDMI input without FMC card

    Started by DilshanSampath, 17th November 2017 18:13
    • Replies: 2
    • Views: 959
    18th November 2017, 20:02 Go to last post
  28. Closed: Moving window integrator

    Started by Rani1234, 17th November 2017 12:43
    • Replies: 4
    • Views: 1,054
    17th November 2017, 18:38 Go to last post
  29. [SOLVED]Closed: Initializing Xilinx BRAM with image pixels

    Started by Taki_comp, 6th November 2017 20:52
    • Replies: 10
    • Views: 1,774
    17th November 2017, 14:38 Go to last post