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Threads 301 to 330 of 22301

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: [Moved]: Clock from Aurora protocol for asynchronous FIFO

    Started by ThanhTai, 15th December 2017 18:03
    • Replies: 1
    • Views: 563
    18th December 2017, 02:40 Go to last post
  2. Closed: FPGA Based Car Game (Christmas Themed)

    Started by bwarlord01, 16th December 2017 15:26
    • Replies: 1
    • Views: 582
    16th December 2017, 19:46 Go to last post
  3. Closed: Vivado - math.real support

    Started by shaiko, 14th December 2017 12:37
    • Replies: 7
    • Views: 1,142
    15th December 2017, 13:12 Go to last post
  4. Closed: SSD performance gain

    Started by shaiko, 12th December 2017 17:27
    • Replies: 7
    • Views: 977
    14th December 2017, 09:45 Go to last post
  5. Closed: OpenCL GPU vs FPGA implementation

    Started by shaiko, 13th December 2017 01:23
    • Replies: 1
    • Views: 649
    13th December 2017, 16:35 Go to last post
    • Replies: 0
    • Views: 458
    13th December 2017, 07:53 Go to last post
  6. Closed: Generate desired random number in range in verilog

    Started by tayyab786, 27th November 2017 20:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 3,193
    11th December 2017, 23:48 Go to last post
  7. Closed: FPGA USB Data software

    Started by expertengr, 9th December 2017 12:10
    • Replies: 5
    • Views: 924
    11th December 2017, 19:52 Go to last post
  8. [SOLVED]Closed: Round robin arbiter with ring counter.

    Started by ppko1233, 10th December 2017 14:26
    • Replies: 1
    • Views: 701
    11th December 2017, 16:48 Go to last post
  9. Closed: Improve UART resource usage

    Started by promach, 10th December 2017 12:41
    • Replies: 1
    • Views: 629
    11th December 2017, 02:09 Go to last post
  10. [SOLVED]Closed: logic : give value in which require decimal number represent

    Started by tayyab786, 10th December 2017 14:05
    • Replies: 5
    • Views: 745
    10th December 2017, 22:10 Go to last post
  11. Closed: Circuit protection with VHDL code

    Started by manush30, 6th December 2017 08:40
    • Replies: 9
    • Views: 1,131
    10th December 2017, 10:54 Go to last post
  12. Closed: ADS (advanced Design System) Xilinx FPGA model kit

    Started by Enrocinu, 10th December 2017 00:00
    • Replies: 0
    • Views: 662
    10th December 2017, 00:00 Go to last post
    • Replies: 2
    • Views: 679
    9th December 2017, 20:11 Go to last post
    • Replies: 4
    • Views: 1,076
    9th December 2017, 16:34 Go to last post
  13. Closed: choosing high speed data storage element

    Started by amin5659, 7th December 2017 16:42
    • Replies: 10
    • Views: 1,235
    9th December 2017, 10:39 Go to last post
  14. [SOLVED]Closed: How to load program to A54SX16A-PQG208M FPGA?

    Started by Mithun_K_Das, 5th December 2017 12:17
    • Replies: 13
    • Views: 1,667
    9th December 2017, 05:34 Go to last post
  15. Closed: Xpath error: unbalanced parantheses found in Expression

    Started by Sunayana Chakradhar, 8th December 2017 10:54
    • Replies: 4
    • Views: 758
    8th December 2017, 22:19 Go to last post
  16. Closed: How to run two module in series using verilog

    Started by kapaa, 7th December 2017 03:21
    • Replies: 6
    • Views: 900
    7th December 2017, 22:44 Go to last post
  17. Closed: FPGA-Based Christmas project

    Started by bwarlord01, 6th December 2017 19:29
    • Replies: 3
    • Views: 748
    7th December 2017, 02:46 Go to last post
  18. Closed: What is Most Economic FPGA?

    Started by Zerox100, 5th December 2017 16:04
    • Replies: 2
    • Views: 631
    6th December 2017, 12:59 Go to last post
  19. Closed: What is difference between row and page in SDRAM?

    Started by matrixofdynamism, 6th December 2017 12:18
    • Replies: 0
    • Views: 446
    6th December 2017, 12:18 Go to last post
  20. Closed: Vendor specific macros for Igloo2

    Started by filip.amator, 5th December 2017 23:15
    • Replies: 2
    • Views: 926
    6th December 2017, 11:38 Go to last post
  21. Closed: ppg database regarding

    Started by josephine1234, 5th December 2017 12:00
    • Replies: 1
    • Views: 479
    5th December 2017, 12:13 Go to last post
  22. Closed: FPGA Ethernet interface

    Started by Vlad., 3rd December 2017 19:11
    • Replies: 3
    • Views: 1,461
    4th December 2017, 09:51 Go to last post
  23. Closed: Regarding Verilog codes

    Started by josephine1234, 1st December 2017 06:06
    • Replies: 5
    • Views: 1,143
    2nd December 2017, 13:07 Go to last post
  24. Closed: SPI communication (ALTERA board)

    Started by MiLaNa1995, 30th November 2017 14:19
    • Replies: 1
    • Views: 698
    2nd December 2017, 09:36 Go to last post
  25. Closed: Multiple users of a DDR interface

    Started by shaiko, 29th November 2017 21:08
    • Replies: 14
    • Views: 1,840
    2nd December 2017, 09:31 Go to last post
  26. Closed: Coding help in Verilog

    Started by josephine1234, 1st December 2017 06:04
    • Replies: 4
    • Views: 686
    1st December 2017, 13:18 Go to last post
  27. Closed: Implementation of output wrt clock in verilog

    Started by kapaa, 30th November 2017 08:24
    • Replies: 5
    • Views: 870
    1st December 2017, 07:01 Go to last post