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Threads 3001 to 3030 of 22239

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: floating point adder

    Started by shan14, 5th December 2014 06:08
    • Replies: 0
    • Views: 549
    5th December 2014, 06:08 Go to last post
  2. Closed: Button increment counter (2-bit) verilog

    Started by Spectre90, 3rd December 2014 08:14
    • Replies: 9
    • Views: 6,127
    5th December 2014, 04:54 Go to last post
  3. [SOLVED]Closed: SATA controller program execution

    Started by Sunayana Chakradhar, 27th November 2014 14:36
    2 Pages
    1 2
    • Replies: 34
    • Views: 2,405
    4th December 2014, 19:28 Go to last post
    • Replies: 0
    • Views: 1,012
    4th December 2014, 18:29 Go to last post
  4. Closed: ADC interface with FPGA

    Started by Sweta25, 4th December 2014 03:09
    • Replies: 7
    • Views: 1,866
    4th December 2014, 17:34 Go to last post
  5. [SOLVED]Closed: Assign statements dependency on clock

    Started by anusha vasanta, 3rd December 2014 06:21
    • Replies: 12
    • Views: 1,325
    4th December 2014, 00:09 Go to last post
  6. Closed: 4x4 keypad microcontroller

    Started by noobokti, 1st December 2014 02:06
    • Replies: 2
    • Views: 1,207
    3rd December 2014, 23:08 Go to last post
    • Replies: 2
    • Views: 1,609
    3rd December 2014, 17:10 Go to last post
    • Replies: 1
    • Views: 715
    3rd December 2014, 15:54 Go to last post
  7. [SOLVED]Closed: Gasp Controller Asynchronous Pipeline went wrong

    Started by MZulkarnain Jaranee, 27th November 2014 07:45
    • Replies: 8
    • Views: 1,105
    3rd December 2014, 14:55 Go to last post
  8. Closed: main coding difference b/w Big-endian and Little-endian

    Started by anusha vasanta, 3rd December 2014 05:57
    • Replies: 2
    • Views: 837
    3rd December 2014, 14:29 Go to last post
  9. Closed: edge detection using system generator

    Started by shan14, 28th November 2014 10:47
    • Replies: 13
    • Views: 1,752
    3rd December 2014, 12:20 Go to last post
  10. Closed: Clock Validity checking

    Started by completelyuseless, 3rd December 2014 08:18
    • Replies: 0
    • Views: 479
    3rd December 2014, 08:18 Go to last post
  11. Closed: To buy FPGA development board

    Started by mehanathan, 2nd December 2014 10:09
    • Replies: 3
    • Views: 743
    2nd December 2014, 23:07 Go to last post
  12. [SOLVED]Closed: how to increment a counter for 5 cycles.

    Started by prashanthi999, 25th November 2014 16:29
    • Replies: 7
    • Views: 1,055
    2nd December 2014, 21:57 Go to last post
  13. Closed: unbound componet vhdl error

    Started by abu9022, 2nd December 2014 19:08
    • Replies: 5
    • Views: 2,369
    2nd December 2014, 19:37 Go to last post
  14. Closed: xilinx FIR compiler IP core

    Started by vivek keviv, 2nd December 2014 10:24
    • Replies: 4
    • Views: 1,449
    2nd December 2014, 19:09 Go to last post
  15. Closed: HDLCompilers Verilog Error-Urgent

    Started by uniquadrion, 2nd December 2014 15:03
    • Replies: 4
    • Views: 563
    2nd December 2014, 18:41 Go to last post
  16. Closed: Bidirectional memory to non verilog

    Started by forast, 2nd December 2014 14:04
    • Replies: 4
    • Views: 639
    2nd December 2014, 17:25 Go to last post
  17. Closed: [Moved] Procedure for Xilinx System Generator

    Started by kishornakul, 2nd December 2014 07:41
    • Replies: 0
    • Views: 507
    2nd December 2014, 07:41 Go to last post
  18. Closed: Altera PLL - modelsim waveform

    Started by shaiko, 1st December 2014 12:24
    • Replies: 13
    • Views: 2,426
    1st December 2014, 23:09 Go to last post
  19. Closed: Implementation of Counter in Verilog

    Started by Spectre90, 30th November 2014 22:52
    • Replies: 3
    • Views: 1,227
    1st December 2014, 20:05 Go to last post
  20. Closed: need help with a part of my project

    Started by Spectre90, 1st December 2014 03:01
    • Replies: 3
    • Views: 610
    1st December 2014, 19:45 Go to last post
  21. Closed: ALU that multiplies using asterix-Verilog

    Started by uniquadrion, 1st December 2014 01:50
    • Replies: 3
    • Views: 826
    1st December 2014, 19:40 Go to last post
  22. Closed: How to use D Latch in RTL

    Started by dhanya22, 27th November 2014 14:29
    • Replies: 6
    • Views: 1,029
    1st December 2014, 19:16 Go to last post
  23. Closed: How to design a simplified LUT

    Started by ruwan2, 1st December 2014 03:17
    • Replies: 2
    • Views: 741
    1st December 2014, 18:20 Go to last post
  24. [SOLVED]Closed: fifo implementation using a counter

    Started by sandy3129, 16th November 2014 13:32
    2 Pages
    1 2
    • Replies: 38
    • Views: 3,487
    1st December 2014, 18:05 Go to last post
  25. [SOLVED]Closed: system verilog input randamization problem

    Started by dipin, 26th November 2014 12:36
    • Replies: 9
    • Views: 1,521
    1st December 2014, 17:25 Go to last post
  26. Closed: Verilog ALU that multiplies using asterix

    Started by uniquadrion, 1st December 2014 01:16
    • Replies: 0
    • Views: 614
    1st December 2014, 01:16 Go to last post