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Threads 3001 to 3030 of 22487

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Xilinx Coregen initialization of ROM

    Started by Tapojyoti Mandal, 19th February 2015 13:43
    • Replies: 5
    • Views: 1,733
    24th February 2015, 17:01 Go to last post
  2. Closed: full subtractor versus two's complement full adder for subtraction

    Started by ssubha, 24th February 2015 10:46
    • Replies: 2
    • Views: 976
    24th February 2015, 13:15 Go to last post
  3. Closed: Can i use EPCS16 as an external flash memory??

    Started by H.Hosny, 23rd February 2015 16:06
    • Replies: 2
    • Views: 619
    24th February 2015, 11:11 Go to last post
  4. Closed: fixed point representation

    Started by lokesh@88, 24th February 2015 06:44
    • Replies: 1
    • Views: 509
    24th February 2015, 08:17 Go to last post
  5. Closed: fixed point to std_logic_vector conversion in vhdl

    Started by symlet, 11th March 2013 09:05
    • Replies: 18
    • Views: 4,419
    24th February 2015, 07:25 Go to last post
  6. Closed: Why setup time is needed?????????

    Started by nitin_ndg, 3rd November 2007 08:08
    • Replies: 13
    • Views: 3,974
    24th February 2015, 05:24 Go to last post
  7. Closed: Microwire sampling and propagation timings

    Started by shaiko, 23rd February 2015 23:00
    • Replies: 1
    • Views: 653
    24th February 2015, 01:11 Go to last post
  8. Closed: Arithematic operations error (ModelSim - VHDL)

    Started by Mahati, 22nd February 2015 14:49
    • Replies: 8
    • Views: 761
    23rd February 2015, 17:45 Go to last post
  9. Closed: Why are ADC's output in 2'complement

    Started by sid_27, 23rd February 2015 15:16
    • Replies: 2
    • Views: 1,270
    23rd February 2015, 17:30 Go to last post
  10. Closed: dma controller using vhdl

    Started by Payal Singh, 23rd February 2015 16:34
    • Replies: 1
    • Views: 1,123
    23rd February 2015, 17:07 Go to last post
  11. Closed: creating new vhdl files with Lattice icecube2

    Started by JoseL, 20th February 2015 10:54
    • Replies: 4
    • Views: 1,451
    23rd February 2015, 17:00 Go to last post
  12. Closed: fixed point representation

    Started by lokesh@88, 23rd February 2015 12:34
    • Replies: 1
    • Views: 551
    23rd February 2015, 12:44 Go to last post
  13. Closed: how much is transfer rate for a ddr3 sdram using MIG Tool?

    Started by Port Map, 22nd February 2015 15:52
    • Replies: 3
    • Views: 671
    23rd February 2015, 09:30 Go to last post
  14. Closed: XILINX bus problem in schematic

    Started by Jiadong Yao, 21st February 2015 21:40
    • Replies: 2
    • Views: 1,011
    22nd February 2015, 10:14 Go to last post
  15. Closed: Reading and sending multiple bytes through UART in VHDL

    Started by Feco, 21st February 2015 15:28
    • Replies: 2
    • Views: 2,724
    21st February 2015, 17:06 Go to last post
  16. Closed: cordic corde with error how can i solve it

    Started by mr54852, 21st February 2015 12:10
    • Replies: 1
    • Views: 473
    21st February 2015, 12:22 Go to last post
  17. Closed: which fpga language is widely used

    Started by ep.hobbyiest, 21st February 2015 05:12
    • Replies: 2
    • Views: 801
    21st February 2015, 08:22 Go to last post
  18. Closed: Circular FIFO in VHDL

    Started by Binome, 10th February 2015 09:50
    2 Pages
    1 2
    • Replies: 32
    • Views: 7,038
    21st February 2015, 07:18 Go to last post
  19. Closed: Verilog code Divide by 2.5

    Started by pmoonlite, 20th February 2015 08:56
    • Replies: 13
    • Views: 2,029
    21st February 2015, 01:59 Go to last post
  20. Closed: About testbench content

    Started by Praseetha, 20th February 2015 06:02
    • Replies: 1
    • Views: 525
    20th February 2015, 08:56 Go to last post
    • Replies: 1
    • Views: 1,011
    19th February 2015, 18:41 Go to last post
  21. Closed: Matrix Multiplication in Vhdl

    Started by Eddy786, 22nd January 2015 09:14
    • Replies: 14
    • Views: 3,134
    19th February 2015, 16:26 Go to last post
  22. Closed: FPGA ethernet beginner

    Started by shawnmk123, 19th February 2015 07:34
    • Replies: 4
    • Views: 794
    19th February 2015, 11:10 Go to last post
  23. Closed: Sending data from PC to FPGA via Ethernet

    Started by jamesmatt, 13th February 2015 12:29
    • Replies: 2
    • Views: 867
    18th February 2015, 23:45 Go to last post
  24. [SOLVED]Closed: Generating AXI4Lite BFM using Xilinx Coregen

    Started by dpaul, 17th February 2015 16:42
    • Replies: 7
    • Views: 3,144
    18th February 2015, 18:25 Go to last post
  25. Closed: H.264 verilog or VHDL code

    Started by priyahain, 18th February 2015 06:28
    • Replies: 3
    • Views: 1,426
    18th February 2015, 17:23 Go to last post
  26. Closed: simpliest seven segment display

    Started by ecegigahertz, 16th February 2015 15:23
    • Replies: 5
    • Views: 654
    18th February 2015, 09:10 Go to last post
  27. Closed: fpga floating point problem!!!

    Started by Indrajit Ghosh, 18th February 2015 00:10
    • Replies: 1
    • Views: 686
    18th February 2015, 00:12 Go to last post
  28. Closed: Writing Bitstream into file: VHDL/Verilog

    Started by beginner_EDA, 17th February 2015 17:23
    • Replies: 6
    • Views: 1,523
    17th February 2015, 22:11 Go to last post
  29. Closed: Text output for FPGA

    Started by rekhavadakkeparambil, 14th February 2015 11:27
    • Replies: 5
    • Views: 656
    17th February 2015, 18:06 Go to last post