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Threads 3001 to 3030 of 22808

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: better ways to clock divisions

    Started by bharath9, 17th December 2014 06:03
    • Replies: 8
    • Views: 1,369
    23rd May 2015, 16:42 Go to last post
  2. Closed: project :Gray Counter

    Started by bianca_p, 22nd May 2015 17:23
    • Replies: 9
    • Views: 1,931
    22nd May 2015, 22:02 Go to last post
  3. Closed: Difference between signal and variable

    Started by Binome, 8th July 2014 07:02
    • Replies: 10
    • Views: 2,028
    22nd May 2015, 10:04 Go to last post
  4. Closed: parse error unexpected variable

    Started by p11, 22nd May 2015 07:41
    • Replies: 3
    • Views: 895
    22nd May 2015, 08:32 Go to last post
    • Replies: 7
    • Views: 838
    21st May 2015, 17:43 Go to last post
  5. Closed: VHDL code to interface FPGA & MAX3223

    Started by diganth, 21st May 2015 07:28
    • Replies: 1
    • Views: 620
    21st May 2015, 08:16 Go to last post
  6. Closed: Help fixing problems in the vhdl Sudoku code

    Started by Ms.Friday, 20th May 2015 14:28
    • Replies: 7
    • Views: 973
    20th May 2015, 21:17 Go to last post
    • Replies: 3
    • Views: 1,473
    20th May 2015, 13:35 Go to last post
  7. Closed: How do compilers interpret gates in a structural HDL adder?

    Started by p11, 19th May 2015 17:51
    • Replies: 1
    • Views: 730
    19th May 2015, 19:34 Go to last post
  8. Closed: CPLD for IO expansion and decoading

    Started by mrinalmani, 18th May 2015 18:53
    • Replies: 4
    • Views: 811
    19th May 2015, 16:44 Go to last post
  9. Closed: Verilog error with for loop

    Started by ykishore, 19th May 2015 15:28
    • Replies: 2
    • Views: 660
    19th May 2015, 16:32 Go to last post
  10. [SOLVED]Closed: [moved] Anyone experienced with Mentor Precision for synthesis?

    Started by dpaul, 11th May 2015 20:08
    • Replies: 6
    • Views: 2,407
    19th May 2015, 10:44 Go to last post
  11. Closed: [moved] Vhdl testbench for fft

    Started by vhdlpro, 18th May 2015 10:41
    • Replies: 2
    • Views: 1,150
    19th May 2015, 10:00 Go to last post
  12. Closed: Wires in verilog code does not update immediately

    Started by Ameera Q, 12th May 2015 05:08
    • Replies: 7
    • Views: 1,443
    19th May 2015, 05:19 Go to last post
  13. Closed: Instiating submodules in verilog

    Started by QMA, 13th May 2015 02:10
    • Replies: 5
    • Views: 1,764
    18th May 2015, 15:20 Go to last post
  14. Moved: C-18 compiler floating point problem

    Started by Arrowspace, 17th May 2015 17:31
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  15. Closed: Carry skip adder error in VHDL

    Started by Arrowspace, 8th May 2015 04:55
    • Replies: 17
    • Views: 2,604
    17th May 2015, 16:09 Go to last post
  16. Closed: How to get the longest one's sequence in verilog?

    Started by peto, 16th May 2015 19:45
    • Replies: 4
    • Views: 1,605
    17th May 2015, 10:11 Go to last post
  17. Closed: calculator disign using key encoder

    Started by yasminroseengle, 12th May 2015 01:38
    • Replies: 4
    • Views: 975
    15th May 2015, 19:19 Go to last post
  18. Closed: Not getting triggered in Vivado logic analyzer

    Started by rahdirs, 9th May 2015 20:03
    • Replies: 13
    • Views: 4,567
    15th May 2015, 18:40 Go to last post
  19. Closed: resent areas developed in finite state machine

    Started by arava prakash, 14th May 2015 12:29
    • Replies: 3
    • Views: 730
    15th May 2015, 12:39 Go to last post
  20. Closed: Programming Lattice iCE40LP

    Started by dora, 14th May 2015 13:31
    • Replies: 8
    • Views: 1,433
    15th May 2015, 07:59 Go to last post
  21. Closed: Ethernet connection of Spartan 3AN board

    Started by ashwinidharpale, 6th March 2015 15:50
    • Replies: 4
    • Views: 1,602
    14th May 2015, 13:01 Go to last post
  22. Closed: Stuck at fault detection of a square pulse

    Started by tv123, 10th May 2015 09:48
    • Replies: 18
    • Views: 1,246
    14th May 2015, 10:41 Go to last post
  23. Closed: Initialize the BRAMS with SDK (EDK 14.7)

    Started by Pavelglv, 22nd April 2015 22:40
    • Replies: 2
    • Views: 1,441
    13th May 2015, 18:04 Go to last post
  24. Closed: verilog-A nbit variable

    Started by wturtle, 13th May 2015 16:11
    • Replies: 0
    • Views: 664
    13th May 2015, 16:11 Go to last post
  25. Closed: Architecture for RFID Anticollision algorithm

    Started by tv123, 12th May 2015 11:23
    • Replies: 2
    • Views: 549
    13th May 2015, 14:56 Go to last post