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Threads 3001 to 3030 of 22715

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED]Closed: How to use conditional statement with ipcore?

    Started by Indrajit Ghosh, 26th April 2015 09:36
    • Replies: 4
    • Views: 695
    26th April 2015, 22:11 Go to last post
  2. Closed: How many external memory controllers can an FPGA have?

    Started by nervecell_23, 26th April 2015 19:43
    • Replies: 1
    • Views: 764
    26th April 2015, 20:33 Go to last post
  3. [SOLVED]Closed: help:make the clock divider twice as fast or 2 Hz.

    Started by saUNT, 26th April 2015 14:01
    • Replies: 4
    • Views: 807
    26th April 2015, 16:39 Go to last post
  4. Closed: design mistake "sequential type is unconnected in block"

    Started by eng.fedail, 25th April 2015 10:10
    • Replies: 4
    • Views: 1,664
    26th April 2015, 15:40 Go to last post
  5. Closed: coding radix 2^2 sdf fft in verilog

    Started by resh93, 4th February 2015 17:12
    • Replies: 1
    • Views: 2,269
    26th April 2015, 10:13 Go to last post
  6. Closed: testing bits in vhdl within if statement

    Started by rameshrai, 25th April 2015 07:08
    • Replies: 2
    • Views: 840
    26th April 2015, 01:19 Go to last post
  7. Closed: Altered Adder with binary output

    Started by Eduard Barnoviciu, 25th April 2015 12:05
    • Replies: 5
    • Views: 517
    26th April 2015, 00:42 Go to last post
  8. Closed: get FPGA to run in stand alone

    Started by VisRoboris, 25th April 2015 18:41
    • Replies: 3
    • Views: 654
    25th April 2015, 22:47 Go to last post
  9. Closed: Output variables sequentially?

    Started by random_duck, 25th April 2015 14:03
    • Replies: 4
    • Views: 755
    25th April 2015, 20:30 Go to last post
  10. [SOLVED]Closed: How to display a image on PC using FPGA FROM BRAM?

    Started by gmk3, 24th April 2015 11:05
    • Replies: 4
    • Views: 1,569
    25th April 2015, 07:05 Go to last post
  11. Closed: Frequency divider using finite state machine

    Started by tv123, 24th April 2015 14:07
    • Replies: 3
    • Views: 1,809
    25th April 2015, 05:54 Go to last post
  12. Moved: [moved] Code composer studio v6

    Started by Muhammad Amir, 23rd April 2015 17:50
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  13. Closed: Timing failure in DDR3 Design

    Started by rahdirs, 23rd April 2015 06:06
    • Replies: 3
    • Views: 1,722
    23rd April 2015, 17:07 Go to last post
  14. Closed: signal routing using clock framework

    Started by ssankurathri, 17th April 2015 06:19
    • Replies: 9
    • Views: 998
    23rd April 2015, 16:14 Go to last post
  15. [SOLVED]Closed: quartus 2 simple vhdl; Error: Node instance instantiates undefined entity.

    Started by zoulzubazz, 21st April 2015 21:57
    • Replies: 3
    • Views: 10,848
    22nd April 2015, 22:44 Go to last post
  16. Closed: where to start ? fpga

    Started by Yassine Wydadi, 22nd April 2015 12:23
    • Replies: 3
    • Views: 781
    22nd April 2015, 19:13 Go to last post
  17. [SOLVED]Closed: Problem with fixed point multiplication

    Started by normantg, 22nd April 2015 17:37
    • Replies: 1
    • Views: 776
    22nd April 2015, 17:50 Go to last post
  18. Closed: connect NEXYS3 and MRF24WG0MA

    Started by Anooshah Noshad Khan, 15th April 2015 09:56
    • Replies: 3
    • Views: 1,052
    22nd April 2015, 16:04 Go to last post
  19. Closed: disconnect flip flop to a bus

    Started by rameshrai, 22nd April 2015 11:15
    • Replies: 6
    • Views: 559
    22nd April 2015, 12:53 Go to last post
    • Replies: 15
    • Views: 1,699
    22nd April 2015, 08:41 Go to last post
  20. Closed: Routing vs. Logic percentage estimation in an FPGA design

    Started by msdarvishi, 21st April 2015 20:11
    • Replies: 1
    • Views: 700
    21st April 2015, 21:26 Go to last post
  21. Closed: How to find delay path using Tcl command?

    Started by msdarvishi, 20th April 2015 21:44
    • Replies: 3
    • Views: 912
    21st April 2015, 18:31 Go to last post
  22. Closed: adc0804 interfacing with fpga

    Started by Maxima8, 21st April 2015 03:30
    • Replies: 7
    • Views: 1,579
    21st April 2015, 18:02 Go to last post
  23. Closed: fpga and xcf04 connection

    Started by morykeys, 17th April 2015 12:21
    • Replies: 13
    • Views: 1,536
    21st April 2015, 16:41 Go to last post
  24. Closed: Altera assignment editor

    Started by shaiko, 21st April 2015 11:40
    • Replies: 3
    • Views: 1,004
    21st April 2015, 12:01 Go to last post
  25. Closed: Arithmetic in FPGA design

    Started by matrixofdynamism, 16th April 2015 12:17
    • Replies: 11
    • Views: 1,141
    20th April 2015, 16:37 Go to last post
  26. Closed: Altera DE2 Board User Interface using Verilog

    Started by michie, 19th April 2015 11:25
    • Replies: 2
    • Views: 1,184
    19th April 2015, 17:23 Go to last post
  27. Closed: Behavioral and structural modelling in verilog

    Started by tv123, 19th April 2015 06:17
    • Replies: 3
    • Views: 978
    19th April 2015, 07:38 Go to last post
  28. Closed: nexys 3 FPGA board with PmodBT2

    Started by Fazeel Ayaz, 1st April 2015 14:10
    • Replies: 2
    • Views: 1,160
    19th April 2015, 05:42 Go to last post