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Threads 3001 to 3030 of 22274

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: 16-bit register scaling to drive MDACs

    Started by sawaak, 16th December 2014 08:06
    • Replies: 0
    • Views: 566
    16th December 2014, 08:06 Go to last post
  2. Closed: VHDL for Real time applications

    Started by Y.SAI SARASWATHI, 15th December 2014 14:44
    • Replies: 1
    • Views: 823
    15th December 2014, 20:32 Go to last post
  3. [SOLVED]Closed: CPU: am designing a 4 bit CPU using VHDL on quartus 2 for altera .

    Started by axi3795, 14th December 2014 16:59
    • Replies: 3
    • Views: 1,309
    15th December 2014, 20:12 Go to last post
  4. Closed: spi slave code in vhdl

    Started by DEVI403, 12th December 2014 13:15
    • Replies: 2
    • Views: 2,623
    15th December 2014, 18:49 Go to last post
  5. Closed: sine table to Audio CODEC line out de2-70 vhdl

    Started by jackobian, 13th December 2014 04:51
    • Replies: 2
    • Views: 1,069
    15th December 2014, 18:45 Go to last post
  6. Closed: Concept of Negative setup time

    Started by VirtuosoDracula, 12th December 2014 09:11
    • Replies: 2
    • Views: 1,491
    15th December 2014, 12:45 Go to last post
  7. Closed: what is miter? Allegro 16.5 (trace width) how to use this tool

    Started by TADE, 15th December 2014 10:40
    • Replies: 1
    • Views: 709
    15th December 2014, 12:35 Go to last post
  8. Closed: RAM/ROM using VHDL, Am not really getting what to and need help

    Started by axi3795, 12th December 2014 17:38
    • Replies: 1
    • Views: 1,146
    12th December 2014, 18:01 Go to last post
  9. Closed: How to create a sine wave using lut in verilog?

    Started by keerthna, 9th December 2014 09:48
    • Replies: 10
    • Views: 1,835
    12th December 2014, 17:11 Go to last post
  10. Closed: regarding time-scale in verilog

    Started by anusha vasanta, 5th December 2014 05:33
    • Replies: 2
    • Views: 925
    12th December 2014, 14:13 Go to last post
  11. Closed: Source code -MESA - Horner Bezier

    Started by snehalkate, 11th December 2014 11:13
    • Replies: 1
    • Views: 593
    12th December 2014, 14:05 Go to last post
  12. Closed: Matlab hamming to vhdl 8-bit

    Started by OS_cilloscope, 12th December 2014 03:22
    • Replies: 1
    • Views: 901
    12th December 2014, 09:53 Go to last post
  13. Closed: Did I correctly implement this SR-Latch and D-Latch?

    Started by delta136, 10th December 2014 13:33
    • Replies: 9
    • Views: 1,123
    11th December 2014, 17:41 Go to last post
  14. Closed: How to extend 4-bit barrel shifter to 32-bit?

    Started by delta136, 10th December 2014 22:28
    • Replies: 5
    • Views: 1,667
    11th December 2014, 01:57 Go to last post
  15. Closed: Offset meaning in programming language

    Started by shan14, 10th December 2014 12:02
    • Replies: 2
    • Views: 799
    10th December 2014, 16:07 Go to last post
  16. Closed: Verilog code for counting pulses in 555timer

    Started by SURAJ7, 9th December 2014 12:13
    • Replies: 3
    • Views: 735
    10th December 2014, 06:46 Go to last post
  17. Closed: connecting Artix 7 to pc

    Started by Majid Zamani, 9th December 2014 13:58
    • Replies: 3
    • Views: 864
    10th December 2014, 02:09 Go to last post
  18. [SOLVED]Closed: How does Xilinx IP cores for sine waves generate Sine wave?

    Started by keerthna, 3rd December 2014 15:21
    • Replies: 5
    • Views: 1,813
    9th December 2014, 16:23 Go to last post
  19. Closed: pipelining concept in rtl

    Started by anusha vasanta, 9th December 2014 11:47
    • Replies: 2
    • Views: 626
    9th December 2014, 15:05 Go to last post
  20. Closed: Spartan 6 TQG144 package DDR/DDR2 interfacing

    Started by GhostInABox, 8th December 2014 11:57
    • Replies: 2
    • Views: 978
    9th December 2014, 14:01 Go to last post
  21. Closed: floating point multiplier

    Started by shan14, 9th December 2014 10:52
    • Replies: 1
    • Views: 724
    9th December 2014, 11:33 Go to last post
    • Replies: 5
    • Views: 995
    9th December 2014, 10:33 Go to last post
  22. Closed: spartan 6 FPGA + DDR2

    Started by GhostInABox, 8th December 2014 15:18
    • Replies: 3
    • Views: 1,121
    9th December 2014, 09:17 Go to last post
    • Replies: 1
    • Views: 1,187
    9th December 2014, 04:29 Go to last post
    • Replies: 2
    • Views: 669
    9th December 2014, 01:12 Go to last post
  23. Closed: State Conductor for Asynchronous Pipeline

    Started by MZulkarnain Jaranee, 5th December 2014 19:38
    • Replies: 7
    • Views: 1,386
    8th December 2014, 20:33 Go to last post
    • Replies: 2
    • Views: 3,414
    7th December 2014, 18:38 Go to last post
  24. Closed: When is it nessasary to use the VHDL null statement?

    Started by shaiko, 6th December 2014 11:24
    • Replies: 6
    • Views: 1,695
    7th December 2014, 08:25 Go to last post
  25. Closed: Decoding DCF Signal using FPGA Spartan VHDL

    Started by Raj Sohal, 6th December 2014 22:27
    • Replies: 1
    • Views: 1,496
    7th December 2014, 00:28 Go to last post