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Threads 3001 to 3030 of 22756

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Read Back CPLD Max7128

    Started by 7of9, 7th May 2015 15:25
    • Replies: 0
    • Views: 1,097
    7th May 2015, 15:25 Go to last post
  2. Closed: Field Programmable Transistor Array (FPTA)

    Started by sajjade, 30th April 2015 13:58
    • Replies: 6
    • Views: 2,981
    7th May 2015, 11:59 Go to last post
  3. [SOLVED]Closed: verilog and system verilog for behavioral models

    Started by DharmaSlice, 7th May 2015 08:01
    • Replies: 0
    • Views: 1,191
    7th May 2015, 08:01 Go to last post
  4. Moved: orcad simulation problem boost circuit

    Started by Arrowspace, 7th May 2015 04:55
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  5. Closed: Async FIFO 2 Clock code advice - VHDL

    Started by Yaro, 6th May 2015 11:52
    • Replies: 1
    • Views: 948
    6th May 2015, 22:23 Go to last post
  6. Closed: Artix7-ADC interface problem

    Started by eren000, 3rd May 2015 11:02
    • Replies: 16
    • Views: 2,193
    6th May 2015, 21:26 Go to last post
  7. Closed: Gray counter code error

    Started by Yaro, 6th May 2015 12:55
    • Replies: 6
    • Views: 1,045
    6th May 2015, 16:27 Go to last post
  8. Closed: Drawing timing diagrams/waveforms in source file

    Started by BlackHelicopter, 5th May 2015 23:41
    • Replies: 5
    • Views: 892
    6th May 2015, 01:14 Go to last post
    • Replies: 11
    • Views: 1,058
    5th May 2015, 19:08 Go to last post
  9. Closed: [moved] clock domains crossing

    Started by dora, 24th April 2015 15:31
    2 Pages
    1 2
    • Replies: 29
    • Views: 3,218
    5th May 2015, 18:10 Go to last post
  10. Closed: Array for values of a function

    Started by ctzof, 4th May 2015 13:49
    • Replies: 7
    • Views: 783
    5th May 2015, 17:49 Go to last post
  11. Closed: simulation and synthesis in VHDL

    Started by Arrowspace, 5th May 2015 02:44
    • Replies: 2
    • Views: 590
    5th May 2015, 16:02 Go to last post
  12. Closed: Look up table for a given function

    Started by ctzof, 29th April 2015 14:48
    2 Pages
    1 2
    • Replies: 21
    • Views: 2,409
    5th May 2015, 15:16 Go to last post
  13. Closed: Nyquist sammpling freq. with synchronizer

    Started by yuvalkesi, 4th May 2015 10:47
    • Replies: 8
    • Views: 875
    5th May 2015, 10:17 Go to last post
  14. Closed: Timing costraints, how to write an sdc file

    Started by Yaro, 4th May 2015 14:47
    • Replies: 4
    • Views: 2,300
    4th May 2015, 19:04 Go to last post
  15. Closed: How to locate a DFlipFlop in a specific SLICE

    Started by msdarvishi, 28th April 2015 02:01
    • Replies: 14
    • Views: 1,513
    4th May 2015, 17:55 Go to last post
  16. Closed: How To Truncate bits of decimal part in sfixed data?

    Started by soujanya04, 2nd May 2015 15:40
    • Replies: 8
    • Views: 821
    4th May 2015, 09:54 Go to last post
  17. Closed: Ultrasound transmitter pulse

    Started by jimmykk, 29th April 2015 13:24
    • Replies: 15
    • Views: 1,406
    4th May 2015, 09:42 Go to last post
  18. Closed: IF LOOP in Verilog A not working for 0.7

    Started by atulkulkarni, 30th April 2015 14:08
    • Replies: 5
    • Views: 1,085
    4th May 2015, 06:18 Go to last post
  19. Closed: how to sequence ipcore?

    Started by Indrajit Ghosh, 1st May 2015 18:15
    • Replies: 5
    • Views: 747
    2nd May 2015, 00:14 Go to last post
  20. Moved: [URGENT] How to solve Mapping problem ERROR:Pack:2811

    Started by msdarvishi, 1st May 2015 22:42
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  21. Closed: upcounter and updown counter power and area

    Started by tv123, 30th April 2015 14:51
    • Replies: 4
    • Views: 870
    1st May 2015, 09:37 Go to last post
  22. Closed: confusion in disabling a signal in verilog!!

    Started by Indrajit Ghosh, 28th April 2015 11:38
    • Replies: 10
    • Views: 1,174
    1st May 2015, 05:57 Go to last post
  23. Closed: help: adding counter

    Started by saUNT, 30th April 2015 17:15
    • Replies: 1
    • Views: 613
    30th April 2015, 17:45 Go to last post
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  24. Closed: Formal port/generic <> is not declared in--- ERROR!

    Started by kaiserschmarren87, 30th April 2015 15:07
    • Replies: 0
    • Views: 5,133
    30th April 2015, 15:07 Go to last post
  25. Closed: Using FT2232H in Sync FIFO mode for streaming out data

    Started by chensx2012, 30th April 2015 11:07
    • Replies: 1
    • Views: 957
    30th April 2015, 13:40 Go to last post
  26. Closed: Spartan 3E interface Cable

    Started by dhanya22, 11th April 2015 08:47
    • Replies: 15
    • Views: 1,495
    30th April 2015, 08:05 Go to last post