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Threads 3001 to 3030 of 22300

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: VHDL simulation with type "time"

    Started by shaiko, 23rd December 2014 17:37
    • Replies: 4
    • Views: 838
    24th December 2014, 15:31 Go to last post
  2. Closed: Can anybody help with Jedec files ?

    Started by BasicBoy, 24th December 2014 13:27
    • Replies: 1
    • Views: 457
    24th December 2014, 13:33 Go to last post
  3. Closed: FPGA PCI-e Development board ?

    Started by bianchi77, 21st December 2014 10:15
    • Replies: 4
    • Views: 1,009
    24th December 2014, 12:46 Go to last post
  4. [SOLVED]Closed: generate for loop inside a generate if loop

    Started by anusha vasanta, 22nd December 2014 07:50
    • Replies: 9
    • Views: 1,377
    24th December 2014, 05:11 Go to last post
  5. [SOLVED]Closed: VHDL How to Design a Screen (Frame) Buffer

    Started by yttuncel, 16th December 2014 20:31
    • Replies: 6
    • Views: 2,799
    23rd December 2014, 18:26 Go to last post
  6. Closed: Text on Screen using FPGA

    Started by yttuncel, 23rd December 2014 18:04
    • Replies: 0
    • Views: 716
    23rd December 2014, 18:04 Go to last post
  7. Closed: how to design the controller in vlsi

    Started by iyyappanbala, 23rd December 2014 14:21
    • Replies: 1
    • Views: 475
    23rd December 2014, 16:19 Go to last post
  8. Closed: 5V Stepper motor 28BYJ-48

    Started by Sweta25, 17th December 2014 11:22
    • Replies: 5
    • Views: 1,489
    23rd December 2014, 11:46 Go to last post
  9. Closed: what is the wrong with this code

    Started by Serwan Bamerni, 21st December 2014 23:58
    • Replies: 4
    • Views: 889
    23rd December 2014, 07:30 Go to last post
  10. Closed: Interfacing FPGA with SPARTAN 6

    Started by Ponmalar21, 19th December 2014 10:11
    • Replies: 2
    • Views: 703
    23rd December 2014, 07:09 Go to last post
  11. Closed: Active HDL 10 released

    Started by Zerox100, 21st December 2014 20:35
    • Replies: 0
    • Views: 762
    21st December 2014, 20:35 Go to last post
  12. Closed: Verification techniques for FPGA prototyping.

    Started by ghegde, 21st December 2014 06:15
    • Replies: 3
    • Views: 694
    21st December 2014, 13:38 Go to last post
  13. [SOLVED]Closed: problem in RS232 vhdl code

    Started by vishy71, 2nd December 2013 10:29
    • Replies: 7
    • Views: 1,418
    20th December 2014, 19:29 Go to last post
  14. Closed: Sizing a VHDL input port

    Started by shaiko, 16th December 2014 12:17
    2 Pages
    1 2
    • Replies: 30
    • Views: 3,190
    20th December 2014, 11:47 Go to last post
  15. Closed: how to ctrl the operation of register

    Started by anusha vasanta, 20th December 2014 07:17
    • Replies: 3
    • Views: 505
    20th December 2014, 11:11 Go to last post
    • Replies: 3
    • Views: 569
    20th December 2014, 10:25 Go to last post
    • Replies: 1
    • Views: 547
    19th December 2014, 15:25 Go to last post
  16. Closed: instantiation with in an always block

    Started by anusha vasanta, 19th December 2014 10:03
    • Replies: 4
    • Views: 725
    19th December 2014, 12:34 Go to last post
  17. Closed: Question about DDR2 ALTERA IP Controller

    Started by flote21, 18th December 2014 23:20
    • Replies: 2
    • Views: 1,238
    19th December 2014, 10:37 Go to last post
  18. Closed: Xilinx Kintex STARTUPE2

    Started by barry, 18th December 2014 16:57
    • Replies: 2
    • Views: 3,418
    18th December 2014, 20:24 Go to last post
  19. Closed: Rising edge of IN- maintains value of 1 how?

    Started by vishal_sonam, 18th December 2014 09:18
    • Replies: 3
    • Views: 701
    18th December 2014, 17:58 Go to last post
  20. Closed: Synthesizing encrypted RTL using Xilinx ISE

    Started by fahum, 17th December 2014 16:34
    • Replies: 3
    • Views: 1,794
    18th December 2014, 13:28 Go to last post
  21. Closed: Rising edge of IN- what does it mean.

    Started by vishal_sonam, 17th December 2014 20:33
    • Replies: 3
    • Views: 1,058
    18th December 2014, 09:23 Go to last post
  22. Closed: issues on data passage through wires

    Started by anusha vasanta, 18th December 2014 05:36
    • Replies: 1
    • Views: 436
    18th December 2014, 06:46 Go to last post
  23. Closed: Tools supporting verilog-2001

    Started by anusha vasanta, 15th December 2014 10:27
    • Replies: 6
    • Views: 858
    17th December 2014, 22:35 Go to last post
  24. Closed: Xilinx LogiCore Block Problem

    Started by koshmar29, 15th December 2014 22:39
    • Replies: 7
    • Views: 1,024
    17th December 2014, 06:39 Go to last post
    • Replies: 2
    • Views: 2,749
    17th December 2014, 05:43 Go to last post
  25. Closed: 16-bit register scaling to drive MDACs

    Started by sawaak, 16th December 2014 08:06
    • Replies: 0
    • Views: 579
    16th December 2014, 08:06 Go to last post
  26. Closed: VHDL for Real time applications

    Started by Y.SAI SARASWATHI, 15th December 2014 14:44
    • Replies: 1
    • Views: 845
    15th December 2014, 20:32 Go to last post
  27. [SOLVED]Closed: CPU: am designing a 4 bit CPU using VHDL on quartus 2 for altera .

    Started by axi3795, 14th December 2014 16:59
    • Replies: 3
    • Views: 1,348
    15th December 2014, 20:12 Go to last post