1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    129,539
Page 101 of 762 FirstFirst ... 51 91 99 100 101 102 103 111 151 201 601 ... LastLast
Threads 3001 to 3030 of 22858

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: How to fiix LUT inputs?

    Started by d0nathan, 5th June 2015 14:16
    • Replies: 3
    • Views: 497
    5th June 2015, 16:45 Go to last post
    • Replies: 1
    • Views: 1,855
    5th June 2015, 11:34 Go to last post
  2. Closed: How to read ram in test bench?

    Started by ultimate_kc, 4th June 2015 05:13
    • Replies: 2
    • Views: 722
    5th June 2015, 11:28 Go to last post
  3. Closed: how to initialize a 1D*1D VECTOR?

    Started by fahim1, 4th June 2015 11:37
    • Replies: 2
    • Views: 626
    5th June 2015, 11:26 Go to last post
  4. Closed: Suggestion on FPGA board on elevator system

    Started by jesslyn993, 26th May 2015 03:56
    • Replies: 6
    • Views: 1,182
    5th June 2015, 09:19 Go to last post
  5. Closed: why the signal register use its previous value?

    Started by fahim1, 4th June 2015 20:37
    • Replies: 8
    • Views: 698
    5th June 2015, 04:29 Go to last post
  6. Closed: delay calculation in vhdl

    Started by Ponmalar21, 4th June 2015 06:55
    • Replies: 2
    • Views: 664
    4th June 2015, 08:28 Go to last post
  7. Closed: How to multiplex serial data and send it to the PC?

    Started by player80, 4th June 2015 02:29
    • Replies: 1
    • Views: 615
    4th June 2015, 08:25 Go to last post
  8. Closed: Signals and variables in VHDL

    Started by bob2987, 5th March 2015 21:49
    2 Pages
    1 2
    • Replies: 25
    • Views: 2,628
    4th June 2015, 07:15 Go to last post
  9. Closed: [moved] Error debugging in vhdl

    Started by Ponmalar21, 4th June 2015 07:00
    • Replies: 0
    • Views: 542
    4th June 2015, 07:00 Go to last post
  10. Closed: boolean keyword in vhdl

    Started by p11, 3rd June 2015 22:28
    • Replies: 2
    • Views: 658
    3rd June 2015, 23:56 Go to last post
  11. Closed: Booting Linux on Nios II soft core on Stratix V FPGA

    Started by electrobuz, 3rd June 2015 20:42
    • Replies: 0
    • Views: 940
    3rd June 2015, 20:42 Go to last post
    • Replies: 6
    • Views: 926
    3rd June 2015, 20:34 Go to last post
  12. Closed: simple audio geneation on sparatn 3an

    Started by fpga.vhdl, 3rd June 2015 08:29
    • Replies: 1
    • Views: 473
    3rd June 2015, 16:50 Go to last post
  13. Closed: verilog, the wait statement

    Started by NSergeevich, 2nd June 2015 14:41
    • Replies: 5
    • Views: 1,267
    3rd June 2015, 16:26 Go to last post
  14. Closed: Errors of inout ports & their associated expressions.

    Started by wesleytaylor, 3rd June 2015 13:20
    • Replies: 1
    • Views: 1,779
    3rd June 2015, 13:42 Go to last post
  15. Closed: what does this warning(NgdBuild:478) mean?

    Started by h.m, 3rd June 2015 08:49
    • Replies: 1
    • Views: 993
    3rd June 2015, 09:38 Go to last post
  16. Closed: process statement in vhdl confusion

    Started by p11, 23rd May 2015 10:00
    2 Pages
    1 2
    • Replies: 38
    • Views: 3,354
    3rd June 2015, 06:35 Go to last post
  17. Closed: not getting right result of ALU program in VHDL

    Started by abhiinics, 31st May 2015 12:16
    • Replies: 2
    • Views: 773
    1st June 2015, 22:59 Go to last post
  18. Closed: altera cyclone V banks

    Started by davida, 1st June 2015 11:45
    • Replies: 1
    • Views: 735
    1st June 2015, 20:40 Go to last post
    • Replies: 3
    • Views: 2,153
    1st June 2015, 18:01 Go to last post
  19. Closed: SDD SATA Disk problem using Core Device FPGA

    Started by rafean, 1st June 2015 17:09
    • Replies: 0
    • Views: 629
    1st June 2015, 17:09 Go to last post
  20. Closed: how does variables behave in reading functions?

    Started by h.m, 1st June 2015 08:35
    • Replies: 4
    • Views: 753
    1st June 2015, 13:35 Go to last post
  21. [SOLVED]Closed: How to model jumper links or any crosspoint device?

    Started by wesleytaylor, 28th May 2015 11:05
    • Replies: 5
    • Views: 721
    1st June 2015, 10:21 Go to last post
  22. Closed: Verilog task query regarding while simulating

    Started by verilog_vhdl7, 15th April 2015 13:01
    • Replies: 9
    • Views: 1,049
    1st June 2015, 08:07 Go to last post
  23. Closed: error and warning in vhdl in counter

    Started by p11, 30th May 2015 07:58
    • Replies: 4
    • Views: 1,128
    30th May 2015, 15:44 Go to last post
  24. Closed: JTAG Programming of ATF1508 CPLD

    Started by Druzyek, 30th May 2015 06:18
    • Replies: 0
    • Views: 806
    30th May 2015, 06:18 Go to last post
    • Replies: 0
    • Views: 581
    30th May 2015, 03:46 Go to last post
    • Replies: 1
    • Views: 3,436
    29th May 2015, 16:28 Go to last post
  25. [SOLVED]Closed: Verilog 2001 indexed part-select +: in always block

    Started by ShanghaiDSP, 29th May 2015 11:22
    • Replies: 5
    • Views: 4,789
    29th May 2015, 16:23 Go to last post