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Threads 3001 to 3030 of 22389

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Closed: Randomication in verilog

    Started by shrikanthke, 24th January 2015 10:13
    • Replies: 2
    • Views: 621
    24th January 2015, 16:29 Go to last post
  2. Closed: Partial Reconfiguration via ICAP

    Started by msdarvishi, 24th January 2015 01:46
    • Replies: 2
    • Views: 910
    24th January 2015, 16:25 Go to last post
  3. Closed: FPGA Design, Digital Clock

    Started by action taker, 23rd January 2015 15:03
    • Replies: 12
    • Views: 1,026
    23rd January 2015, 23:44 Go to last post
  4. Closed: vhdl coding for finding image centroid

    Started by ann mary, 19th January 2015 19:25
    • Replies: 6
    • Views: 1,209
    23rd January 2015, 20:09 Go to last post
  5. Closed: Design a digital clock using FPGA

    Started by Mumba, 21st January 2015 16:39
    • Replies: 9
    • Views: 2,798
    23rd January 2015, 14:28 Go to last post
  6. Closed: 8 Bit adder/Subtractor using verilog on active HDL

    Started by Graci, 23rd January 2015 06:54
    • Replies: 1
    • Views: 3,149
    23rd January 2015, 09:17 Go to last post
  7. Closed: Immediately termination of FPGA_Editor

    Started by msdarvishi, 23rd January 2015 04:12
    • Replies: 1
    • Views: 630
    23rd January 2015, 09:16 Go to last post
  8. Closed: making some changes in NoC blocks to be faulty

    Started by mostafa272, 21st January 2015 16:11
    • Replies: 2
    • Views: 555
    22nd January 2015, 07:12 Go to last post
  9. [SOLVED]Closed: Available Placement and Routing Tools in Xilinx Virtex-5 FPGAs used currently

    Started by msdarvishi, 21st January 2015 18:48
    • Replies: 1
    • Views: 553
    21st January 2015, 19:16 Go to last post
  10. Closed: matrix transpose code for Implementation of 2D fft

    Started by shan14, 17th January 2015 11:13
    • Replies: 5
    • Views: 1,182
    21st January 2015, 17:41 Go to last post
  11. Closed: delay a impulse response

    Started by lgeorge123, 21st January 2015 13:27
    • Replies: 1
    • Views: 565
    21st January 2015, 17:24 Go to last post
  12. Closed: Lift Simulator using DE1

    Started by You Wei Lim, 21st January 2015 15:15
    • Replies: 1
    • Views: 611
    21st January 2015, 16:33 Go to last post
  13. Closed: FPGA with build-in flash

    Started by jesslyn993, 21st January 2015 03:54
    • Replies: 4
    • Views: 692
    21st January 2015, 11:57 Go to last post
  14. Closed: How to store integer string from keyboard on FPGA

    Started by koshmar29, 21st January 2015 07:36
    • Replies: 1
    • Views: 826
    21st January 2015, 08:54 Go to last post
  15. Closed: stepper motor vhdl codes

    Started by Sweta25, 21st January 2015 03:00
    • Replies: 3
    • Views: 1,581
    21st January 2015, 07:35 Go to last post
  16. Closed: Verilog coding - error correction in Xilinx platform

    Started by shrikanthke, 20th January 2015 19:32
    • Replies: 2
    • Views: 565
    20th January 2015, 23:15 Go to last post
  17. Closed: convert 2d array to 1d in vhdl

    Started by harian, 20th January 2015 12:53
    • Replies: 3
    • Views: 760
    20th January 2015, 18:56 Go to last post
  18. Closed: Creating EPCQ Block in Cyclone V

    Started by lemart92, 15th September 2014 15:35
    • Replies: 1
    • Views: 1,730
    20th January 2015, 16:01 Go to last post
  19. [SOLVED]Closed: Conformal Tool in FPGA Full CHip design

    Started by nohj_yar, 16th January 2015 09:53
    • Replies: 8
    • Views: 874
    20th January 2015, 05:53 Go to last post
  20. Closed: Timing information during synthesis

    Started by shobanaganesan, 19th January 2015 05:24
    • Replies: 4
    • Views: 809
    19th January 2015, 18:35 Go to last post
    • Replies: 1
    • Views: 608
    19th January 2015, 16:39 Go to last post
  21. Closed: what is the problem with the FDCE

    Started by Serwan Bamerni, 18th January 2015 23:45
    • Replies: 4
    • Views: 706
    19th January 2015, 10:32 Go to last post
  22. Closed: delay calculation in xilinx

    Started by shan14, 19th January 2015 07:03
    • Replies: 5
    • Views: 1,080
    19th January 2015, 10:16 Go to last post
  23. Closed: Altera FPGA pwoer-up pins state

    Started by sherif123, 18th January 2015 11:29
    • Replies: 3
    • Views: 1,105
    18th January 2015, 15:45 Go to last post
  24. [SOLVED]Closed: XST synthesis without user constraints

    Started by syn_rocks, 15th January 2015 18:05
    • Replies: 4
    • Views: 699
    17th January 2015, 08:51 Go to last post
  25. Closed: Virtex-5 IOBs swing capability

    Started by msdarvishi, 16th January 2015 03:41
    • Replies: 4
    • Views: 797
    16th January 2015, 19:52 Go to last post
  26. Closed: wheater signal or varuable while assigning inputs

    Started by harian, 16th January 2015 16:24
    • Replies: 4
    • Views: 474
    16th January 2015, 17:23 Go to last post
  27. Closed: Problem while simulation of array signals VHDL

    Started by harian, 13th January 2015 13:28
    • Replies: 7
    • Views: 1,349
    16th January 2015, 16:05 Go to last post
  28. [SOLVED]Closed: Simulation Problems - Output signal displays false values in the beginning.

    Started by sreevenkjan, 15th January 2015 09:41
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,250
    16th January 2015, 13:42 Go to last post
  29. Closed: VHDL signed numbers arithmetics

    Started by shaiko, 13th January 2015 15:29
    2 Pages
    1 2
    • Replies: 20
    • Views: 2,921
    14th January 2015, 23:55 Go to last post