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Threads 1 to 30 of 22806

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 35,609
    21st March 2007, 21:21 Go to last post
  2. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 30,785
    2nd June 2013, 16:13 Go to last post
  1. Closed: (BsystemC contraint random

    Started by anant, 22nd September 2004 16:42
    • Replies: 1
    • Views: 1,759
    15th December 2004, 10:24 Go to last post
  2. Closed:

    Started by Bosechandran, 26th December 2016 10:00
    • Replies: 6
    • Views: 1,905
    16th May 2017, 05:50 Go to last post
  3. Closed:

    Started by mehdimolu, 6th November 2018 16:32
    • Replies: 1
    • Views: 630
    7th November 2018, 00:23 Go to last post
  4. Closed: Altium LiveDesign Evaluation Board: using FPGAs CLK

    Started by Lykos1986, 24th May 2006 10:49
    • Replies: 4
    • Views: 1,740
    29th June 2006, 08:23 Go to last post
  5. Closed: vhdl model of risc architecture - link

    Started by politicante, 5th June 2003 21:13
    • Replies: 0
    • Views: 1,958
    5th June 2003, 21:13 Go to last post
  6. Closed: # FATAL ERROR while loading design # Error loading design

    Started by eng.msmahmoud, 29th December 2012 15:31
    • Replies: 3
    • Views: 5,659
    2nd January 2013, 23:31 Go to last post
  7. Closed: $39 Spartan™-3A Evaluation Kit from AVnet

    Started by arnab.bhaumik, 2nd September 2008 05:33
    • Replies: 2
    • Views: 3,823
    3rd September 2008, 04:10 Go to last post
  8. Closed: $display maximum value?

    Started by jmountney, 9th September 2013 13:23
    • Replies: 1
    • Views: 585
    9th September 2013, 14:10 Go to last post
  9. Closed: $fgets problem (SystemVerilog)

    Started by zoex666, 26th January 2013 10:48
    • Replies: 10
    • Views: 13,101
    1st February 2014, 18:05 Go to last post
  10. Closed: $fread, $fwrite not supported in modelsim

    Started by sudhirkv, 9th April 2009 07:07
    • Replies: 1
    • Views: 3,193
    9th April 2009, 20:51 Go to last post
  11. Closed: $fwrite : Argument 1 is an unknown file descriptor

    Started by Gayathrirani, 12th January 2015 10:57
    • Replies: 2
    • Views: 2,618
    12th January 2015, 18:24 Go to last post
  12. Closed: $time equivalent in vhdl

    Started by verilog2vhdl, 22nd October 2007 23:52
    • Replies: 2
    • Views: 2,173
    23rd October 2007, 09:29 Go to last post
  13. $urandom for error insertion in Systemverilog

    Started by rrucha, 15th August 2019 21:30
    • Replies: 5
    • Views: 598
    16th August 2019, 19:53 Go to last post
  14. Closed: $writememh and $writememb in Verilog

    Started by Ghassan, 13th August 2008 14:51
    • Replies: 0
    • Views: 10,014
    13th August 2008, 14:51 Go to last post
    • Replies: 5
    • Views: 3,509
    11th January 2012, 10:38 Go to last post
  15. Closed: " inferring latch(es)" vhdl error

    Started by INS-ANI, 4th October 2010 13:56
    • Replies: 9
    • Views: 4,347
    11th October 2010, 10:29 Go to last post
  16. Closed: "alias" problem in fixed_pkg

    Started by debalina, 3rd September 2011 15:44
    • Replies: 1
    • Views: 816
    3rd September 2011, 17:44 Go to last post
  17. Closed: "Bit" is undefined (more references follow) ada error

    Started by harerama, 15th May 2012 08:30
    • Replies: 2
    • Views: 1,430
    15th May 2012, 09:47 Go to last post
  18. Closed: "clock skew"-"clock delay"......PLL-DLL

    Started by SAV, 19th November 2004 21:00
    • Replies: 6
    • Views: 4,053
    28th December 2004, 03:24 Go to last post
  19. Closed: "Cloning" an FPGA from a closed supplier

    Started by lokko, 3rd January 2011 02:25
    • Replies: 5
    • Views: 1,345
    3rd January 2011, 05:21 Go to last post
  20. Closed: "Digital Design" by MorrisMano book request

    Started by saurabhmmmec, 4th April 2008 18:53
    • Replies: 6
    • Views: 1,899
    18th February 2009, 22:58 Go to last post
    • Replies: 3
    • Views: 1,332
    7th December 2006, 03:24 Go to last post
  21. Closed: "drawing cannot contain placeholder" error in silvaco gateway

    Started by remaja, 20th June 2013 03:59
    • Replies: 0
    • Views: 810
    20th June 2013, 03:59 Go to last post
  22. Closed: "Edge not allowed in level-sensitive path" in comp

    Started by jay_ec_engg, 3rd May 2005 05:49
    • Replies: 4
    • Views: 2,344
    3rd May 2005, 16:05 Go to last post
  23. [SOLVED]Closed: "ERROR: [Common 17-165] Too many positional options when parsing

    Started by rafimiet, 13th September 2017 07:55
    • Replies: 7
    • Views: 3,779
    14th September 2017, 10:51 Go to last post
  24. Closed: "Evaluation boards" versus "Production boards"

    Started by FlyingDutch, 1st August 2018 09:39
    • Replies: 3
    • Views: 517
    1st August 2018, 16:49 Go to last post
  25. Closed: "for loop" in FPGA

    Started by Shoaib, 22nd March 2004 21:12
    • Replies: 14
    • Views: 6,473
    2nd August 2004, 11:32 Go to last post
  26. Closed: "Frequency Bridge" for data translation

    Started by zorax85, 27th September 2011 10:24
    • Replies: 3
    • Views: 880
    27th September 2011, 12:05 Go to last post
  27. Closed: "gated clock" warning, what is the solution for my code?

    Started by Fractional-N, 26th February 2014 14:34
    • Replies: 2
    • Views: 3,113
    26th February 2014, 15:00 Go to last post