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Threads 1 to 30 of 22715

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 32,798
    21st March 2007, 21:21 Go to last post
  2. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 27,849
    2nd June 2013, 16:13 Go to last post
  1. Closed: 4 bit full adder in verilog

    Started by icaniwill, 28th February 2009 15:47
    • Replies: 6
    • Views: 131,201
    14th February 2013, 21:01 Go to last post
  2. Closed: USB Blaster download cable design

    Started by air2008, 4th April 2005 03:10
    6 Pages
    1 2 3 ... 6
    • Replies: 108
    • Views: 114,231
    14th August 2010, 05:48 Go to last post
  3. Closed: Verilog code for frequency divider (50 Mhz to 1 kHz)

    Started by ph333sh, 11th September 2008 04:22
    • Replies: 19
    • Views: 107,107
    27th July 2013, 21:33 Go to last post
  4. Closed: Multi-dimensional array in VHDL

    Started by gnudaemon, 19th January 2005 12:54
    • Replies: 17
    • Views: 103,932
    6th May 2014, 08:45 Go to last post
  5. Closed: Verilog Code : 'define & parameter

    Started by choonlle, 22nd August 2006 06:00
    • Replies: 6
    • Views: 103,671
    31st August 2006, 07:36 Go to last post
  6. Closed: Difference between LVTTL and LVCMOS..?

    Started by giggs11, 30th October 2004 05:33
    • Replies: 2
    • Views: 88,449
    2nd November 2004, 14:05 Go to last post
  7. Closed: What is the difference of CPLD and FPGA?

    Started by bunalmis, 1st December 2003 09:24
    2 Pages
    1 2
    • Replies: 24
    • Views: 81,415
    24th November 2008, 08:54 Go to last post
  8. Closed: VHDL hexadecimal instead of binary

    Started by shaiko, 2nd March 2012 22:25
    • Replies: 10
    • Views: 79,796
    5th March 2012, 09:44 Go to last post
  9. Closed: Code for division in VHDL

    Started by kavitha_bonthu, 4th February 2008 16:17
    • Replies: 16
    • Views: 74,486
    6th October 2013, 05:04 Go to last post
  10. Closed: vhdl code for d flipflop

    Started by divyak, 25th October 2006 13:09
    • Replies: 10
    • Views: 73,722
    29th July 2011, 16:54 Go to last post
  11. Closed: How to Initialize 2D array in VHDL?

    Started by alexz, 19th February 2007 12:59
    • Replies: 2
    • Views: 73,199
    19th February 2007, 16:22 Go to last post
  12. Closed: How can I describe a ROM in VHDL?

    Started by skycanny, 11th May 2005 03:46
    2 Pages
    1 2
    • Replies: 29
    • Views: 71,216
    14th August 2011, 21:22 Go to last post
  13. Closed: need simple text lcd display VHDL code

    Started by lupineye, 4th November 2006 06:20
    2 Pages
    1 2
    • Replies: 28
    • Views: 71,183
    1st December 2012, 13:54 Go to last post
  14. Closed: What is the best VHDL book?

    Started by delay, 14th June 2004 06:10
    4 Pages
    1 2 3 ... 4
    • Replies: 66
    • Views: 69,462
    28th February 2012, 02:00 Go to last post
  15. Closed: VHDL Program for a 4 bit full-adder

    Started by fm_com_28, 10th October 2006 21:33
    • Replies: 5
    • Views: 68,236
    17th September 2014, 09:24 Go to last post
  16. Closed: VHDL Type Conversion : from SIGNED to STD_LOGIC_VECTOR

    Started by omara007, 27th October 2005 04:43
    • Replies: 7
    • Views: 67,972
    4th August 2007, 17:53 Go to last post
  17. Closed: how to realize a SPI interface with VHDL?

    Started by ymq8328, 8th September 2005 07:05
    2 Pages
    1 2
    • Replies: 29
    • Views: 66,758
    30th January 2013, 11:45 Go to last post
  18. Closed: How to convert 'real' values to std_logic_vector ?

    Started by GeekWizard, 6th April 2008 23:22
    • Replies: 8
    • Views: 66,375
    13th April 2008, 18:45 Go to last post
  19. Closed: What is the $clog2 built-in function do in systemverilog???

    Started by alam.tauqueer, 22nd January 2010 10:50
    • Replies: 1
    • Views: 63,917
    24th January 2010, 04:05 Go to last post
  20. Closed: VHDL vector integer conversion question

    Started by 555lin, 25th September 2007 11:44
    • Replies: 14
    • Views: 60,272
    28th June 2008, 13:55 Go to last post
  21. Closed: How to declare and define 2D array in VHDL?

    Started by sivamit, 5th November 2006 07:17
    • Replies: 8
    • Views: 60,087
    7th November 2006, 13:05 Go to last post
  22. Closed: Generate Loop in Verilog 2001

    Started by appu1985, 22nd June 2007 02:58
    • Replies: 13
    • Views: 59,714
    4th June 2010, 06:31 Go to last post
  23. Closed: how to use % operator in verilog

    Started by taolibuyan, 12th December 2007 16:50
    • Replies: 12
    • Views: 59,479
    13th November 2014, 09:48 Go to last post
  24. Closed: reading a file in testbench(verilog)

    Started by param, 10th March 2006 10:25
    • Replies: 6
    • Views: 59,068
    22nd November 2011, 12:06 Go to last post
  25. Closed: VHDL:Convert std_logic to integer

    Started by christian.m, 18th November 2011 09:44
    • Replies: 12
    • Views: 58,948
    28th August 2012, 22:06 Go to last post
  26. Closed: Structural VHDL code for SR Flip-Flop

    Started by BlackOps, 29th February 2008 15:54
    • Replies: 13
    • Views: 58,184
    16th December 2010, 12:22 Go to last post
  27. Closed: About inout ports in verilog

    Started by int19, 3rd July 2007 13:46
    • Replies: 4
    • Views: 57,893
    5th July 2007, 16:56 Go to last post
  28. Closed: How does inout pin declaration in VHDL work?

    Started by alexz, 30th January 2006 16:04
    • Replies: 19
    • Views: 57,703
    4th August 2012, 23:45 Go to last post
  29. Closed: CRC32 implementation in ETHERNET : exact way

    Started by dilan2005, 17th March 2008 05:24
    2 Pages
    1 2
    • Replies: 22
    • Views: 57,653
    1st February 2012, 05:35 Go to last post
  30. Closed: Explanation of timescale 1ns/1ps in Verilog

    Started by prshanth dk, 29th August 2005 09:36
    • Replies: 4
    • Views: 57,403
    2nd September 2005, 11:05 Go to last post