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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 27,808
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 32,765
    21st March 2007, 21:21 Go to last post
  1. Closed: USB Blaster download cable design

    Started by air2008, 4th April 2005 03:10
    6 Pages
    1 2 3 ... 6
    • Replies: 108
    • Views: 114,192
    14th August 2010, 05:48 Go to last post
  2. Closed: Syncronous FIFO - flag generation

    Started by shaiko, 30th June 2014 13:00
    6 Pages
    1 2 3 ... 6
    • Replies: 108
    • Views: 8,514
    19th July 2014, 03:21 Go to last post
  3. Closed: Help in Digital Converter with VHDL

    Started by YenYu, 19th July 2007 09:40
    6 Pages
    1 2 3 ... 6
    • Replies: 102
    • Views: 12,531
    17th August 2007, 18:27 Go to last post
  4. Closed: FPGA, CPLD in Egypt ?!

    Started by causeitso, 12th August 2006 15:05
    5 Pages
    1 2 3 ... 5
    • Replies: 82
    • Views: 10,667
    24th October 2010, 19:32 Go to last post
  5. Closed: Need code for generating clock doubler using DCM...

    Started by vidyaredy, 17th June 2008 12:19
    5 Pages
    1 2 3 ... 5
    • Replies: 80
    • Views: 26,065
    26th March 2014, 07:06 Go to last post
  6. Closed: How to fill a RAM using VHDL code?

    Started by prakashvenugopal, 28th October 2011 11:23
    4 Pages
    1 2 3 ... 4
    • Replies: 69
    • Views: 14,882
    20th December 2011, 09:10 Go to last post
  7. [SOLVED] Verilog Error : Too Few Parameters Passed To Task

    Started by AshkanYJM, 12th August 2014 18:05
    4 Pages
    1 2 3 ... 4
    • Replies: 67
    • Views: 6,605
    6th September 2014, 07:07 Go to last post
  8. Closed: What is the best VHDL book?

    Started by delay, 14th June 2004 06:10
    4 Pages
    1 2 3 ... 4
    • Replies: 66
    • Views: 69,446
    28th February 2012, 02:00 Go to last post
  9. Closed: Accessing records in VHDL

    Started by shaiko, 29th July 2015 09:03
    4 Pages
    1 2 3 ... 4
    • Replies: 66
    • Views: 8,678
    8th August 2015, 10:56 Go to last post
  10. Closed: Trouble getting started with a Spartan-6

    Started by EnderW4785, 31st January 2012 02:44
    4 Pages
    1 2 3 ... 4
    • Replies: 64
    • Views: 11,891
    28th February 2012, 18:50 Go to last post
  11. Verilog testbench help!! (bit urgent)

    Started by sonika111, 8th March 2018 14:43
    4 Pages
    1 2 3 ... 4
    • Replies: 62
    • Views: 5,692
    16th March 2018, 16:56 Go to last post
  12. Closed: a program to output a specified image to a stream of integers for VHDL file input

    Started by fanwel, 12th December 2011 08:48
    3 Pages
    1 2 3
    • Replies: 59
    • Views: 4,923
    5th January 2012, 03:45 Go to last post
  13. Closed: SPI on FPGA - output 1 byte from one port?

    Started by kidi3, 7th October 2015 19:51
    3 Pages
    1 2 3
    • Replies: 58
    • Views: 4,478
    26th October 2015, 15:59 Go to last post
  14. Closed: need of help for designing 8x8 led matrix

    Started by prakashvenugopal, 4th August 2011 08:47
    3 Pages
    1 2 3
    • Replies: 56
    • Views: 7,833
    6th September 2011, 09:24 Go to last post
  15. Closed: Two clock domain- Problem!

    Started by PeterUK2009, 2nd July 2013 18:32
    3 Pages
    1 2 3
    • Replies: 56
    • Views: 4,551
    26th July 2013, 16:40 Go to last post
  16. Closed: Implement I2C in VHDL

    Started by Ironlord, 16th October 2018 07:47
    3 Pages
    1 2 3
    • Replies: 55
    • Views: 4,053
    23rd November 2018, 13:02 Go to last post
  17. Poll: Closed: [POLL] Program your FPGA?

    Started by mobile-it, 6th October 2005 06:21
    3 Pages
    1 2 3
    • Replies: 53
    • Views: 8,943
    27th November 2010, 06:56 Go to last post
  18. Closed: acessing a binary string from a test bench input and storing a part of it in an array

    Started by chat, 17th March 2011 07:06
    3 Pages
    1 2 3
    • Replies: 49
    • Views: 3,525
    18th March 2011, 08:41 Go to last post
  19. [SOLVED]Closed: [moved] Can't get data from I2C slave register with FPGA

    Started by tumkayaonur, 25th November 2015 14:20
    3 Pages
    1 2 3
    • Replies: 46
    • Views: 4,312
    10th December 2015, 15:52 Go to last post
  20. Closed: I want to learn VLSI, FPGA and ASIC

    Started by nikhilele, 30th August 2006 10:57
    3 Pages
    1 2 3
    • Replies: 45
    • Views: 22,261
    29th July 2012, 06:26 Go to last post
  21. Closed: MP3 decoder chip built with PLD and VHDL

    Started by wafer101, 11th December 2002 01:00
    3 Pages
    1 2 3
    • Replies: 44
    • Views: 26,057
    8th February 2005, 15:46 Go to last post
  22. Closed: need help with designing QPSK modulator/demodulator

    Started by neocool, 2nd September 2004 16:25
    3 Pages
    1 2 3
    • Replies: 44
    • Views: 26,113
    29th January 2010, 08:07 Go to last post
  23. [SOLVED]Closed: Systematic Cyclic Encoder in VHDL

    Started by Morell, 1st December 2015 09:11
    3 Pages
    1 2 3
    • Replies: 44
    • Views: 4,824
    18th December 2015, 17:35 Go to last post
  24. Closed: reading image data stored in text file using vhdl in xilinx

    Started by kakarala, 25th June 2010 19:30
    3 Pages
    1 2 3
    • Replies: 43
    • Views: 14,147
    31st May 2013, 09:06 Go to last post
  25. UCF for spi in nexys3

    Started by Ananhasaasneh77, 2nd May 2016 15:00
    3 Pages
    1 2 3
    • Replies: 43
    • Views: 3,762
    6th May 2016, 16:41 Go to last post
  26. Closed: HDL Entry vs. Schematic Entry Tool?

    Started by wzdreamer, 3rd March 2003 20:56
    3 Pages
    1 2 3
    • Replies: 42
    • Views: 11,851
    31st May 2007, 16:12 Go to last post
  27. Closed: Which VHDL/Verilog Editor is the best ?

    Started by ddboy40, 18th May 2007 05:10
    3 Pages
    1 2 3
    • Replies: 42
    • Views: 46,627
    3rd December 2011, 13:23 Go to last post
  28. Closed: Problem with including variables in VHDL for state machines

    Started by ombadei, 10th May 2009 05:03
    3 Pages
    1 2 3
    • Replies: 42
    • Views: 12,970
    28th May 2009, 00:49 Go to last post
  29. Closed: comparator with a single input

    Started by kcinimod, 20th December 2011 18:22
    3 Pages
    1 2 3
    • Replies: 42
    • Views: 2,820
    5th January 2012, 14:55 Go to last post
  30. Closed: how to connect External memory to altera fpga

    Started by zarakhan, 10th October 2014 12:14
    3 Pages
    1 2 3
    • Replies: 41
    • Views: 7,105
    14th October 2014, 08:56 Go to last post