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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 26,665
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 31,756
    21st March 2007, 21:21 Go to last post
    • Replies: 7
    • Views: 199
    Yesterday, 16:07 Go to last post
  1. VHDL code for 74hc4094

    Started by sa007jbond, 19th May 2019 12:55
    • Replies: 2
    • Views: 213
    Yesterday, 08:10 Go to last post
  2. rem and mod operators

    Started by mahmood.n, 18th May 2019 07:59
    • Replies: 10
    • Views: 1,152
    20th May 2019, 16:22 Go to last post
  3. Including VHDL libraries to add two signals

    Started by joniengr, 17th May 2019 08:42
    • Replies: 8
    • Views: 1,443
    17th May 2019, 19:15 Go to last post
    • Replies: 4
    • Views: 156
    17th May 2019, 07:46 Go to last post
    • Replies: 1
    • Views: 141
    16th May 2019, 21:32 Go to last post
  4. VHDL modulo 2^64 addition

    Started by MSAKARIM, 12th May 2019 17:02
    • Replies: 10
    • Views: 396
    14th May 2019, 17:08 Go to last post
  5. FPGA and processors working

    Started by sushl, 14th May 2019 12:38
    • Replies: 4
    • Views: 430
    14th May 2019, 14:24 Go to last post
  6. [SOLVED] Writing to an output file in VHDL

    Started by MSAKARIM, 14th May 2019 12:48
    • Replies: 2
    • Views: 173
    14th May 2019, 13:56 Go to last post
  7. Is this old design a candidate for CPLD?

    Started by ezflyr, 9th May 2019 22:03
    • Replies: 7
    • Views: 236
    10th May 2019, 16:22 Go to last post
    • Replies: 2
    • Views: 297
    10th May 2019, 08:55 Go to last post
  8. HDMI in and out , just connected in to out.

    Started by abimann, 10th April 2019 12:01
    • Replies: 14
    • Views: 1,958
    9th May 2019, 16:42 Go to last post
  9. Circular buffer design

    Started by design_newbie, 30th April 2019 14:30
    2 Pages
    1 2
    • Replies: 22
    • Views: 2,816
    7th May 2019, 20:23 Go to last post
  10. VHDL the maximum width of databus

    Started by AudenHaung, 3rd May 2019 10:17
    • Replies: 3
    • Views: 509
    7th May 2019, 11:40 Go to last post
  11. how to check a register value is 1 using verilog?

    Started by Poomagal, 30th April 2019 08:57
    • Replies: 9
    • Views: 329
    4th May 2019, 14:15 Go to last post
    • Replies: 2
    • Views: 577
    3rd May 2019, 16:42 Go to last post
    • Replies: 12
    • Views: 785
    3rd May 2019, 16:32 Go to last post
  12. Verilog beginner: is synthetized rtl optimal?

    Started by Joel_Damato, 25th April 2019 09:04
    • Replies: 10
    • Views: 477
    29th April 2019, 14:38 Go to last post
  13. [SOLVED] Convert from STD_LOGIC to integer in VHDL

    Started by MSAKARIM, 26th April 2019 11:47
    • Replies: 7
    • Views: 445
    27th April 2019, 17:38 Go to last post
    • Replies: 0
    • Views: 228
    26th April 2019, 12:08 Go to last post
  14. Audio file sending via pmod wifi to zybo board

    Started by ya_montazar, 26th April 2019 03:50
    • Replies: 1
    • Views: 290
    26th April 2019, 09:15 Go to last post
  15. [SOLVED] ASMD Chart decision boxes for OR condition

    Started by eengr, 25th April 2019 09:36
    • Replies: 2
    • Views: 216
    25th April 2019, 17:04 Go to last post
    • Replies: 6
    • Views: 467
    24th April 2019, 09:04 Go to last post
  16. Link Training with IO DELAY

    Started by beginner_EDA, 12th April 2019 10:22
    • Replies: 7
    • Views: 750
    23rd April 2019, 12:42 Go to last post