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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 25,332
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,764
    21st March 2007, 21:21 Go to last post
  1. PLS explain how to make BRAM

    Started by abimann, 2nd December 2018 07:00
    • Replies: 10
    • Views: 376
    Yesterday, 21:41 Go to last post
  2. Input and output delay values for FPGA

    Started by Alauddin123, Yesterday 06:47
    • Replies: 1
    • Views: 91
    Yesterday, 20:06 Go to last post
  3. clocking issues in capturing debug signals in ILA

    Started by Alauddin123, 15th November 2018 06:57
    • Replies: 3
    • Views: 310
    Yesterday, 06:39 Go to last post
  4. [SOLVED] Verilog Interview Question

    Started by rahdirs, 6th December 2018 23:06
    • Replies: 5
    • Views: 366
    Yesterday, 01:36 Go to last post
    • Replies: 1
    • Views: 63
    14th December 2018, 22:09 Go to last post
  5. Converting Verilog to VHDL

    Started by joniengr, 6th December 2018 11:45
    • Replies: 11
    • Views: 427
    14th December 2018, 15:51 Go to last post
    • Replies: 4
    • Views: 358
    12th December 2018, 09:29 Go to last post
  6. Xilinx XPower Analyzer Confidence Level

    Started by dayana42200, 10th December 2018 02:38
    • Replies: 4
    • Views: 291
    12th December 2018, 00:09 Go to last post
  7. Fixed point complex numbers in sdSOC

    Started by Radhikamkr, 10th December 2018 13:34
    • Replies: 0
    • Views: 153
    10th December 2018, 13:34 Go to last post
  8. Design a 4-core processor on FPGA

    Started by adwnis123, 7th December 2018 15:11
    • Replies: 9
    • Views: 414
    8th December 2018, 18:02 Go to last post
  9. Why Quarus Prime is uninstalled after restart a Windows?

    Started by frdm90, 5th December 2018 16:40
    • Replies: 4
    • Views: 190
    6th December 2018, 17:01 Go to last post
  10. Generating SAIF file

    Started by dayana42200, 3rd December 2018 02:43
    • Replies: 7
    • Views: 347
    6th December 2018, 01:43 Go to last post
  11. USB Softcore for FPGA

    Started by promach, 1st December 2018 05:29
    • Replies: 4
    • Views: 329
    5th December 2018, 09:11 Go to last post
    • Replies: 4
    • Views: 174
    4th December 2018, 18:03 Go to last post
  12. VHDL unconstrained array in VCS

    Started by shaiko, 4th December 2018 13:13
    • Replies: 2
    • Views: 129
    4th December 2018, 14:31 Go to last post
  13. Spartan-6 Servo Control

    Started by prakash_kadri, 28th November 2018 12:04
    • Replies: 6
    • Views: 389
    30th November 2018, 02:54 Go to last post
  14. Best Way to Implement Shared RAM

    Started by groover, 26th November 2018 21:46
    2 Pages
    1 2
    • Replies: 25
    • Views: 659
    29th November 2018, 23:17 Go to last post
  15. Propper clock generation for SPI protocol

    Started by Ironlord, 27th November 2018 13:05
    • Replies: 14
    • Views: 443
    29th November 2018, 13:24 Go to last post
  16. Using different time units in Verilog simulation

    Started by shaiko, 25th November 2018 00:09
    • Replies: 2
    • Views: 260
    26th November 2018, 16:52 Go to last post
  17. [SOLVED] Instantiating module with inout

    Started by ranayehya, 26th November 2018 08:03
    • Replies: 4
    • Views: 198
    26th November 2018, 15:23 Go to last post
  18. Definitions for a Memory in Verilog

    Started by groover, 25th November 2018 20:49
    • Replies: 0
    • Views: 203
    25th November 2018, 20:49 Go to last post
    • Replies: 2
    • Views: 168
    25th November 2018, 20:40 Go to last post
  19. System Verilog - default type of a declared variable

    Started by shaiko, 24th November 2018 18:53
    • Replies: 7
    • Views: 321
    25th November 2018, 15:39 Go to last post
  20. Parameter location in a Verilog Module

    Started by shaiko, 24th November 2018 20:12
    • Replies: 1
    • Views: 151
    24th November 2018, 20:28 Go to last post
  21. Verilog & System Verilog - port sizing by inheritance

    Started by shaiko, 24th November 2018 13:43
    • Replies: 1
    • Views: 155
    24th November 2018, 15:48 Go to last post
  22. Implement I2C in VHDL

    Started by Ironlord, 16th October 2018 07:47
    3 Pages
    1 2 3
    • Replies: 55
    • Views: 2,208
    23rd November 2018, 13:02 Go to last post
    • Replies: 3
    • Views: 176
    22nd November 2018, 21:16 Go to last post
  23. reorder queue mechanism

    Started by promach, 18th September 2018 04:33
    • Replies: 10
    • Views: 896
    20th November 2018, 09:10 Go to last post
  24. FPGA ALM or LAB estimated size

    Started by PablodlR, 29th October 2018 13:14
    • Replies: 6
    • Views: 478
    20th November 2018, 07:26 Go to last post