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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 26,067
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 31,222
    21st March 2007, 21:21 Go to last post
  1. Color sensor and Basys3 with VHDL

    Started by kmesne, Yesterday 19:18
    • Replies: 0
    • Views: 39
    Yesterday, 19:18 Go to last post
  2. VHDL coding Status register read problem

    Started by eengr, 15th March 2019 18:35
    • Replies: 4
    • Views: 163
    Yesterday, 16:09 Go to last post
    • Replies: 4
    • Views: 204
    Yesterday, 14:19 Go to last post
  3. Negative Slack / Report Analysis

    Started by player80, 9th March 2019 05:37
    2 Pages
    1 2
    • Replies: 21
    • Views: 906
    16th March 2019, 18:00 Go to last post
  4. [SOLVED] VHDL code Counter problem

    Started by eengr, 13th March 2019 19:20
    • Replies: 5
    • Views: 286
    15th March 2019, 18:00 Go to last post
  5. Triangular wave generator in FPGA

    Started by Ironlord, 15th March 2019 09:14
    • Replies: 2
    • Views: 140
    15th March 2019, 13:32 Go to last post
    • Replies: 0
    • Views: 177
    13th March 2019, 05:44 Go to last post
    • Replies: 4
    • Views: 179
    12th March 2019, 23:29 Go to last post
  6. Why my 2-digit counter w/VHDL didn't work?

    Started by huytergan, 12th March 2019 12:44
    • Replies: 5
    • Views: 233
    12th March 2019, 15:28 Go to last post
    • Replies: 0
    • Views: 82
    12th March 2019, 01:52 Go to last post
  7. FPGA vendors outside USA

    Started by bga72, 11th March 2019 17:59
    • Replies: 3
    • Views: 162
    11th March 2019, 20:48 Go to last post
    • Replies: 3
    • Views: 192
    11th March 2019, 14:22 Go to last post
  8. [SOLVED] VHDL syntax for floating point

    Started by eengr, 4th March 2019 14:28
    • Replies: 16
    • Views: 592
    11th March 2019, 13:13 Go to last post
  9. vhdl - config with adv7511

    Started by avishai11910, 10th March 2019 01:43
    • Replies: 2
    • Views: 149
    10th March 2019, 09:16 Go to last post
  10. Round Robin gate-level diagram

    Started by promach, 4th March 2019 14:14
    • Replies: 5
    • Views: 384
    10th March 2019, 05:28 Go to last post
  11. Floorplanning example?

    Started by player80, 7th March 2019 14:57
    • Replies: 4
    • Views: 250
    7th March 2019, 19:40 Go to last post
  12. [SOLVED] Can you help me with this Verilog to VHDL translation?

    Started by Ironlord, 6th March 2019 11:02
    • Replies: 10
    • Views: 386
    7th March 2019, 08:27 Go to last post
  13. Lattice Radiant Warnings list

    Started by ilik, 19th December 2018 15:06
    • Replies: 1
    • Views: 231
    6th March 2019, 11:48 Go to last post
  14. Synthesizable modulo operator

    Started by promach, 1st March 2019 04:12
    • Replies: 3
    • Views: 2,112
    1st March 2019, 22:14 Go to last post
  15. Allowed values for generic parameters

    Started by ireon, 27th February 2019 12:39
    • Replies: 3
    • Views: 298
    1st March 2019, 10:13 Go to last post
  16. [SOLVED] Add templates ODDR and OSERDESE2 in vhdl project

    Started by Cesar0182, 28th February 2019 15:46
    • Replies: 2
    • Views: 174
    28th February 2019, 19:52 Go to last post
  17. [moved] Lattice CPLD Reconstruction and porting

    Started by wwfeldman, 25th February 2019 17:39
    • Replies: 7
    • Views: 382
    28th February 2019, 17:22 Go to last post
  18. Spidergon Networks-on-Chips

    Started by promach, 27th February 2019 03:29
    • Replies: 0
    • Views: 141
    27th February 2019, 03:29 Go to last post
    • Replies: 11
    • Views: 440
    26th February 2019, 21:03 Go to last post
  19. Can a gated input clock be a problem for a design?

    Started by player80, 21st February 2019 10:06
    • Replies: 4
    • Views: 288
    26th February 2019, 20:06 Go to last post
  20. FPGA to HPS interrupts

    Started by Ironlord, 21st February 2019 12:49
    • Replies: 4
    • Views: 350
    26th February 2019, 09:00 Go to last post
  21. Unfamiliar VHDL | operator

    Started by shaiko, 23rd February 2019 03:50
    • Replies: 1
    • Views: 331
    23rd February 2019, 08:52 Go to last post
  22. VHDL code flow in ISE Design Suite 14.7

    Started by prakash_kadri, 19th February 2019 08:40
    • Replies: 7
    • Views: 373
    23rd February 2019, 01:18 Go to last post