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Threads 1 to 30 of 22899

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 32,288
    mrflibble
    2nd June 2013, 16:13 Go to last post

  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 37,554
    klug
    21st March 2007, 21:21 Go to last post

  1. VHDL errror for real, std_logic_vector for sine value in DDS

    Started by sangitacp93, Yesterday 09:17
    • Replies: 2
    • Views: 163
    TrickyDicky
    Yesterday, 13:18 Go to last post

  2. [SOLVED] Device Support for MAX10 FPGA

    Started by gary36, 28th April 2020 16:08
    1 Attachment(s)
    • Replies: 10
    • Views: 1,523
    gary36
    30th May 2020, 12:11 Go to last post

  3. Parameterized register chain in Systemverilog

    Started by shaiko, 27th May 2020 15:53
    • Replies: 3
    • Views: 410
    ads-ee
    28th May 2020, 19:23 Go to last post

  4. Limitations of unpacked arrays

    Started by shaiko, 27th May 2020 12:07
    • Replies: 0
    • Views: 162
    shaiko
    27th May 2020, 12:07 Go to last post

  5. Default type of a Systemverilog port

    Started by shaiko, 27th May 2020 00:34
    • Replies: 3
    • Views: 293
    dave_59
    27th May 2020, 06:41 Go to last post

  6. ZYNQ based data acquisition system

    Started by joniengr, 26th May 2020 19:17
    • Replies: 0
    • Views: 193
    joniengr
    26th May 2020, 19:17 Go to last post

  7. Google Coral Dev board vs FPGA

    Started by adwnis123, 1st May 2020 18:09
    • Replies: 2
    • Views: 1,202
    adwnis123
    24th May 2020, 12:52 Go to last post

  8. double-edged clock in VHDL

    Started by mahmood.n, 22nd May 2020 12:08
    1 Attachment(s)
    • Replies: 6
    • Views: 434
    FvM
    22nd May 2020, 14:44 Go to last post

  9. Implementation error (ERROR: Place: 1500) on ISE 14.5

    Started by Cesar0182, 18th May 2020 17:59
    1 Attachment(s)
    • Replies: 4
    • Views: 513
    dpaul
    22nd May 2020, 08:46 Go to last post

  10. Looking for lite synthesis software

    Started by mahmood.n, 17th May 2020 00:45
    1 Attachment(s)
    • Replies: 3
    • Views: 398
    danadakk
    20th May 2020, 18:17 Go to last post

  11. MISR polynomial selection criteria?

    Started by ibtesam90, 18th May 2020 14:37
    • Replies: 0
    • Views: 231
    ibtesam90
    18th May 2020, 14:37 Go to last post

  12. Implementation suggestion on memory mapped IO

    Started by Zerox100, 16th May 2020 07:16
    • Replies: 3
    • Views: 453
    Zerox100
    18th May 2020, 12:20 Go to last post

  13. Technology map viewer

    Started by mahmood.n, 17th May 2020 09:39
    4 Attachment(s)
    • Replies: 7
    • Views: 591
    Akanimo
    17th May 2020, 20:47 Go to last post

  14. [SOLVED] Vivado Synthesis failed with No errors or warnning

    Started by MSAKARIM, 7th May 2020 17:14
    • Replies: 15
    • Views: 1,500
    MSAKARIM
    17th May 2020, 16:05 Go to last post

  15. [SOLVED] Adding '1' to a std_logic_vector in VHDL

    Started by chandlerbing65nm, 23rd March 2020 16:54
    2 Attachment(s)
    • Replies: 8
    • Views: 1,062
    surajrgupta
    16th May 2020, 21:44 Go to last post

  16. Failed coverage in NoC coding

    Started by promach, 16th May 2020 04:34
    • Replies: 0
    • Views: 213
    promach
    16th May 2020, 04:34 Go to last post

  17. VHDL functions mistakes?

    Started by clros, 15th May 2020 17:22
    • Replies: 3
    • Views: 307
    TrickyDicky
    15th May 2020, 23:27 Go to last post

  18. UART Transmit issue with CPLD

    Started by reservevoltage, 5th May 2020 10:08
    • Replies: 3
    • Views: 1,051
    ads-ee
    11th May 2020, 16:28 Go to last post

  19. Nexys video Artix-7 board - PCIe Ethernet FMC high throughput and low latency

    Started by QuantAl_go, 9th May 2020 12:04
    • Replies: 1
    • Views: 370
    dpaul
    11th May 2020, 08:53 Go to last post

  20. Returning error from Modelsim to bash script

    Started by braam7, 10th May 2020 19:22
    • Replies: 0
    • Views: 214
    braam7
    10th May 2020, 19:22 Go to last post

  21. Verilog with multiple if conditions

    Started by techy5025, 10th May 2020 02:30
    • Replies: 3
    • Views: 430
    techy5025
    10th May 2020, 18:13 Go to last post

  22. Verilog/SV: can assign + ternary produce latches?

    Started by pbernardi, 5th May 2020 19:51
    • Replies: 6
    • Views: 1,858
    vGoodtimes
    9th May 2020, 07:57 Go to last post

  23. BRAM model question?

    Started by Zerox100, 5th May 2020 15:34
    1 Attachment(s)
    • Replies: 1
    • Views: 896
    vGoodtimes
    7th May 2020, 03:12 Go to last post

  24. Error: Identifier "ODDRE1" does not identify a component declaration.

    Started by Cesar0182, 5th May 2020 17:18
    1 Attachment(s)
    • Replies: 3
    • Views: 930
    ads-ee
    5th May 2020, 18:10 Go to last post

  25. AXI arvalid signal issue

    Started by promach, 5th February 2020 04:23
    8 Pages •
    1 2 3 ... 8
    16 Attachment(s)
    • Replies: 148
    • Views: 9,386
    promach
    5th May 2020, 07:36 Go to last post

  26. Error while coding a 2 bit comparator code

    Started by Sujith_Raj, 4th May 2020 05:52
    • Replies: 2
    • Views: 955
    vGoodtimes
    5th May 2020, 02:15 Go to last post

  27. Artix7 XC7A100T BRAM Math

    Started by abimann, 19th April 2020 12:06
    • Replies: 8
    • Views: 801
    TrickyDicky
    4th May 2020, 16:14 Go to last post

  28. [SOLVED] comma in 'always' statements (Verilog HDL)

    Started by PGPPG, 29th April 2020 08:18
    1 Attachment(s)
    • Replies: 3
    • Views: 1,062
    FvM
    29th April 2020, 10:36 Go to last post

  29. [moved] Xilinx Ethernet Interface

    Started by princez, 19th April 2020 22:12
    • Replies: 3
    • Views: 587
    vGoodtimes
    29th April 2020, 03:34 Go to last post

  30. Switching between more Bit-streams in single FPGA

    Started by Mai89, 27th April 2020 16:59
    • Replies: 3
    • Views: 460
    dpaul
    28th April 2020, 11:13 Go to last post
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