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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 25,789
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,995
    21st March 2007, 21:21 Go to last post
    • Replies: 0
    • Views: 8
    Today, 10:39 Go to last post
  1. Speed of RC Servo VHDL code

    Started by prakash_kadri, Today 06:12
    • Replies: 2
    • Views: 93
    Today, 09:45 Go to last post
  2. [SOLVED] Reed solomon encoder in vhdl

    Started by Saurabhmale, Yesterday 14:15
    • Replies: 4
    • Views: 140
    Yesterday, 18:27 Go to last post
  3. Verilog shifter synthesis in Design Compiler

    Started by oAwad, Yesterday 00:39
    • Replies: 2
    • Views: 136
    Yesterday, 01:54 Go to last post
  4. Unknown formal identifier in VHDL

    Started by sarmadmahmood969, 16th February 2019 01:49
    • Replies: 5
    • Views: 176
    16th February 2019, 15:48 Go to last post
  5. Where to find Altera PLDShell v5.0 Software

    Started by laguna831, 16th February 2019 11:59
    • Replies: 0
    • Views: 54
    16th February 2019, 11:59 Go to last post
  6. Kintex & FPGA signal integrity for SERDES Signal

    Started by chamarnadh, 16th February 2019 09:14
    • Replies: 0
    • Views: 72
    16th February 2019, 09:14 Go to last post
    • Replies: 2
    • Views: 298
    14th February 2019, 09:21 Go to last post
  7. mutlplty verilog code does not multiply

    Started by promach, 9th February 2019 01:40
    • Replies: 12
    • Views: 598
    13th February 2019, 07:58 Go to last post
  8. [SOLVED] VHDL Counter FPGA Spartan-6

    Started by prakash_kadri, 4th February 2019 20:10
    • Replies: 8
    • Views: 733
    11th February 2019, 09:02 Go to last post
  9. USB multiplexer via FPGA

    Started by orso135, 10th February 2019 19:01
    • Replies: 1
    • Views: 144
    10th February 2019, 21:59 Go to last post
  10. Verification for VHDL keeping FPGA in mind

    Started by dpaul, 4th February 2019 12:33
    • Replies: 3
    • Views: 319
    6th February 2019, 10:32 Go to last post
  11. Order of Execution of taking "NOT" and multiplication

    Started by akh_power, 4th February 2019 01:19
    • Replies: 4
    • Views: 270
    4th February 2019, 10:12 Go to last post
  12. Couldn't find design package

    Started by ranayehya, 26th January 2019 13:48
    • Replies: 1
    • Views: 391
    3rd February 2019, 07:09 Go to last post
  13. FPGA neural network training

    Started by adwnis123, 28th January 2019 16:16
    • Replies: 13
    • Views: 887
    1st February 2019, 22:42 Go to last post
  14. [SOLVED] VHDL : Sine Wave Lookup Table Not Working

    Started by akh_power, 28th January 2019 13:25
    • Replies: 10
    • Views: 570
    31st January 2019, 17:01 Go to last post
  15. 2M multiplication method

    Started by promach, 29th January 2019 04:59
    • Replies: 2
    • Views: 354
    31st January 2019, 04:35 Go to last post
  16. Wallace Tree Multiplier Questions

    Started by promach, 25th January 2019 04:39
    • Replies: 1
    • Views: 221
    25th January 2019, 06:43 Go to last post
  17. LPC data transfer Method

    Started by beginner_EDA, 22nd January 2019 15:58
    • Replies: 12
    • Views: 594
    24th January 2019, 17:12 Go to last post
  18. [SOLVED] HPS-FPGA issues on Intel Cyclone V

    Started by Ironlord, 11th January 2019 13:10
    • Replies: 1
    • Views: 328
    24th January 2019, 11:57 Go to last post
  19. Using Verilog Tasks in VHDL Code

    Started by mertberkea, 23rd January 2019 08:40
    • Replies: 3
    • Views: 260
    23rd January 2019, 19:16 Go to last post
  20. Serial by Parallel Booth Multiplier

    Started by promach, 22nd January 2019 03:53
    • Replies: 8
    • Views: 402
    23rd January 2019, 12:03 Go to last post
  21. Mismatched pcie lanes ip core vs hardware.

    Started by wesleytaylor, 15th January 2019 10:59
    • Replies: 1
    • Views: 198
    23rd January 2019, 06:10 Go to last post
  22. Formal verification of mutiplier verilog code

    Started by promach, 17th January 2019 07:10
    • Replies: 7
    • Views: 685
    22nd January 2019, 06:56 Go to last post
  23. Unable to allocate all 2GB of DDR4_PL in ZCU106

    Started by msdarvishi, 21st January 2019 23:39
    • Replies: 0
    • Views: 160
    21st January 2019, 23:39 Go to last post
  24. [SOLVED] Simulation in questa

    Started by ranayehya, 16th January 2019 14:58
    • Replies: 1
    • Views: 254
    16th January 2019, 17:29 Go to last post
    • Replies: 1
    • Views: 248
    16th January 2019, 13:24 Go to last post
  25. Converting Verilog to VHDL

    Started by joniengr, 6th December 2018 11:45
    2 Pages
    1 2
    • Replies: 29
    • Views: 1,625
    15th January 2019, 16:48 Go to last post
    • Replies: 7
    • Views: 576
    15th January 2019, 09:24 Go to last post
  26. Spartan 6 - OSERDES2 to ODDR - Unroutable signals

    Started by pigtwo, 12th January 2019 17:22
    • Replies: 4
    • Views: 430
    13th January 2019, 23:28 Go to last post