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Threads 1 to 30 of 22519

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 25,826
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 31,030
    21st March 2007, 21:21 Go to last post
  1. Unfamiliar VHDL | operator

    Started by shaiko, Today 03:50
    • Replies: 1
    • Views: 66
    Today, 08:52 Go to last post
  2. VHDL code flow in ISE Design Suite 14.7

    Started by prakash_kadri, 19th February 2019 08:40
    • Replies: 7
    • Views: 179
    Today, 01:18 Go to last post
  3. FPGA to HPS interrupts

    Started by Ironlord, 21st February 2019 12:49
    • Replies: 3
    • Views: 150
    Yesterday, 13:18 Go to last post
  4. Can a gated input clock be a problem for a design?

    Started by player80, 21st February 2019 10:06
    • Replies: 3
    • Views: 118
    Yesterday, 08:03 Go to last post
  5. Verilog Assignment with condition

    Started by beginner_EDA, 21st February 2019 10:25
    • Replies: 2
    • Views: 127
    21st February 2019, 19:44 Go to last post
    • Replies: 0
    • Views: 68
    21st February 2019, 06:21 Go to last post
  6. Troubles with latched counter

    Started by lbdcdrc, 18th February 2019 15:30
    • Replies: 18
    • Views: 396
    20th February 2019, 00:48 Go to last post
  7. Where to find Altera PLDShell v5.0 Software

    Started by laguna831, 16th February 2019 11:59
    • Replies: 4
    • Views: 174
    19th February 2019, 19:47 Go to last post
  8. [SOLVED] Help to translate verilog code lines to vhdl

    Started by Cesar0182, 18th February 2019 15:56
    • Replies: 9
    • Views: 187
    19th February 2019, 16:51 Go to last post
  9. Moved: Error: Indexed name is not to std_ulogic_vector

    Started by Cesar0182, 19th February 2019 15:22
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  10. FPGA neural network training

    Started by adwnis123, 28th January 2019 16:16
    • Replies: 14
    • Views: 954
    18th February 2019, 22:04 Go to last post
  11. How to begin development on SOC (xilinx)

    Started by tajiknomi, 18th February 2019 10:39
    • Replies: 3
    • Views: 137
    18th February 2019, 17:00 Go to last post
  12. [SOLVED] Reed solomon encoder in vhdl

    Started by Saurabhmale, 17th February 2019 14:15
    • Replies: 5
    • Views: 202
    18th February 2019, 16:53 Go to last post
  13. Kintex & FPGA signal integrity for SERDES Signal

    Started by chamarnadh, 16th February 2019 09:14
    • Replies: 1
    • Views: 115
    18th February 2019, 16:46 Go to last post
  14. Speed of RC Servo VHDL code

    Started by prakash_kadri, 18th February 2019 06:12
    • Replies: 3
    • Views: 163
    18th February 2019, 12:42 Go to last post
  15. Verilog shifter synthesis in Design Compiler

    Started by oAwad, 17th February 2019 00:39
    • Replies: 2
    • Views: 169
    17th February 2019, 01:54 Go to last post
  16. Unknown formal identifier in VHDL

    Started by sarmadmahmood969, 16th February 2019 01:49
    • Replies: 5
    • Views: 202
    16th February 2019, 15:48 Go to last post
    • Replies: 2
    • Views: 306
    14th February 2019, 09:21 Go to last post
  17. mutlplty verilog code does not multiply

    Started by promach, 9th February 2019 01:40
    • Replies: 12
    • Views: 638
    13th February 2019, 07:58 Go to last post
  18. [SOLVED] VHDL Counter FPGA Spartan-6

    Started by prakash_kadri, 4th February 2019 20:10
    • Replies: 8
    • Views: 751
    11th February 2019, 09:02 Go to last post
  19. USB multiplexer via FPGA

    Started by orso135, 10th February 2019 19:01
    • Replies: 1
    • Views: 153
    10th February 2019, 21:59 Go to last post
  20. Verification for VHDL keeping FPGA in mind

    Started by dpaul, 4th February 2019 12:33
    • Replies: 3
    • Views: 326
    6th February 2019, 10:32 Go to last post
  21. Order of Execution of taking "NOT" and multiplication

    Started by akh_power, 4th February 2019 01:19
    • Replies: 4
    • Views: 281
    4th February 2019, 10:12 Go to last post
  22. Couldn't find design package

    Started by ranayehya, 26th January 2019 13:48
    • Replies: 1
    • Views: 398
    3rd February 2019, 07:09 Go to last post
  23. [SOLVED] VHDL : Sine Wave Lookup Table Not Working

    Started by akh_power, 28th January 2019 13:25
    • Replies: 10
    • Views: 577
    31st January 2019, 17:01 Go to last post
  24. 2M multiplication method

    Started by promach, 29th January 2019 04:59
    • Replies: 2
    • Views: 358
    31st January 2019, 04:35 Go to last post
  25. Wallace Tree Multiplier Questions

    Started by promach, 25th January 2019 04:39
    • Replies: 1
    • Views: 225
    25th January 2019, 06:43 Go to last post
  26. LPC data transfer Method

    Started by beginner_EDA, 22nd January 2019 15:58
    • Replies: 12
    • Views: 625
    24th January 2019, 17:12 Go to last post
  27. [SOLVED] HPS-FPGA issues on Intel Cyclone V

    Started by Ironlord, 11th January 2019 13:10
    • Replies: 1
    • Views: 334
    24th January 2019, 11:57 Go to last post