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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,632
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,366
    21st March 2007, 21:21 Go to last post
  1. How to calculate log10(n) in Verilog

    Started by Poomagal, 11th June 2018 07:29
    • Replies: 14
    • Views: 415
    Today, 03:02 Go to last post
    • Replies: 6
    • Views: 265
    23rd June 2018, 07:23 Go to last post
    • Replies: 11
    • Views: 393
    22nd June 2018, 15:30 Go to last post
  2. selection of devboard for hobby project

    Started by theUltimateSource, 18th June 2018 16:37
    • Replies: 7
    • Views: 244
    21st June 2018, 15:22 Go to last post
    • Replies: 4
    • Views: 162
    20th June 2018, 07:16 Go to last post
  3. Verilog code for BCD to Floating point representation

    Started by adhul, 11th June 2018 07:32
    2 Pages
    1 2
    • Replies: 32
    • Views: 760
    20th June 2018, 06:30 Go to last post
  4. [SOLVED] Is there a way to change default programmer port?

    Started by Mohammad Amin Nili, 20th May 2018 23:22
    • Replies: 4
    • Views: 354
    18th June 2018, 11:44 Go to last post
  5. [moved] appropriate algorithm for video encryption

    Started by amin5659, 14th June 2018 17:45
    • Replies: 6
    • Views: 319
    16th June 2018, 07:51 Go to last post
  6. FPGA development Kit

    Started by alikhan968, 12th June 2018 19:26
    • Replies: 7
    • Views: 300
    14th June 2018, 09:17 Go to last post
  7. Build an Adder using VHDL

    Started by B21hasni, 12th June 2018 12:40
    • Replies: 10
    • Views: 345
    13th June 2018, 15:48 Go to last post
  8. [SOLVED] this code for interfacing ADC 122S101 is not working

    Started by adhul, 15th May 2018 07:44
    • Replies: 14
    • Views: 835
    13th June 2018, 10:23 Go to last post
  9. key scheduling present-80 vhdl cryptography

    Started by kumatul123, 12th June 2018 14:57
    • Replies: 2
    • Views: 116
    12th June 2018, 16:33 Go to last post
  10. Moved: Verilog code for BCD to Floating point representation

    Started by adhul, 12th June 2018 11:10
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  11. Help - ATM With VHDL (to store passwords)

    Started by OmegaRazr, 9th June 2018 05:25
    • Replies: 6
    • Views: 358
    12th June 2018, 07:05 Go to last post
  12. Implementing a computer vision algorithm on a FPGA

    Started by synths, 10th June 2018 04:18
    • Replies: 6
    • Views: 296
    11th June 2018, 13:48 Go to last post
    • Replies: 17
    • Views: 630
    10th June 2018, 14:44 Go to last post
    • Replies: 5
    • Views: 243
    9th June 2018, 00:55 Go to last post
    • Replies: 7
    • Views: 848
    8th June 2018, 15:26 Go to last post
  13. Hardware Utilization Efficiency

    Started by rafimiet, 6th June 2018 18:17
    • Replies: 1
    • Views: 125
    6th June 2018, 18:40 Go to last post
  14. Implemtation Mapper Error

    Started by sandhiyaselvaraj, 31st May 2018 05:55
    • Replies: 3
    • Views: 206
    5th June 2018, 14:09 Go to last post
  15. Mux exercise. Is it right?

    Started by Romadness, 30th May 2018 14:56
    • Replies: 16
    • Views: 905
    5th June 2018, 07:27 Go to last post
  16. [SOLVED] ModelSim tcl directory path

    Started by nsgil85, 4th June 2018 14:28
    • Replies: 2
    • Views: 187
    4th June 2018, 16:12 Go to last post
  17. Creating real-time data log of FPGA sensor readings

    Started by JaySeo, 14th May 2018 00:43
    • Replies: 5
    • Views: 408
    4th June 2018, 15:24 Go to last post
    • Replies: 1
    • Views: 203
    4th June 2018, 10:13 Go to last post