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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 27,869
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 32,815
    21st March 2007, 21:21 Go to last post
  1. SPI communication in SDK

    Started by Roronoa137, 13th September 2019 14:36
    • Replies: 9
    • Views: 548
    Yesterday, 02:05 Go to last post
  2. parameterized insertion of bits to data

    Started by rrucha, 18th September 2019 22:44
    • Replies: 10
    • Views: 347
    21st September 2019, 08:45 Go to last post
  3. Multiplexer output width depends on SELECT

    Started by rrucha, 13th September 2019 18:10
    • Replies: 17
    • Views: 638
    20th September 2019, 08:40 Go to last post
    • Replies: 2
    • Views: 162
    18th September 2019, 10:50 Go to last post
  4. [SOLVED] Need help creating Vivado Timing Constraint

    Started by wesleytaylor, 17th September 2019 12:27
    • Replies: 6
    • Views: 193
    17th September 2019, 18:05 Go to last post
  5. [SOLVED] Suppressing the spacing in $fwrite command of Verilog

    Started by tahirsengine, 17th September 2019 09:17
    • Replies: 3
    • Views: 164
    17th September 2019, 15:52 Go to last post
  6. PLDA drivers needed Windows x64

    Started by paradapa, 15th September 2019 12:24
    • Replies: 0
    • Views: 131
    15th September 2019, 12:24 Go to last post
    • Replies: 5
    • Views: 291
    14th September 2019, 06:53 Go to last post
  7. Using calculated CRC as seed for the next CRC calculation

    Started by rrucha, 12th September 2019 00:27
    • Replies: 4
    • Views: 294
    12th September 2019, 22:06 Go to last post
  8. [moved] VHDL of input capture and output compare

    Started by natalfra, 12th September 2019 14:51
    • Replies: 8
    • Views: 300
    12th September 2019, 21:58 Go to last post
    • Replies: 1
    • Views: 96
    12th September 2019, 21:19 Go to last post
    • Replies: 9
    • Views: 446
    12th September 2019, 18:12 Go to last post
  9. Unable to run the simulation correctly ( Modelsim )

    Started by bravo1234, 11th September 2019 08:44
    • Replies: 2
    • Views: 177
    11th September 2019, 16:16 Go to last post
    • Replies: 5
    • Views: 274
    11th September 2019, 12:00 Go to last post
  10. [SOLVED] VHDL scope vs visibility vs visibility by selection

    Started by wesleytaylor, 10th September 2019 09:23
    • Replies: 3
    • Views: 202
    10th September 2019, 16:16 Go to last post
  11. [SOLVED] problem with programming the xilinx fpga

    Started by hamidkavianathar, 25th August 2019 13:23
    • Replies: 4
    • Views: 790
    8th September 2019, 13:23 Go to last post
    • Replies: 2
    • Views: 383
    7th September 2019, 09:49 Go to last post
  12. CDC - How make merge data after conversion?

    Started by arkadyy, 5th September 2019 13:25
    • Replies: 10
    • Views: 538
    6th September 2019, 22:15 Go to last post
  13. Sine function generator (VHDL)

    Started by FlyingDutch, 11th August 2019 15:33
    • Replies: 6
    • Views: 657
    5th September 2019, 17:35 Go to last post
  14. Inferred VHDL dual port RAM template

    Started by shaiko, 30th August 2019 00:01
    • Replies: 7
    • Views: 533
    5th September 2019, 11:56 Go to last post
  15. ERROR:HDLParsers:709

    Started by abimann, 4th September 2019 08:05
    • Replies: 2
    • Views: 288
    4th September 2019, 09:04 Go to last post
  16. HELP ME the newbie with Verilog Code

    Started by ridhohrnf, 3rd September 2019 18:07
    • Replies: 3
    • Views: 251
    4th September 2019, 08:28 Go to last post
    • Replies: 12
    • Views: 1,140
    3rd September 2019, 15:48 Go to last post
  17. pcie hard ip altera- latency problem

    Started by manush30, 3rd September 2019 09:04
    • Replies: 3
    • Views: 405
    3rd September 2019, 13:26 Go to last post
  18. Switching between more bit-streams on FPGA

    Started by MSAKARIM, 29th August 2019 20:58
    • Replies: 2
    • Views: 524
    1st September 2019, 14:40 Go to last post
  19. [SOLVED] VHDL: reading text file stops at endfile()

    Started by igaco, 30th August 2019 22:25
    • Replies: 3
    • Views: 371
    31st August 2019, 11:46 Go to last post
  20. Req: Bluspec Systemverilog good learning materials

    Started by Zerox100, 27th August 2019 11:49
    • Replies: 1
    • Views: 310
    30th August 2019, 18:12 Go to last post
  21. Shifting control from one module to another iteratively

    Started by rrucha, 28th August 2019 22:56
    • Replies: 8
    • Views: 566
    30th August 2019, 09:11 Go to last post
  22. SystemVerilog Input generation

    Started by rrucha, 27th August 2019 19:41
    • Replies: 13
    • Views: 700
    30th August 2019, 09:01 Go to last post
  23. Transferring data from PS to PL

    Started by Roronoa137, 19th August 2019 09:48
    • Replies: 8
    • Views: 625
    29th August 2019, 08:18 Go to last post