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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 26,391
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 31,492
    21st March 2007, 21:21 Go to last post
    • Replies: 5
    • Views: 179
    Yesterday, 17:49 Go to last post
  1. ZCU111 Ultrascale+ RFSoC board

    Started by chyrie, 17th April 2019 14:33
    • Replies: 2
    • Views: 121
    Yesterday, 10:10 Go to last post
  2. 8 Bit Matrix Multiplication in Verilog

    Started by Shanks100, 16th April 2019 12:24
    • Replies: 2
    • Views: 258
    Yesterday, 06:50 Go to last post
  3. FATAL_ERROR: Vivado Simulator

    Started by MSAKARIM, 5th April 2019 16:15
    • Replies: 7
    • Views: 374
    16th April 2019, 16:45 Go to last post
  4. Link Training with IO DELAY

    Started by beginner_EDA, 12th April 2019 10:22
    • Replies: 4
    • Views: 351
    16th April 2019, 08:24 Go to last post
  5. Inheritance in HDL languages

    Started by FlyingDutch, 13th April 2019 09:00
    • Replies: 7
    • Views: 630
    15th April 2019, 21:44 Go to last post
    • Replies: 2
    • Views: 328
    13th April 2019, 16:07 Go to last post
  6. How to use a termination resistor?

    Started by Ironlord, 12th April 2019 08:36
    • Replies: 4
    • Views: 170
    12th April 2019, 10:29 Go to last post
  7. XOR Vs NOT in layout comparison

    Started by skthebatman, 10th April 2019 12:18
    • Replies: 2
    • Views: 343
    11th April 2019, 07:25 Go to last post
  8. HDMI in and out , just connected in to out.

    Started by abimann, 10th April 2019 12:01
    • Replies: 2
    • Views: 154
    10th April 2019, 16:35 Go to last post
  9. FPGA neural network training estimation time

    Started by adwnis123, 8th April 2019 11:57
    • Replies: 6
    • Views: 757
    10th April 2019, 13:00 Go to last post
  10. Parking lot occupancy counter State Diagram

    Started by eengr, 5th April 2019 11:26
    • Replies: 10
    • Views: 928
    9th April 2019, 10:41 Go to last post
  11. Fixed point multiplication in Verilog

    Started by krishvamsi, 7th April 2019 14:21
    • Replies: 6
    • Views: 532
    7th April 2019, 18:53 Go to last post
  12. [moved] verilog code of a neural network

    Started by krishvamsi, 3rd April 2019 11:48
    • Replies: 6
    • Views: 766
    4th April 2019, 12:26 Go to last post
  13. [SOLVED] Quartus and fixed point

    Started by Ironlord, 2nd April 2019 09:24
    • Replies: 13
    • Views: 1,508
    3rd April 2019, 11:33 Go to last post
  14. [SOLVED] Time multiplexing with LED

    Started by eengr, 29th March 2019 18:41
    • Replies: 4
    • Views: 528
    2nd April 2019, 20:58 Go to last post
    • Replies: 5
    • Views: 399
    2nd April 2019, 15:43 Go to last post
    • Replies: 8
    • Views: 508
    1st April 2019, 11:16 Go to last post
  15. Pipelining 32 Bit Multiplier in Verilog

    Started by AlinParcalab, 27th March 2019 17:04
    • Replies: 9
    • Views: 948
    1st April 2019, 09:35 Go to last post
    • Replies: 18
    • Views: 2,272
    1st April 2019, 08:08 Go to last post
  16. Buffer backpressure for on-off flow control

    Started by promach, 1st April 2019 04:58
    • Replies: 0
    • Views: 203
    1st April 2019, 04:58 Go to last post
  17. Stochastic rounding for floating point

    Started by oAwad, 31st March 2019 00:19
    • Replies: 3
    • Views: 488
    31st March 2019, 20:49 Go to last post
  18. Need USB3 FTDI or cypress HDL code

    Started by jalalba, 30th March 2019 09:44
    • Replies: 1
    • Views: 171
    31st March 2019, 07:57 Go to last post
  19. RGMII problem with MAX 10 Development board

    Started by Humusk, 28th March 2019 19:08
    • Replies: 4
    • Views: 412
    29th March 2019, 13:19 Go to last post
    • Replies: 2
    • Views: 334
    28th March 2019, 14:36 Go to last post
  20. Parent signal when alias is accessed

    Started by shaiko, 26th March 2019 20:20
    • Replies: 7
    • Views: 937
    27th March 2019, 08:38 Go to last post
  21. Color sensor and Basys3 with VHDL

    Started by kmesne, 18th March 2019 19:18
    • Replies: 5
    • Views: 744
    26th March 2019, 17:42 Go to last post
  22. Moved: TCS34725 Basys3 VHDL

    Started by kmesne, 26th March 2019 15:38
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  23. Verilog code to find modular inverse value

    Started by Poomagal, 21st March 2019 08:09
    • Replies: 7
    • Views: 788
    26th March 2019, 09:30 Go to last post
  24. [SOLVED] VHDL coding Status register read problem

    Started by eengr, 15th March 2019 18:35
    • Replies: 6
    • Views: 1,471
    25th March 2019, 15:13 Go to last post