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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,984
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,577
    21st March 2007, 21:21 Go to last post
    • Replies: 2
    • Views: 227
    23rd September 2018, 22:57 Go to last post
  1. [Verilog] Modelsim problem of enum in simulation

    Started by sqx, 21st September 2018 05:14
    • Replies: 3
    • Views: 118
    23rd September 2018, 21:09 Go to last post
  2. FPGA Operating system

    Started by adwnis123, 8th September 2018 21:01
    2 Pages
    1 2
    • Replies: 20
    • Views: 688
    23rd September 2018, 04:12 Go to last post
  3. Quartus / Prime floor planning / atoms to obtain best fMax

    Started by Wiljan, 21st September 2018 09:15
    • Replies: 6
    • Views: 199
    22nd September 2018, 09:53 Go to last post
  4. reorder queue mechanism

    Started by promach, 18th September 2018 04:33
    • Replies: 7
    • Views: 305
    22nd September 2018, 06:05 Go to last post
    • Replies: 5
    • Views: 213
    21st September 2018, 19:59 Go to last post
    • Replies: 2
    • Views: 139
    21st September 2018, 16:12 Go to last post
    • Replies: 0
    • Views: 56
    21st September 2018, 12:54 Go to last post
  5. Large FPGA with logic only

    Started by sythe, 19th September 2018 09:22
    • Replies: 5
    • Views: 177
    20th September 2018, 11:58 Go to last post
  6. [SOLVED] Conversion of std_logic to integer in VHDL

    Started by tahirsengine, 19th September 2018 09:22
    • Replies: 2
    • Views: 167
    19th September 2018, 13:18 Go to last post
    • Replies: 10
    • Views: 277
    19th September 2018, 10:10 Go to last post
  7. [SOLVED] VIVADO .SRCS folder disappeared, even in new projects

    Started by tahirsengine, 17th September 2018 15:52
    • Replies: 2
    • Views: 168
    18th September 2018, 09:06 Go to last post
  8. Working with sparten 3e starter board

    Started by ranayehya, 2nd September 2018 13:28
    • Replies: 17
    • Views: 593
    17th September 2018, 22:27 Go to last post
  9. Registers in FPGA fabric

    Started by tahirsengine, 6th September 2018 11:39
    • Replies: 12
    • Views: 515
    17th September 2018, 15:00 Go to last post
  10. different voltages in IO Differencial ports

    Started by abimann, 16th September 2018 06:08
    • Replies: 2
    • Views: 210
    17th September 2018, 12:54 Go to last post
    • Replies: 2
    • Views: 170
    17th September 2018, 11:16 Go to last post
  11. ODDR VS ODDR2 I use Virtex-4

    Started by abimann, 15th September 2018 14:39
    • Replies: 1
    • Views: 135
    15th September 2018, 17:44 Go to last post
  12. Difference between the two coding styles for clock gating

    Started by rahdirs, 12th September 2018 15:28
    • Replies: 2
    • Views: 209
    14th September 2018, 19:35 Go to last post
  13. Pipeline valid and ready signals semantic meaning

    Started by promach, 13th September 2018 09:19
    • Replies: 4
    • Views: 243
    14th September 2018, 16:16 Go to last post
  14. Is there any good source of learning VHDL-2008?

    Started by tahirsengine, 13th September 2018 07:42
    • Replies: 2
    • Views: 220
    13th September 2018, 17:10 Go to last post
  15. Clock Gaters Tree -> routing conjection

    Started by ivlsi, 9th September 2018 00:49
    • Replies: 8
    • Views: 423
    10th September 2018, 17:59 Go to last post
  16. Coefficients of Type-3 Digital PLL

    Started by promach, 9th September 2018 03:59
    • Replies: 0
    • Views: 148
    9th September 2018, 03:59 Go to last post
    • Replies: 2
    • Views: 127
    8th September 2018, 20:57 Go to last post
  17. [SOLVED] infer RAM with mlab or m10k

    Started by nsgil85, 29th August 2018 12:55
    • Replies: 2
    • Views: 166
    8th September 2018, 20:39 Go to last post
  18. Calling VHDL code in Verilog Code

    Started by manjunath_crl, 7th September 2018 08:17
    • Replies: 4
    • Views: 250
    8th September 2018, 14:00 Go to last post