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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 28,100
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 33,027
    21st March 2007, 21:21 Go to last post
    • Replies: 7
    • Views: 366
    Yesterday, 16:56 Go to last post
  1. LTSSM state of PCIe and USR_LNK_UP assertion

    Started by vishnuk, 12th October 2019 11:38
    • Replies: 0
    • Views: 233
    12th October 2019, 11:38 Go to last post
  2. [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Started by yashjain, 2nd October 2019 15:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 863
    12th October 2019, 07:32 Go to last post
  3. Implementation of ADC

    Started by student21, 10th October 2019 11:07
    • Replies: 8
    • Views: 556
    11th October 2019, 21:39 Go to last post
  4. parameterized MUX implementation

    Started by rrucha, 9th October 2019 00:18
    • Replies: 3
    • Views: 199
    11th October 2019, 20:13 Go to last post
    • Replies: 11
    • Views: 518
    11th October 2019, 16:01 Go to last post
  5. Moved: Implemetation of ADC

    Started by student21, 10th October 2019 22:20
    •  
    •  
    • Replies: 14
    • Views: 554
    10th October 2019, 09:19 Go to last post
  6. Netlist Verilog to RTL or structrual to behavioral

    Started by s002wjhw, 9th October 2019 16:14
    • Replies: 0
    • Views: 110
    9th October 2019, 16:14 Go to last post
  7. Clock Skew problem in oserdes

    Started by beginner_EDA, 8th October 2019 15:31
    • Replies: 1
    • Views: 177
    9th October 2019, 12:23 Go to last post
    • Replies: 4
    • Views: 240
    7th October 2019, 23:12 Go to last post
    • Replies: 2
    • Views: 219
    5th October 2019, 10:14 Go to last post
  8. Testbench input stimulus

    Started by rogger201, 30th September 2019 19:14
    • Replies: 3
    • Views: 316
    4th October 2019, 22:45 Go to last post
    • Replies: 14
    • Views: 579
    4th October 2019, 18:48 Go to last post
  9. Help!! with MUX and Shift Registers in an architecture

    Started by Mai89, 29th September 2019 19:18
    • Replies: 3
    • Views: 252
    4th October 2019, 15:55 Go to last post
    • Replies: 3
    • Views: 315
    4th October 2019, 05:42 Go to last post
  10. Difference between TRN and AXI4-Stream

    Started by buenos, 3rd October 2019 21:37
    • Replies: 2
    • Views: 242
    3rd October 2019, 23:37 Go to last post
    • Replies: 14
    • Views: 657
    3rd October 2019, 19:30 Go to last post
  11. Data string length to be send out from FPGA

    Started by Vlad., 2nd October 2019 10:44
    • Replies: 4
    • Views: 290
    2nd October 2019, 17:03 Go to last post
    • Replies: 8
    • Views: 494
    2nd October 2019, 09:49 Go to last post
  12. Ternary Content Addressable memory

    Started by Sisirapk, 1st October 2019 06:49
    • Replies: 2
    • Views: 136
    1st October 2019, 07:42 Go to last post
  13. Simulation about 30MHz -> 1Hz clock divider

    Started by Xilinx_Modelsim, 28th September 2019 08:57
    • Replies: 10
    • Views: 449
    30th September 2019, 23:08 Go to last post
  14. How to declare a variable number of parameters

    Started by pbernardi, 28th September 2019 05:23
    • Replies: 7
    • Views: 391
    30th September 2019, 18:33 Go to last post
  15. UNKNOWN BYPASS problem

    Started by hamidkavianathar, 28th September 2019 15:27
    • Replies: 10
    • Views: 477
    30th September 2019, 08:57 Go to last post
  16. UART TX signalling from another process

    Started by vinodstanur, 29th September 2019 18:07
    • Replies: 1
    • Views: 153
    29th September 2019, 21:19 Go to last post
  17. Help to make use of an .h file in my vhdl code

    Started by Cesar0182, 26th September 2019 17:01
    • Replies: 13
    • Views: 521
    27th September 2019, 21:59 Go to last post
  18. 10 millisecond counter with different frequencies

    Started by tahirsengine, 27th September 2019 08:36
    • Replies: 3
    • Views: 189
    27th September 2019, 09:37 Go to last post
  19. [SOLVED] if else statement inside an always block

    Started by rogger201, 26th September 2019 21:22
    • Replies: 3
    • Views: 198
    26th September 2019, 23:12 Go to last post
  20. Nexys 4 DDR Board UART ERROR

    Started by AvaTRm, 26th September 2019 07:29
    • Replies: 2
    • Views: 193
    26th September 2019, 20:44 Go to last post