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Threads 1 to 30 of 22775

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 28,360
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 33,259
    21st March 2007, 21:21 Go to last post
  1. readback the firmware Cyclone IV

    Started by Zerox100, 20th October 2019 12:24
    • Replies: 18
    • Views: 1,188
    Yesterday, 18:30 Go to last post
  2. Data Transfer over long rwisted pair cable

    Started by Port Map, 28th October 2019 13:09
    • Replies: 14
    • Views: 825
    Yesterday, 12:26 Go to last post
    • Replies: 1
    • Views: 236
    12th November 2019, 13:09 Go to last post
  3. Fast Arbiters for On-Chip Network Switches

    Started by promach, 9th November 2019 13:18
    • Replies: 0
    • Views: 219
    9th November 2019, 13:18 Go to last post
  4. Learn cryptography/emcryption in VHDL

    Started by sonika111, 6th November 2019 17:50
    • Replies: 1
    • Views: 251
    9th November 2019, 03:32 Go to last post
  5. Remote Flash Programming

    Started by marlapraveen, 7th November 2019 14:07
    • Replies: 0
    • Views: 139
    7th November 2019, 14:07 Go to last post
  6. Moved: SD Card Identification

    Started by Sujeer, 6th November 2019 05:19
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  7. vhdl problem debug help please

    Started by sonika111, 5th November 2019 16:15
    • Replies: 6
    • Views: 253
    5th November 2019, 16:58 Go to last post
  8. Logic duplication and optimization

    Started by shaiko, 3rd November 2019 02:13
    • Replies: 7
    • Views: 481
    5th November 2019, 11:14 Go to last post
    • Replies: 8
    • Views: 405
    1st November 2019, 21:12 Go to last post
  9. AXI4 VHDL BFM Options

    Started by ptkinzer, 24th October 2019 13:32
    • Replies: 10
    • Views: 621
    1st November 2019, 15:22 Go to last post
  10. Timing constraints using a PLL.

    Started by Pastel, 30th October 2019 02:12
    • Replies: 4
    • Views: 346
    30th October 2019, 17:42 Go to last post
    • Replies: 4
    • Views: 274
    29th October 2019, 16:38 Go to last post
  11. FPGA program has some hard to trace glitches

    Started by Saltwater, 22nd October 2019 12:59
    • Replies: 18
    • Views: 824
    29th October 2019, 11:35 Go to last post
  12. Error (10028): Can't resolve multiple constant drivers

    Started by Pastel, 28th October 2019 09:37
    • Replies: 5
    • Views: 354
    29th October 2019, 09:14 Go to last post
  13. Reduce Net delay in FPGA synthesis?

    Started by Zerox100, 28th October 2019 15:29
    • Replies: 6
    • Views: 288
    28th October 2019, 23:02 Go to last post
    • Replies: 2
    • Views: 248
    23rd October 2019, 23:50 Go to last post
    • Replies: 2
    • Views: 234
    23rd October 2019, 06:45 Go to last post
  14. help please tosimulate this file

    Started by michael 1978, 21st October 2019 19:53
    • Replies: 6
    • Views: 509
    22nd October 2019, 21:17 Go to last post
    • Replies: 4
    • Views: 325
    21st October 2019, 22:48 Go to last post
  15. Open source RGMII Phy core for xilinx microblaze

    Started by aminpix, 21st October 2019 05:38
    • Replies: 0
    • Views: 212
    21st October 2019, 05:38 Go to last post
    • Replies: 5
    • Views: 587
    18th October 2019, 18:48 Go to last post
  16. Miller Decoder State machine

    Started by ejleiss, 17th October 2019 18:43
    • Replies: 0
    • Views: 232
    17th October 2019, 18:43 Go to last post
    • Replies: 2
    • Views: 323
    17th October 2019, 08:38 Go to last post
  17. Hardware implementation of problem

    Started by rrucha, 15th October 2019 17:27
    • Replies: 3
    • Views: 294
    16th October 2019, 01:06 Go to last post
    • Replies: 6
    • Views: 616
    15th October 2019, 17:47 Go to last post
    • Replies: 7
    • Views: 593
    14th October 2019, 16:56 Go to last post
  18. LTSSM state of PCIe and USR_LNK_UP assertion

    Started by vishnuk, 12th October 2019 11:38
    • Replies: 0
    • Views: 346
    12th October 2019, 11:38 Go to last post