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Threads 1 to 30 of 22714

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 27,811
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 32,767
    21st March 2007, 21:21 Go to last post
  1. SPI communication in SDK

    Started by Roronoa137, 13th September 2019 14:36
    • Replies: 6
    • Views: 326
    Today, 13:03 Go to last post
  2. PLDA drivers needed Windows x64

    Started by paradapa, 15th September 2019 12:24
    • Replies: 0
    • Views: 107
    15th September 2019, 12:24 Go to last post
  3. Multiplexer output width depends on SELECT

    Started by rrucha, 13th September 2019 18:10
    • Replies: 7
    • Views: 322
    14th September 2019, 12:53 Go to last post
    • Replies: 5
    • Views: 252
    14th September 2019, 06:53 Go to last post
  4. Using calculated CRC as seed for the next CRC calculation

    Started by rrucha, 12th September 2019 00:27
    • Replies: 4
    • Views: 268
    12th September 2019, 22:06 Go to last post
  5. [moved] VHDL of input capture and output compare

    Started by natalfra, 12th September 2019 14:51
    • Replies: 8
    • Views: 272
    12th September 2019, 21:58 Go to last post
    • Replies: 1
    • Views: 79
    12th September 2019, 21:19 Go to last post
    • Replies: 9
    • Views: 368
    12th September 2019, 18:12 Go to last post
  6. Unable to run the simulation correctly ( Modelsim )

    Started by bravo1234, 11th September 2019 08:44
    • Replies: 2
    • Views: 154
    11th September 2019, 16:16 Go to last post
    • Replies: 5
    • Views: 245
    11th September 2019, 12:00 Go to last post
  7. [SOLVED] VHDL scope vs visibility vs visibility by selection

    Started by wesleytaylor, 10th September 2019 09:23
    • Replies: 3
    • Views: 182
    10th September 2019, 16:16 Go to last post
  8. [SOLVED] problem with programming the xilinx fpga

    Started by hamidkavianathar, 25th August 2019 13:23
    • Replies: 4
    • Views: 771
    8th September 2019, 13:23 Go to last post
    • Replies: 2
    • Views: 363
    7th September 2019, 09:49 Go to last post
  9. CDC - How make merge data after conversion?

    Started by arkadyy, 5th September 2019 13:25
    • Replies: 10
    • Views: 514
    6th September 2019, 22:15 Go to last post
  10. Sine function generator (VHDL)

    Started by FlyingDutch, 11th August 2019 15:33
    • Replies: 6
    • Views: 632
    5th September 2019, 17:35 Go to last post
  11. Inferred VHDL dual port RAM template

    Started by shaiko, 30th August 2019 00:01
    • Replies: 7
    • Views: 502
    5th September 2019, 11:56 Go to last post
  12. ERROR:HDLParsers:709

    Started by abimann, 4th September 2019 08:05
    • Replies: 2
    • Views: 272
    4th September 2019, 09:04 Go to last post
  13. HELP ME the newbie with Verilog Code

    Started by ridhohrnf, 3rd September 2019 18:07
    • Replies: 3
    • Views: 236
    4th September 2019, 08:28 Go to last post
    • Replies: 12
    • Views: 1,089
    3rd September 2019, 15:48 Go to last post
  14. pcie hard ip altera- latency problem

    Started by manush30, 3rd September 2019 09:04
    • Replies: 3
    • Views: 384
    3rd September 2019, 13:26 Go to last post
  15. Switching between more bit-streams on FPGA

    Started by MSAKARIM, 29th August 2019 20:58
    • Replies: 2
    • Views: 507
    1st September 2019, 14:40 Go to last post
  16. [SOLVED] VHDL: reading text file stops at endfile()

    Started by igaco, 30th August 2019 22:25
    • Replies: 3
    • Views: 351
    31st August 2019, 11:46 Go to last post
  17. Req: Bluspec Systemverilog good learning materials

    Started by Zerox100, 27th August 2019 11:49
    • Replies: 1
    • Views: 300
    30th August 2019, 18:12 Go to last post
  18. Shifting control from one module to another iteratively

    Started by rrucha, 28th August 2019 22:56
    • Replies: 8
    • Views: 541
    30th August 2019, 09:11 Go to last post
  19. SystemVerilog Input generation

    Started by rrucha, 27th August 2019 19:41
    • Replies: 13
    • Views: 655
    30th August 2019, 09:01 Go to last post
  20. Transferring data from PS to PL

    Started by Roronoa137, 19th August 2019 09:48
    • Replies: 8
    • Views: 594
    29th August 2019, 08:18 Go to last post
  21. Lattice FPGAs and Diamond software

    Started by Amadeus, 22nd August 2019 13:37
    • Replies: 5
    • Views: 573
    23rd August 2019, 07:59 Go to last post