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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 28,574
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 33,459
    21st March 2007, 21:21 Go to last post
  1. fastest multiplication alghorithms

    Started by Zerox100, 2nd December 2019 14:51
    • Replies: 13
    • Views: 579
    6th December 2019, 03:59 Go to last post
    • Replies: 9
    • Views: 459
    5th December 2019, 15:24 Go to last post
  2. Verilator width warnings

    Started by promach, 3rd December 2019 06:37
    • Replies: 3
    • Views: 285
    4th December 2019, 17:00 Go to last post
  3. Multiplication in vhdl

    Started by sonika111, 3rd December 2019 15:10
    • Replies: 1
    • Views: 177
    3rd December 2019, 16:02 Go to last post
  4. QMTECH Xilinx FPGA Artix7 Artix-7 Development Board

    Started by FlyingDutch, 29th November 2019 17:30
    • Replies: 5
    • Views: 374
    2nd December 2019, 14:52 Go to last post
    • Replies: 6
    • Views: 264
    28th November 2019, 16:55 Go to last post
  5. Solve Equations Verilog

    Started by Chinmaye, 28th November 2019 07:05
    • Replies: 2
    • Views: 226
    28th November 2019, 15:02 Go to last post
  6. Simple Problem of Systemverilog

    Started by Holzapfel, 28th November 2019 00:02
    • Replies: 2
    • Views: 182
    28th November 2019, 10:38 Go to last post
  7. filter unwanted signal keeping fast RMS settling time

    Started by franticEB, 24th November 2019 20:12
    • Replies: 3
    • Views: 380
    24th November 2019, 23:32 Go to last post
    • Replies: 5
    • Views: 388
    24th November 2019, 18:57 Go to last post
  8. Design a system clock monitor in verilog

    Started by bravo1234, 19th November 2019 12:11
    • Replies: 3
    • Views: 392
    20th November 2019, 12:23 Go to last post
  9. Assigning a null array in VHDL

    Started by shaiko, 19th November 2019 14:17
    • Replies: 7
    • Views: 442
    20th November 2019, 08:42 Go to last post
  10. Zynq QSPI Flash - Program it without Vivado SDK

    Started by Medea, 18th November 2019 10:39
    • Replies: 0
    • Views: 209
    18th November 2019, 10:39 Go to last post
  11. Data Transfer over long rwisted pair cable

    Started by Port Map, 28th October 2019 13:09
    • Replies: 15
    • Views: 1,252
    16th November 2019, 10:36 Go to last post
  12. readback the firmware Cyclone IV

    Started by Zerox100, 20th October 2019 12:24
    2 Pages
    1 2
    • Replies: 21
    • Views: 1,643
    16th November 2019, 08:37 Go to last post
    • Replies: 1
    • Views: 371
    12th November 2019, 13:09 Go to last post
  13. Fast Arbiters for On-Chip Network Switches

    Started by promach, 9th November 2019 13:18
    • Replies: 0
    • Views: 279
    9th November 2019, 13:18 Go to last post
  14. Learn cryptography/emcryption in VHDL

    Started by sonika111, 6th November 2019 17:50
    • Replies: 1
    • Views: 330
    9th November 2019, 03:32 Go to last post
  15. Remote Flash Programming

    Started by marlapraveen, 7th November 2019 14:07
    • Replies: 0
    • Views: 184
    7th November 2019, 14:07 Go to last post
  16. vhdl problem debug help please

    Started by sonika111, 5th November 2019 16:15
    • Replies: 6
    • Views: 374
    5th November 2019, 16:58 Go to last post
  17. Logic duplication and optimization

    Started by shaiko, 3rd November 2019 02:13
    • Replies: 7
    • Views: 612
    5th November 2019, 11:14 Go to last post
    • Replies: 8
    • Views: 561
    1st November 2019, 21:12 Go to last post
  18. AXI4 VHDL BFM Options

    Started by ptkinzer, 24th October 2019 13:32
    • Replies: 10
    • Views: 813
    1st November 2019, 15:22 Go to last post
  19. Timing constraints using a PLL.

    Started by Pastel, 30th October 2019 02:12
    • Replies: 4
    • Views: 455
    30th October 2019, 17:42 Go to last post
    • Replies: 4
    • Views: 369
    29th October 2019, 16:38 Go to last post
  20. FPGA program has some hard to trace glitches

    Started by Saltwater, 22nd October 2019 12:59
    • Replies: 18
    • Views: 1,047
    29th October 2019, 11:35 Go to last post
  21. Error (10028): Can't resolve multiple constant drivers

    Started by Pastel, 28th October 2019 09:37
    • Replies: 5
    • Views: 533
    29th October 2019, 09:14 Go to last post
  22. Reduce Net delay in FPGA synthesis?

    Started by Zerox100, 28th October 2019 15:29
    • Replies: 6
    • Views: 398
    28th October 2019, 23:02 Go to last post