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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,606
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,343
    21st March 2007, 21:21 Go to last post
  1. Verilog code for BCD to Floating point representation

    Started by adhul, 11th June 2018 07:32
    2 Pages
    1 2
    • Replies: 29
    • Views: 619
    Today, 09:29 Go to last post
    • Replies: 3
    • Views: 84
    Yesterday, 18:43 Go to last post
  2. [SOLVED] Is there a way to change default programmer port?

    Started by Mohammad Amin Nili, 20th May 2018 23:22
    • Replies: 4
    • Views: 329
    Yesterday, 11:44 Go to last post
  3. How to calculate log10(n) in Verilog

    Started by Poomagal, 11th June 2018 07:29
    • Replies: 13
    • Views: 319
    Yesterday, 09:03 Go to last post
  4. [moved] appropriate algorithm for video encryption

    Started by amin5659, 14th June 2018 17:45
    • Replies: 6
    • Views: 269
    16th June 2018, 07:51 Go to last post
  5. FPGA development Kit

    Started by alikhan968, 12th June 2018 19:26
    • Replies: 7
    • Views: 250
    14th June 2018, 09:17 Go to last post
  6. Build an Adder using VHDL

    Started by B21hasni, 12th June 2018 12:40
    • Replies: 10
    • Views: 296
    13th June 2018, 15:48 Go to last post
    • Replies: 14
    • Views: 777
    13th June 2018, 10:23 Go to last post
  7. key scheduling present-80 vhdl cryptography

    Started by kumatul123, 12th June 2018 14:57
    • Replies: 2
    • Views: 96
    12th June 2018, 16:33 Go to last post
  8. Moved: Verilog code for BCD to Floating point representation

    Started by adhul, 12th June 2018 11:10
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  9. Help - ATM With VHDL (to store passwords)

    Started by OmegaRazr, 9th June 2018 05:25
    • Replies: 6
    • Views: 326
    12th June 2018, 07:05 Go to last post
  10. Implementing a computer vision algorithm on a FPGA

    Started by synths, 10th June 2018 04:18
    • Replies: 6
    • Views: 272
    11th June 2018, 13:48 Go to last post
    • Replies: 17
    • Views: 572
    10th June 2018, 14:44 Go to last post
    • Replies: 5
    • Views: 217
    9th June 2018, 00:55 Go to last post
    • Replies: 7
    • Views: 810
    8th June 2018, 15:26 Go to last post
  11. Hardware Utilization Efficiency

    Started by rafimiet, 6th June 2018 18:17
    • Replies: 1
    • Views: 113
    6th June 2018, 18:40 Go to last post
  12. Implemtation Mapper Error

    Started by sandhiyaselvaraj, 31st May 2018 05:55
    • Replies: 3
    • Views: 188
    5th June 2018, 14:09 Go to last post
  13. Mux exercise. Is it right?

    Started by Romadness, 30th May 2018 14:56
    • Replies: 16
    • Views: 810
    5th June 2018, 07:27 Go to last post
  14. [SOLVED] ModelSim tcl directory path

    Started by nsgil85, 4th June 2018 14:28
    • Replies: 2
    • Views: 173
    4th June 2018, 16:12 Go to last post
  15. Creating real-time data log of FPGA sensor readings

    Started by JaySeo, 14th May 2018 00:43
    • Replies: 5
    • Views: 381
    4th June 2018, 15:24 Go to last post
    • Replies: 1
    • Views: 186
    4th June 2018, 10:13 Go to last post
  16. PL to PS interrupt:how to acess in arm processor

    Started by dipin, 31st May 2018 14:08
    • Replies: 3
    • Views: 244
    4th June 2018, 08:47 Go to last post
  17. Bidirectional overhead arrays

    Started by Saltwater, 27th May 2018 13:30
    • Replies: 18
    • Views: 768
    31st May 2018, 14:33 Go to last post
    • Replies: 0
    • Views: 104
    31st May 2018, 10:02 Go to last post