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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 25,244
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,716
    21st March 2007, 21:21 Go to last post
  1. reorder queue mechanism

    Started by promach, 18th September 2018 04:33
    • Replies: 10
    • Views: 716
    Yesterday, 09:10 Go to last post
  2. FPGA ALM or LAB estimated size

    Started by PablodlR, 29th October 2018 13:14
    • Replies: 6
    • Views: 342
    Yesterday, 07:26 Go to last post
  3. Verilog Synchronize with External Signal

    Started by groover, 18th November 2018 21:44
    • Replies: 4
    • Views: 194
    Yesterday, 00:36 Go to last post
    • Replies: 0
    • Views: 86
    19th November 2018, 17:00 Go to last post
    • Replies: 4
    • Views: 205
    18th November 2018, 01:19 Go to last post
  4. clocking issues in capturing debug signals in ILA

    Started by Alauddin123, 15th November 2018 06:57
    • Replies: 2
    • Views: 210
    17th November 2018, 01:02 Go to last post
  5. ZYNQ - XADC example ZedBoard or ZYBO

    Started by joniengr, 15th November 2018 16:42
    • Replies: 1
    • Views: 151
    16th November 2018, 10:38 Go to last post
  6. Tracking 'X' in the gate lavel simulation

    Started by filip.amator, 10th November 2018 11:32
    • Replies: 5
    • Views: 247
    14th November 2018, 18:11 Go to last post
  7. Implement I2C in VHDL

    Started by Ironlord, 16th October 2018 07:47
    3 Pages
    1 2 3
    • Replies: 43
    • Views: 1,481
    14th November 2018, 10:42 Go to last post
  8. Design of a PCIe card with USB and Ethernet

    Started by HasHx, 7th November 2018 19:29
    • Replies: 7
    • Views: 503
    14th November 2018, 05:59 Go to last post
  9. [SOLVED] VHDL Aliases advanced usecase of name signment

    Started by wesleytaylor, 6th November 2018 18:01
    • Replies: 6
    • Views: 281
    9th November 2018, 20:00 Go to last post
  10. Initial value depending on the input

    Started by bremenpl, 8th November 2018 08:53
    • Replies: 10
    • Views: 419
    9th November 2018, 09:03 Go to last post
  11. SPI verilog testbench code

    Started by promach, 21st October 2018 16:30
    • Replies: 6
    • Views: 502
    9th November 2018, 04:54 Go to last post
  12. FPGA Module with 12 bit ADC

    Started by joniengr, 8th November 2018 11:34
    • Replies: 5
    • Views: 241
    8th November 2018, 15:45 Go to last post
    • Replies: 2
    • Views: 168
    8th November 2018, 09:31 Go to last post
    • Replies: 1
    • Views: 143
    8th November 2018, 09:01 Go to last post
  13. Entity and component with the same name in VHDL

    Started by shaiko, 6th November 2018 19:19
    • Replies: 5
    • Views: 215
    7th November 2018, 22:04 Go to last post
  14. Started by mehdimolu, 6th November 2018 16:32
    • Replies: 1
    • Views: 180
    7th November 2018, 00:23 Go to last post
    • Replies: 8
    • Views: 421
    6th November 2018, 23:21 Go to last post
    • Replies: 13
    • Views: 415
    6th November 2018, 19:41 Go to last post
  15. [SOLVED] FPGA coding style behavioral vs structural modeling

    Started by eengr, 29th October 2018 12:37
    2 Pages
    1 2
    • Replies: 24
    • Views: 894
    6th November 2018, 14:28 Go to last post
    • Replies: 11
    • Views: 648
    6th November 2018, 01:16 Go to last post
  16. Number of configuration bits used by design in Vivado

    Started by msdarvishi, 5th November 2018 22:22
    • Replies: 1
    • Views: 141
    5th November 2018, 23:40 Go to last post
    • Replies: 3
    • Views: 264
    5th November 2018, 17:06 Go to last post
  17. Lattice MachXO2 EFB library can't not found

    Started by robin0338, 5th November 2018 07:17
    • Replies: 0
    • Views: 95
    5th November 2018, 07:17 Go to last post
    • Replies: 5
    • Views: 362
    3rd November 2018, 22:23 Go to last post
  18. system verilog for loop in always_ff question

    Started by ravichandar, 2nd November 2018 06:58
    • Replies: 3
    • Views: 310
    2nd November 2018, 23:52 Go to last post
  19. generating Pure tone Using Codec IC

    Started by kiransbaddi, 30th October 2018 08:00
    • Replies: 4
    • Views: 255
    30th October 2018, 16:21 Go to last post
    • Replies: 9
    • Views: 504
    29th October 2018, 14:55 Go to last post
  20. What define an Electronic Engineer?

    Started by TheXeno, 17th October 2018 23:57
    • Replies: 12
    • Views: 636
    28th October 2018, 20:43 Go to last post