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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,866
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,500
    21st March 2007, 21:21 Go to last post
  1. Video codec IC selection

    Started by kiransbaddi, 19th August 2018 12:10
    • Replies: 1
    • Views: 89
    Today, 20:20 Go to last post
  2. Support for "Jagged" array in modern HDLs

    Started by shaiko, Yesterday 22:32
    • Replies: 12
    • Views: 227
    Today, 20:15 Go to last post
  3. [SOLVED] Using Xilinx fft core

    Started by Radhikamkr, 23rd July 2018 05:26
    • Replies: 8
    • Views: 413
    Today, 17:49 Go to last post
  4. record issue with quartus 15.1

    Started by nsgil85, Today 15:31
    • Replies: 1
    • Views: 43
    Today, 16:00 Go to last post
    • Replies: 6
    • Views: 89
    Today, 15:15 Go to last post
  5. while condition in verilog

    Started by jasmine123, Yesterday 08:41
    • Replies: 2
    • Views: 127
    Yesterday, 15:27 Go to last post
    • Replies: 1
    • Views: 183
    Yesterday, 14:04 Go to last post
  6. [SOLVED] std_logic conversion

    Started by nsgil85, 19th August 2018 13:10
    • Replies: 9
    • Views: 231
    19th August 2018, 18:31 Go to last post
  7. Code Coverage and Functional Coverage

    Started by M.Mata, 10th August 2018 19:50
    • Replies: 5
    • Views: 388
    18th August 2018, 22:19 Go to last post
  8. HDL vs Software Mentalities

    Started by redsees, 15th August 2018 15:58
    2 Pages
    1 2
    • Replies: 21
    • Views: 637
    18th August 2018, 01:05 Go to last post
    • Replies: 2
    • Views: 114
    16th August 2018, 20:32 Go to last post
  9. Closed: FPGA to eMMC clk frequency & adjustable sampling point

    Started by wesleytaylor, 1st November 2017 11:49
    • Replies: 1
    • Views: 670
    14th August 2018, 15:49 Go to last post
  10. Moved: Bus sampling tuning concept

    Started by wesleytaylor, 14th August 2018 16:51
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    •  
    • Replies: 5
    • Views: 169
    14th August 2018, 14:11 Go to last post
  11. Problems in the I2C master

    Started by PablodlR, 8th August 2018 11:32
    • Replies: 9
    • Views: 389
    13th August 2018, 14:51 Go to last post
  12. Weird synthesis error (Xilinx, Verilog)

    Started by dayana42200, 13th August 2018 01:58
    • Replies: 4
    • Views: 303
    13th August 2018, 09:58 Go to last post
  13. In-Circuit Emulators

    Started by M.Mata, 10th August 2018 19:37
    • Replies: 1
    • Views: 109
    10th August 2018, 20:54 Go to last post
  14. ISE xc2c64a, 2 output, phase.

    Started by victor910, 7th August 2018 04:22
    2 Pages
    1 2
    • Replies: 30
    • Views: 789
    10th August 2018, 09:50 Go to last post
  15. how to calculate exponential (fixpoint) in fpga?

    Started by jalal.baba, 9th August 2018 10:46
    • Replies: 6
    • Views: 229
    9th August 2018, 16:07 Go to last post
  16. How to do fractional downsampling using Lagrange?

    Started by bravoegg, 9th August 2018 08:19
    • Replies: 1
    • Views: 114
    9th August 2018, 13:14 Go to last post
  17. Xilinx fft core output not proper

    Started by Radhikamkr, 8th August 2018 11:07
    • Replies: 1
    • Views: 114
    8th August 2018, 13:56 Go to last post
  18. Multiplication of float/real value in VHDL

    Started by arunprasadvr3, 8th August 2018 08:59
    • Replies: 8
    • Views: 233
    8th August 2018, 11:00 Go to last post
    • Replies: 6
    • Views: 405
    7th August 2018, 11:01 Go to last post
  19. Problem understanding System Verilog

    Started by redtomato11, 1st July 2018 21:38
    • Replies: 3
    • Views: 382
    7th August 2018, 04:51 Go to last post
  20. Xilinix to Quartus "Library Conversion"

    Started by UmarKhayyam, 26th July 2018 15:13
    • Replies: 1
    • Views: 180
    5th August 2018, 13:46 Go to last post
  21. register settings for BMP280

    Started by abimann, 4th August 2018 10:22
    • Replies: 1
    • Views: 164
    4th August 2018, 10:56 Go to last post