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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 25,048
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,627
    21st March 2007, 21:21 Go to last post
  1. Implement I2C in VHDL

    Started by Ironlord, Yesterday 07:47
    • Replies: 6
    • Views: 115
    Yesterday, 13:21 Go to last post
    • Replies: 1
    • Views: 91
    15th October 2018, 22:25 Go to last post
  2. What is wrong with this Mux code using indexing?

    Started by fouwad, 13th October 2018 22:39
    • Replies: 3
    • Views: 208
    14th October 2018, 07:32 Go to last post
    • Replies: 7
    • Views: 362
    12th October 2018, 15:23 Go to last post
  3. [SOLVED] Design an RTL for different FPGA types compliance

    Started by Mohammad Amin Nili, 10th October 2018 10:17
    • Replies: 4
    • Views: 182
    10th October 2018, 23:52 Go to last post
    • Replies: 8
    • Views: 291
    10th October 2018, 22:17 Go to last post
    • Replies: 0
    • Views: 213
    7th October 2018, 04:16 Go to last post
    • Replies: 4
    • Views: 319
    6th October 2018, 16:20 Go to last post
  4. exponential operator in verilog

    Started by ssrk1050, 4th October 2018 09:52
    • Replies: 11
    • Views: 455
    5th October 2018, 23:14 Go to last post
  5. Warning in Vivado Design Suite during synthesis

    Started by Radhikamkr, 27th August 2018 23:22
    • Replies: 4
    • Views: 457
    3rd October 2018, 17:17 Go to last post
    • Replies: 1
    • Views: 174
    2nd October 2018, 00:05 Go to last post
    • Replies: 7
    • Views: 322
    1st October 2018, 23:22 Go to last post
  6. RIFFA full duplex and multi-threading support

    Started by promach, 7th July 2018 10:16
    • Replies: 15
    • Views: 1,404
    1st October 2018, 11:59 Go to last post
  7. Vivado Combinational Loop DRC

    Started by mselmanerel, 30th September 2018 18:27
    • Replies: 2
    • Views: 137
    30th September 2018, 22:18 Go to last post
    • Replies: 4
    • Views: 254
    29th September 2018, 18:59 Go to last post
  8. Converting a RF signal into baseband using VHDL

    Started by mertberkea, 27th September 2018 09:06
    • Replies: 3
    • Views: 252
    28th September 2018, 16:59 Go to last post
  9. Dual flop synchronizers and mtbf

    Started by Alauddin123, 28th September 2018 11:17
    • Replies: 2
    • Views: 173
    28th September 2018, 14:12 Go to last post
  10. [SOLVED] Comparing ASIC gate-equivalent with Xilinx FPGA LUTs

    Started by dpaul, 27th September 2018 14:42
    • Replies: 4
    • Views: 220
    27th September 2018, 19:38 Go to last post
  11. VHDL substitute text to simplify code.

    Started by buenos, 26th September 2018 02:05
    • Replies: 4
    • Views: 252
    27th September 2018, 08:32 Go to last post
    • Replies: 2
    • Views: 191
    24th September 2018, 22:40 Go to last post
    • Replies: 1
    • Views: 202
    24th September 2018, 13:26 Go to last post
    • Replies: 2
    • Views: 295
    23rd September 2018, 22:57 Go to last post
  12. [Verilog] Modelsim problem of enum in simulation

    Started by sqx, 21st September 2018 05:14
    • Replies: 3
    • Views: 199
    23rd September 2018, 21:09 Go to last post
  13. FPGA Operating system

    Started by adwnis123, 8th September 2018 21:01
    2 Pages
    1 2
    • Replies: 20
    • Views: 954
    23rd September 2018, 04:12 Go to last post
  14. Quartus / Prime floor planning / atoms to obtain best fMax

    Started by Wiljan, 21st September 2018 09:15
    • Replies: 6
    • Views: 293
    22nd September 2018, 09:53 Go to last post
  15. reorder queue mechanism

    Started by promach, 18th September 2018 04:33
    • Replies: 7
    • Views: 434
    22nd September 2018, 06:05 Go to last post
    • Replies: 5
    • Views: 311
    21st September 2018, 19:59 Go to last post
    • Replies: 2
    • Views: 199
    21st September 2018, 16:12 Go to last post