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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 26,979
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 32,045
    21st March 2007, 21:21 Go to last post
  1. OV7670 camera interface with Digilent SPARTAN 3E

    Started by adwnis123, 19th June 2019 11:48
    • Replies: 9
    • Views: 290
    Yesterday, 22:58 Go to last post
  2. Run python on cyclone 5 soc

    Started by dipin, 20th June 2019 07:50
    • Replies: 3
    • Views: 177
    20th June 2019, 18:39 Go to last post
  3. OpenCL vs VHDL running in FPGA

    Started by adwnis123, 20th June 2019 13:47
    • Replies: 1
    • Views: 156
    20th June 2019, 17:15 Go to last post
  4. verilog set parameter to a module

    Started by beginner_EDA, 20th June 2019 13:12
    • Replies: 1
    • Views: 81
    20th June 2019, 15:55 Go to last post
  5. Use of CPLD/FPGA for a newbie's laser project

    Started by MichelM, 20th June 2019 09:39
    • Replies: 3
    • Views: 152
    20th June 2019, 12:37 Go to last post
  6. Display lcd text from Fpga1 to Fpga2 via USB cable

    Started by crb, 18th June 2019 13:58
    • Replies: 7
    • Views: 217
    19th June 2019, 06:56 Go to last post
  7. Import chipscopes data to matlab

    Started by amin5659, 17th June 2019 13:29
    • Replies: 7
    • Views: 261
    18th June 2019, 15:27 Go to last post
  8. [SOLVED] Verilog read-file task, unexpected behaviour

    Started by wesleytaylor, 17th June 2019 10:32
    • Replies: 1
    • Views: 133
    17th June 2019, 16:46 Go to last post
  9. Not enough IOB of a certain FPGA

    Started by MSAKARIM, 16th June 2019 16:00
    • Replies: 9
    • Views: 344
    17th June 2019, 09:48 Go to last post
  10. Vivado Timing Constraint

    Started by Mai89, 16th June 2019 10:57
    • Replies: 2
    • Views: 132
    17th June 2019, 09:44 Go to last post
  11. Active-HDL VHDL simulation problem

    Started by ashueda, 8th June 2019 06:46
    • Replies: 11
    • Views: 561
    16th June 2019, 19:36 Go to last post
    • Replies: 5
    • Views: 287
    15th June 2019, 23:16 Go to last post
    • Replies: 13
    • Views: 679
    13th June 2019, 22:06 Go to last post
    • Replies: 0
    • Views: 139
    13th June 2019, 08:53 Go to last post
  12. Interfacing 16*2 LCD with DE0_nano

    Started by vsnarkhede13, 12th June 2019 11:32
    • Replies: 2
    • Views: 182
    13th June 2019, 07:12 Go to last post
    • Replies: 6
    • Views: 321
    7th June 2019, 09:03 Go to last post
  13. [SOLVED] for generate with step other than one

    Started by Mai89, 6th June 2019 19:25
    • Replies: 3
    • Views: 230
    7th June 2019, 02:32 Go to last post
  14. Unknown xx req signal for NoC coding

    Started by promach, 29th May 2019 08:13
    • Replies: 6
    • Views: 815
    6th June 2019, 07:46 Go to last post
  15. [SOLVED] How to interpret a .RPD file to write image in FPGA Flash Memory

    Started by Humusk, 4th June 2019 18:30
    • Replies: 6
    • Views: 530
    5th June 2019, 14:51 Go to last post
  16. Connecting a SPDT switch to I/O pin of a CPLD

    Started by garvind25, 4th June 2019 17:24
    • Replies: 9
    • Views: 369
    5th June 2019, 13:32 Go to last post
  17. Best Benchmark for mobile processors

    Started by Zerox100, 3rd June 2019 12:55
    • Replies: 0
    • Views: 159
    3rd June 2019, 12:55 Go to last post
  18. Need some help-PwmAudio in VHDL

    Started by yuly330, 31st May 2019 21:44
    • Replies: 1
    • Views: 454
    31st May 2019, 23:26 Go to last post
  19. HC05 UART Communication Data Rate

    Started by matriX_1500, 28th May 2019 13:16
    • Replies: 7
    • Views: 538
    29th May 2019, 15:57 Go to last post
  20. FPGA ASIC gate count

    Started by Hithaishi, 28th May 2019 06:13
    • Replies: 3
    • Views: 283
    28th May 2019, 18:16 Go to last post
    • Replies: 15
    • Views: 838
    27th May 2019, 23:31 Go to last post