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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 31,622
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 36,956
    21st March 2007, 21:21 Go to last post
  1. VHDL: Default Record for generic type

    Started by _MW_, 3rd April 2020 10:50
    • Replies: 7
    • Views: 244
    Yesterday, 16:46 Go to last post
    • Replies: 17
    • Views: 1,333
    Yesterday, 10:13 Go to last post
  2. Generating a digital pulse of 10 secs and 1 sec

    Started by garvind25, 3rd April 2020 21:22
    • Replies: 2
    • Views: 134
    3rd April 2020, 22:18 Go to last post
    • Replies: 9
    • Views: 558
    2nd April 2020, 12:41 Go to last post
  3. AXI arvalid signal issue

    Started by promach, 5th February 2020 04:23
    7 Pages
    1 2 3 ... 7
    • Replies: 125
    • Views: 5,529
    1st April 2020, 09:31 Go to last post
  4. Error :Syntax error near "module"

    Started by abimann, 25th March 2020 21:01
    • Replies: 13
    • Views: 741
    30th March 2020, 15:57 Go to last post
    • Replies: 25
    • Views: 3,191
    27th March 2020, 10:02 Go to last post
  5. [SOLVED] VHDL FIFO Implementation

    Started by chandlerbing65nm, 25th March 2020 21:02
    • Replies: 3
    • Views: 334
    26th March 2020, 21:19 Go to last post
  6. [SOLVED] Delay time calculation

    Started by chandlerbing65nm, 23rd March 2020 23:17
    • Replies: 7
    • Views: 431
    26th March 2020, 15:35 Go to last post
    • Replies: 5
    • Views: 365
    26th March 2020, 00:54 Go to last post
  7. [SOLVED] 128 x 32 single port RAM VHDL code problem

    Started by chandlerbing65nm, 24th March 2020 20:06
    • Replies: 6
    • Views: 382
    25th March 2020, 09:33 Go to last post
  8. A Code issue in Verilog

    Started by tahirsengine, 24th March 2020 11:30
    • Replies: 3
    • Views: 333
    24th March 2020, 15:04 Go to last post
  9. [SOLVED] Adding '1' to a std_logic_vector in VHDL

    Started by chandlerbing65nm, 23rd March 2020 16:54
    • Replies: 7
    • Views: 477
    24th March 2020, 14:18 Go to last post
  10. GSM/GPRS, GPS, RTC-DS3231, SD-Card

    Started by Wajiduddaim, 19th March 2020 09:10
    • Replies: 0
    • Views: 177
    19th March 2020, 09:10 Go to last post
  11. [SOLVED] Using 2 push buttons to light LEDs

    Started by chandlerbing65nm, 16th March 2020 16:46
    • Replies: 4
    • Views: 350
    17th March 2020, 16:45 Go to last post
  12. Data rate between components connected through AXI

    Started by sirnef, 16th March 2020 11:22
    • Replies: 3
    • Views: 358
    16th March 2020, 14:33 Go to last post
  13. Fast Arbiters for On-Chip Network Switches

    Started by promach, 9th November 2019 13:18
    • Replies: 1
    • Views: 1,222
    13th March 2020, 04:32 Go to last post
  14. [SOLVED] problem moving from SLL to shift_left in ISE 14.5

    Started by Cesar0182, 4th March 2020 22:43
    • Replies: 3
    • Views: 378
    10th March 2020, 16:42 Go to last post
  15. [SOLVED] Verilog alarm clock time advancing not working correctly ..

    Started by techy5025, 3rd March 2020 03:16
    • Replies: 6
    • Views: 453
    4th March 2020, 17:41 Go to last post
  16. [SOLVED] Problema para crear coregen en ISE 14.5

    Started by Cesar0182, 28th February 2020 17:10
    • Replies: 4
    • Views: 403
    4th March 2020, 16:09 Go to last post
  17. Buying an old FPGA board

    Started by tahirsengine, 3rd March 2020 08:48
    • Replies: 2
    • Views: 323
    3rd March 2020, 10:27 Go to last post
  18. Sending AT commands using FPGA

    Started by PrashanthKK, 3rd March 2020 07:30
    • Replies: 3
    • Views: 275
    3rd March 2020, 08:17 Go to last post
  19. UART Problem on CPLD c-m240 board

    Started by reservevoltage, 27th February 2020 14:54
    • Replies: 3
    • Views: 374
    28th February 2020, 17:35 Go to last post
  20. The difference between | operator and keyword or

    Started by tahirsengine, 26th February 2020 10:04
    • Replies: 4
    • Views: 515
    27th February 2020, 09:01 Go to last post
  21. [SOLVED] Stopping a countdown timer from 9-0.

    Started by chandlerbing65nm, 25th February 2020 19:37
    • Replies: 2
    • Views: 469
    27th February 2020, 03:23 Go to last post
  22. [SOLVED] Random Led Blinker on DE10-lite FPGA board: [0-7]LED

    Started by chandlerbing65nm, 24th February 2020 22:28
    • Replies: 3
    • Views: 433
    25th February 2020, 19:32 Go to last post
  23. [moved] External Ethernet Microcontroller or ZYNQ

    Started by joniengr, 20th February 2020 15:55
    • Replies: 5
    • Views: 596
    25th February 2020, 17:57 Go to last post
  24. how to generate 4MHz clock from 2 MHz clock.

    Started by ankit rajput, 13th February 2020 11:39
    • Replies: 19
    • Views: 1,752
    25th February 2020, 09:03 Go to last post