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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 25,327
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,764
    21st March 2007, 21:21 Go to last post
  1. [SOLVED] Verilog Interview Question

    Started by rahdirs, 6th December 2018 23:06
    • Replies: 4
    • Views: 318
    Yesterday, 23:34 Go to last post
  2. Converting Verilog to VHDL

    Started by joniengr, 6th December 2018 11:45
    • Replies: 11
    • Views: 412
    Yesterday, 15:51 Go to last post
    • Replies: 4
    • Views: 350
    12th December 2018, 09:29 Go to last post
  3. Xilinx XPower Analyzer Confidence Level

    Started by dayana42200, 10th December 2018 02:38
    • Replies: 4
    • Views: 284
    12th December 2018, 00:09 Go to last post
  4. Fixed point complex numbers in sdSOC

    Started by Radhikamkr, 10th December 2018 13:34
    • Replies: 0
    • Views: 146
    10th December 2018, 13:34 Go to last post
  5. Design a 4-core processor on FPGA

    Started by adwnis123, 7th December 2018 15:11
    • Replies: 9
    • Views: 407
    8th December 2018, 18:02 Go to last post
  6. Why Quarus Prime is uninstalled after restart a Windows?

    Started by frdm90, 5th December 2018 16:40
    • Replies: 4
    • Views: 182
    6th December 2018, 17:01 Go to last post
  7. Generating SAIF file

    Started by dayana42200, 3rd December 2018 02:43
    • Replies: 7
    • Views: 342
    6th December 2018, 01:43 Go to last post
  8. USB Softcore for FPGA

    Started by promach, 1st December 2018 05:29
    • Replies: 4
    • Views: 324
    5th December 2018, 09:11 Go to last post
  9. PLS explain how to make BRAM

    Started by abimann, 2nd December 2018 07:00
    • Replies: 9
    • Views: 347
    4th December 2018, 21:33 Go to last post
    • Replies: 4
    • Views: 171
    4th December 2018, 18:03 Go to last post
  10. VHDL unconstrained array in VCS

    Started by shaiko, 4th December 2018 13:13
    • Replies: 2
    • Views: 127
    4th December 2018, 14:31 Go to last post
  11. Spartan-6 Servo Control

    Started by prakash_kadri, 28th November 2018 12:04
    • Replies: 6
    • Views: 385
    30th November 2018, 02:54 Go to last post
  12. Best Way to Implement Shared RAM

    Started by groover, 26th November 2018 21:46
    2 Pages
    1 2
    • Replies: 25
    • Views: 653
    29th November 2018, 23:17 Go to last post
  13. Propper clock generation for SPI protocol

    Started by Ironlord, 27th November 2018 13:05
    • Replies: 14
    • Views: 438
    29th November 2018, 13:24 Go to last post
  14. Using different time units in Verilog simulation

    Started by shaiko, 25th November 2018 00:09
    • Replies: 2
    • Views: 256
    26th November 2018, 16:52 Go to last post
  15. [SOLVED] Instantiating module with inout

    Started by ranayehya, 26th November 2018 08:03
    • Replies: 4
    • Views: 196
    26th November 2018, 15:23 Go to last post
  16. Definitions for a Memory in Verilog

    Started by groover, 25th November 2018 20:49
    • Replies: 0
    • Views: 202
    25th November 2018, 20:49 Go to last post
    • Replies: 2
    • Views: 162
    25th November 2018, 20:40 Go to last post
  17. System Verilog - default type of a declared variable

    Started by shaiko, 24th November 2018 18:53
    • Replies: 7
    • Views: 312
    25th November 2018, 15:39 Go to last post
  18. Parameter location in a Verilog Module

    Started by shaiko, 24th November 2018 20:12
    • Replies: 1
    • Views: 145
    24th November 2018, 20:28 Go to last post
  19. Verilog & System Verilog - port sizing by inheritance

    Started by shaiko, 24th November 2018 13:43
    • Replies: 1
    • Views: 152
    24th November 2018, 15:48 Go to last post
  20. Implement I2C in VHDL

    Started by Ironlord, 16th October 2018 07:47
    3 Pages
    1 2 3
    • Replies: 55
    • Views: 2,199
    23rd November 2018, 13:02 Go to last post
    • Replies: 3
    • Views: 174
    22nd November 2018, 21:16 Go to last post
  21. reorder queue mechanism

    Started by promach, 18th September 2018 04:33
    • Replies: 10
    • Views: 891
    20th November 2018, 09:10 Go to last post
  22. FPGA ALM or LAB estimated size

    Started by PablodlR, 29th October 2018 13:14
    • Replies: 6
    • Views: 474
    20th November 2018, 07:26 Go to last post
  23. Verilog Synchronize with External Signal

    Started by groover, 18th November 2018 21:44
    • Replies: 4
    • Views: 314
    20th November 2018, 00:36 Go to last post
    • Replies: 4
    • Views: 304
    18th November 2018, 01:19 Go to last post