1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    121,794
Page 1 of 757 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 22687

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 27,533
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 32,520
    21st March 2007, 21:21 Go to last post
  1. Lattice FPGAs and Diamond software

    Started by Amadeus, Yesterday 13:37
    • Replies: 4
    • Views: 119
    Today, 00:29 Go to last post
  2. Real time voice encryption/decryption with FPGA

    Started by adwnis123, 20th August 2019 19:51
    • Replies: 6
    • Views: 286
    Yesterday, 03:11 Go to last post
    • Replies: 5
    • Views: 250
    21st August 2019, 08:42 Go to last post
  3. Introductory literature on PLD

    Started by MikhailFrolov, 20th August 2019 18:51
    • Replies: 4
    • Views: 102
    20th August 2019, 20:52 Go to last post
  4. Transferring data from PS to PL

    Started by Roronoa137, 19th August 2019 09:48
    • Replies: 6
    • Views: 216
    19th August 2019, 13:46 Go to last post
  5. How to write in the log file

    Started by Roronoa137, 8th August 2019 07:56
    • Replies: 4
    • Views: 200
    19th August 2019, 09:31 Go to last post
  6. Verilog code for 8 bit register with read/write

    Started by muku383, 14th August 2019 09:54
    • Replies: 6
    • Views: 427
    17th August 2019, 00:29 Go to last post
  7. $urandom for error insertion in Systemverilog

    Started by rrucha, 15th August 2019 21:30
    • Replies: 5
    • Views: 261
    16th August 2019, 19:53 Go to last post
  8. [SOLVED] Comparator gives wrong Output

    Started by padfoot_1729, 16th August 2019 17:45
    • Replies: 1
    • Views: 147
    16th August 2019, 18:02 Go to last post
  9. verilog code using vivado

    Started by sumag, 16th August 2019 08:54
    • Replies: 3
    • Views: 162
    16th August 2019, 15:32 Go to last post
  10. SystemVerilog Assertions into ModelSim

    Started by Fynjisx, 16th August 2019 08:25
    • Replies: 1
    • Views: 123
    16th August 2019, 12:15 Go to last post
  11. [SOLVED] Modelsim clock signal

    Started by maro.pitti, 13th August 2019 18:48
    • Replies: 10
    • Views: 413
    15th August 2019, 17:51 Go to last post
  12. Strategy for a multi signal generator using a MAX10

    Started by Pastel, 11th August 2019 04:05
    • Replies: 10
    • Views: 479
    15th August 2019, 16:45 Go to last post
  13. Embedded Linux Application

    Started by ranayehya, 14th August 2019 19:09
    • Replies: 2
    • Views: 197
    15th August 2019, 08:05 Go to last post
  14. JESD204B with two different device clocks

    Started by kangalooj, 14th August 2019 22:42
    • Replies: 0
    • Views: 98
    14th August 2019, 22:42 Go to last post
  15. Error in Parity bits of Hamming Code

    Started by rrucha, 8th August 2019 21:43
    • Replies: 19
    • Views: 577
    13th August 2019, 19:18 Go to last post
  16. [SOLVED] Failing to program ALTERA Max 7000A

    Started by andrew_que, 9th August 2019 21:55
    2 Pages
    1 2
    • Replies: 23
    • Views: 696
    13th August 2019, 18:45 Go to last post
    • Replies: 3
    • Views: 226
    12th August 2019, 19:02 Go to last post
  17. Sine function generator (VHDL)

    Started by FlyingDutch, 11th August 2019 15:33
    • Replies: 5
    • Views: 294
    11th August 2019, 18:57 Go to last post
  18. Bayer Pattern to RGB VHDL CODE

    Started by abimann, 5th August 2019 09:50
    • Replies: 1
    • Views: 202
    11th August 2019, 11:04 Go to last post
  19. How to instantiate a submodule in Verilog

    Started by Pastel, 2nd August 2019 08:40
    2 Pages
    1 2
    • Replies: 36
    • Views: 1,239
    10th August 2019, 11:08 Go to last post
  20. verilog code needed for my sequence

    Started by Bosechandran, 8th August 2019 07:14
    • Replies: 5
    • Views: 259
    9th August 2019, 21:07 Go to last post
  21. Injecting errors in SystemVerilog

    Started by rrucha, 6th August 2019 17:42
    • Replies: 2
    • Views: 179
    7th August 2019, 07:08 Go to last post
  22. Verilog: read 2 values from an array at the same time.

    Started by Pastel, 3rd August 2019 07:23
    • Replies: 10
    • Views: 533
    4th August 2019, 12:41 Go to last post
  23. Difference between ByteBlaster and FPGA JTAG

    Started by eric33, 2nd August 2019 18:48
    • Replies: 1
    • Views: 212
    3rd August 2019, 12:11 Go to last post
  24. UART Transmitter by FPGA

    Started by huytergan, 2nd August 2019 19:52
    • Replies: 5
    • Views: 300
    3rd August 2019, 10:15 Go to last post
  25. [SOLVED] testbench display for CRC code

    Started by rrucha, 24th July 2019 19:25
    • Replies: 17
    • Views: 1,009
    2nd August 2019, 21:48 Go to last post
    • Replies: 1
    • Views: 268
    1st August 2019, 15:32 Go to last post
  26. How to compare variables name

    Started by Roronoa137, 26th July 2019 10:43
    • Replies: 6
    • Views: 649
    30th July 2019, 15:54 Go to last post