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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 26,883
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 31,956
    21st March 2007, 21:21 Go to last post
  1. Vivado Timing Constraint

    Started by Mai89, Today 10:57
    • Replies: 0
    • Views: 6
    Today, 10:57 Go to last post
    • Replies: 5
    • Views: 161
    Yesterday, 23:16 Go to last post
  2. Active-HDL VHDL simulation problem

    Started by ashueda, 8th June 2019 06:46
    • Replies: 10
    • Views: 383
    Yesterday, 03:32 Go to last post
  3. Moved: CYPRESS FXLP & WVGA SENSOR in Snapshot Mode

    Started by adityamflow, 14th June 2019 12:47
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    • Replies: 13
    • Views: 497
    13th June 2019, 22:06 Go to last post
    • Replies: 0
    • Views: 87
    13th June 2019, 08:53 Go to last post
  4. Interfacing 16*2 LCD with DE0_nano

    Started by vsnarkhede13, 12th June 2019 11:32
    • Replies: 2
    • Views: 127
    13th June 2019, 07:12 Go to last post
    • Replies: 6
    • Views: 210
    7th June 2019, 09:03 Go to last post
  5. [SOLVED] for generate with step other than one

    Started by Mai89, 6th June 2019 19:25
    • Replies: 3
    • Views: 170
    7th June 2019, 02:32 Go to last post
  6. Unknown xx req signal for NoC coding

    Started by promach, 29th May 2019 08:13
    • Replies: 6
    • Views: 727
    6th June 2019, 07:46 Go to last post
  7. [SOLVED] How to interpret a .RPD file to write image in FPGA Flash Memory

    Started by Humusk, 4th June 2019 18:30
    • Replies: 6
    • Views: 440
    5th June 2019, 14:51 Go to last post
  8. Connecting a SPDT switch to I/O pin of a CPLD

    Started by garvind25, 4th June 2019 17:24
    • Replies: 9
    • Views: 247
    5th June 2019, 13:32 Go to last post
  9. Best Benchmark for mobile processors

    Started by Zerox100, 3rd June 2019 12:55
    • Replies: 0
    • Views: 135
    3rd June 2019, 12:55 Go to last post
  10. Need some help-PwmAudio in VHDL

    Started by yuly330, 31st May 2019 21:44
    • Replies: 1
    • Views: 421
    31st May 2019, 23:26 Go to last post
  11. HC05 UART Communication Data Rate

    Started by matriX_1500, 28th May 2019 13:16
    • Replies: 7
    • Views: 448
    29th May 2019, 15:57 Go to last post
  12. FPGA ASIC gate count

    Started by Hithaishi, 28th May 2019 06:13
    • Replies: 3
    • Views: 230
    28th May 2019, 18:16 Go to last post
    • Replies: 15
    • Views: 682
    27th May 2019, 23:31 Go to last post
  13. [SOLVED] Problem with UART clock value in a VHDL sample code

    Started by matriX_1500, 26th May 2019 12:10
    • Replies: 9
    • Views: 653
    26th May 2019, 20:26 Go to last post
  14. kintex 7 bpi programming error

    Started by shand_12, 23rd May 2019 12:13
    • Replies: 1
    • Views: 452
    24th May 2019, 00:13 Go to last post
    • Replies: 6
    • Views: 887
    22nd May 2019, 01:47 Go to last post
  15. VHDL code for 74hc4094

    Started by sa007jbond, 19th May 2019 12:55
    • Replies: 2
    • Views: 313
    21st May 2019, 08:10 Go to last post
  16. rem and mod operators

    Started by mahmood.n, 18th May 2019 07:59
    • Replies: 10
    • Views: 1,407
    20th May 2019, 16:22 Go to last post
  17. Including VHDL libraries to add two signals

    Started by joniengr, 17th May 2019 08:42
    • Replies: 8
    • Views: 1,950
    17th May 2019, 19:15 Go to last post
    • Replies: 4
    • Views: 245
    17th May 2019, 07:46 Go to last post
    • Replies: 1
    • Views: 282
    16th May 2019, 21:32 Go to last post
  18. VHDL modulo 2^64 addition

    Started by MSAKARIM, 12th May 2019 17:02
    • Replies: 10
    • Views: 603
    14th May 2019, 17:08 Go to last post
  19. FPGA and processors working

    Started by sushl, 14th May 2019 12:38
    • Replies: 4
    • Views: 547
    14th May 2019, 14:24 Go to last post
  20. [SOLVED] Writing to an output file in VHDL

    Started by MSAKARIM, 14th May 2019 12:48
    • Replies: 2
    • Views: 240
    14th May 2019, 13:56 Go to last post