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Threads 1 to 30 of 22299

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 24,737
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,422
    21st March 2007, 21:21 Go to last post
  1. Error detection and correction

    Started by jalal.baba, 14th July 2018 14:29
    • Replies: 1
    • Views: 236
    Yesterday, 18:54 Go to last post
  2. VHDL Barrel Shifter using SLL and SRL

    Started by shaiko, 13th July 2018 10:55
    • Replies: 2
    • Views: 252
    13th July 2018, 12:57 Go to last post
    • Replies: 0
    • Views: 57
    13th July 2018, 09:20 Go to last post
  3. [SOLVED] Force fitting block without drive output

    Started by nsgil85, 12th July 2018 09:23
    • Replies: 1
    • Views: 109
    12th July 2018, 11:48 Go to last post
  4. help me for microsemi_fifo_core

    Started by jalal.baba, 11th July 2018 11:44
    • Replies: 1
    • Views: 114
    11th July 2018, 12:17 Go to last post
  5. RIFFA full duplex and multi-threading support

    Started by promach, 7th July 2018 10:16
    • Replies: 14
    • Views: 587
    11th July 2018, 09:44 Go to last post
  6. AWS EC2 FPGA amazon cloud computing

    Started by dipin, 10th July 2018 08:11
    • Replies: 3
    • Views: 139
    11th July 2018, 07:41 Go to last post
  7. Xilinx SoC Zynq 7020 + Flash problema

    Started by flote21, 10th July 2018 16:18
    • Replies: 0
    • Views: 89
    10th July 2018, 16:18 Go to last post
  8. test bench for an Adder

    Started by B21hasni, 6th July 2018 14:01
    • Replies: 10
    • Views: 359
    9th July 2018, 21:32 Go to last post
  9. Build an Adder using VHDL

    Started by B21hasni, 12th June 2018 12:40
    • Replies: 16
    • Views: 646
    7th July 2018, 14:45 Go to last post
  10. Moved: error while compiling test bench

    Started by B21hasni, 7th July 2018 08:45
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  11. BRAM based FIFO buffer for matrix multiplication

    Started by maha_66, 5th July 2018 22:31
    • Replies: 8
    • Views: 285
    7th July 2018, 07:33 Go to last post
  12. [SOLVED] Latch created in FSM

    Started by Shubham_Pandia, 5th July 2018 14:32
    • Replies: 1
    • Views: 133
    5th July 2018, 15:02 Go to last post
    • Replies: 5
    • Views: 216
    5th July 2018, 10:33 Go to last post
  13. VHDL code for Designing 16 Bit ALU

    Started by B21hasni, 11th June 2018 23:08
    • Replies: 8
    • Views: 636
    4th July 2018, 22:18 Go to last post
  14. compile package and entity

    Started by B21hasni, 27th June 2018 21:59
    • Replies: 15
    • Views: 623
    4th July 2018, 20:51 Go to last post
  15. Moved: the code in ALU package use work.ALU.all;

    Started by B21hasni, 4th July 2018 21:28
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  16. How to calculate log10(n) in Verilog

    Started by Poomagal, 11th June 2018 07:29
    • Replies: 18
    • Views: 841
    4th July 2018, 04:56 Go to last post
  17. Problem understanding System Verilog

    Started by redtomato11, 1st July 2018 21:38
    • Replies: 0
    • Views: 143
    1st July 2018, 21:38 Go to last post
  18. VHDL Matrix Multiplication using UART and BRAM

    Started by maha_66, 30th June 2018 19:35
    • Replies: 4
    • Views: 259
    1st July 2018, 18:00 Go to last post
  19. No operation (NOP) function

    Started by B21hasni, 30th June 2018 11:28
    • Replies: 5
    • Views: 218
    30th June 2018, 15:18 Go to last post
  20. File as a parameter for VHDL function

    Started by filip.amator, 29th June 2018 16:08
    • Replies: 3
    • Views: 202
    29th June 2018, 18:27 Go to last post
  21. Constraining synchronous reset as false path?

    Started by dzosgornik, 29th June 2018 14:07
    • Replies: 0
    • Views: 90
    29th June 2018, 14:07 Go to last post
  22. DMA's Front and Back Buffer Address Translator

    Started by smbasim, 29th June 2018 13:43
    • Replies: 0
    • Views: 81
    29th June 2018, 13:43 Go to last post
  23. Pipeline stages regs

    Started by Alauddin123, 26th June 2018 11:21
    • Replies: 4
    • Views: 312
    26th June 2018, 21:57 Go to last post
    • Replies: 6
    • Views: 437
    23rd June 2018, 07:23 Go to last post
    • Replies: 11
    • Views: 591
    22nd June 2018, 15:30 Go to last post