1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    115,312
Page 1 of 750 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 22491

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 25,618
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 30,903
    21st March 2007, 21:21 Go to last post
  1. LPC data transfer Method

    Started by beginner_EDA, 22nd January 2019 15:58
    • Replies: 11
    • Views: 236
    Today, 00:18 Go to last post
  2. Using Verilog Tasks in VHDL Code

    Started by mertberkea, Yesterday 08:40
    • Replies: 3
    • Views: 114
    Yesterday, 19:16 Go to last post
  3. Serial by Parallel Booth Multiplier

    Started by promach, 22nd January 2019 03:53
    • Replies: 8
    • Views: 177
    Yesterday, 12:03 Go to last post
  4. Mismatched pcie lanes ip core vs hardware.

    Started by wesleytaylor, 15th January 2019 10:59
    • Replies: 1
    • Views: 134
    Yesterday, 06:10 Go to last post
  5. Formal verification of mutiplier verilog code

    Started by promach, 17th January 2019 07:10
    • Replies: 7
    • Views: 536
    22nd January 2019, 06:56 Go to last post
  6. Unable to allocate all 2GB of DDR4_PL in ZCU106

    Started by msdarvishi, 21st January 2019 23:39
    • Replies: 0
    • Views: 80
    21st January 2019, 23:39 Go to last post
  7. [SOLVED] Simulation in questa

    Started by ranayehya, 16th January 2019 14:58
    • Replies: 1
    • Views: 168
    16th January 2019, 17:29 Go to last post
    • Replies: 1
    • Views: 184
    16th January 2019, 13:24 Go to last post
  8. Converting Verilog to VHDL

    Started by joniengr, 6th December 2018 11:45
    2 Pages
    1 2
    • Replies: 29
    • Views: 1,421
    15th January 2019, 16:48 Go to last post
    • Replies: 7
    • Views: 441
    15th January 2019, 09:24 Go to last post
  9. Spartan 6 - OSERDES2 to ODDR - Unroutable signals

    Started by pigtwo, 12th January 2019 17:22
    • Replies: 4
    • Views: 310
    13th January 2019, 23:28 Go to last post
  10. HPS-FPGA issues on Intel Cyclone V

    Started by Ironlord, 11th January 2019 13:10
    • Replies: 0
    • Views: 192
    11th January 2019, 13:10 Go to last post
  11. USB Softcore for FPGA

    Started by promach, 1st December 2018 05:29
    2 Pages
    1 2
    • Replies: 36
    • Views: 2,053
    7th January 2019, 17:48 Go to last post
  12. XC9536XL programing by DLC9G

    Started by frdm90, 7th January 2019 10:53
    • Replies: 1
    • Views: 180
    7th January 2019, 15:23 Go to last post
    • Replies: 2
    • Views: 304
    4th January 2019, 14:36 Go to last post
    • Replies: 1
    • Views: 138
    4th January 2019, 12:07 Go to last post
  13. Best way to interface with 14-bit 20MSample/s ADC

    Started by Palpurul, 2nd January 2019 14:50
    • Replies: 13
    • Views: 519
    4th January 2019, 10:41 Go to last post
    • Replies: 7
    • Views: 317
    4th January 2019, 09:42 Go to last post
  14. TKEEP and TSTRB in AXI Stream

    Started by joniengr, 30th December 2018 23:02
    • Replies: 5
    • Views: 395
    3rd January 2019, 01:35 Go to last post
  15. [SOLVED] Hierarchical block is unconnected

    Started by jasmine123, 30th December 2018 11:12
    • Replies: 3
    • Views: 195
    31st December 2018, 07:52 Go to last post
    • Replies: 2
    • Views: 201
    30th December 2018, 16:40 Go to last post
  16. registered vs non registered?

    Started by player80, 25th December 2018 12:28
    • Replies: 1
    • Views: 220
    25th December 2018, 15:46 Go to last post
  17. Timing analysis guidance

    Started by dayana42200, 22nd December 2018 01:57
    • Replies: 4
    • Views: 475
    24th December 2018, 06:46 Go to last post
  18. SerDes - architecture and applications

    Started by FlyingDutch, 21st December 2018 15:53
    • Replies: 3
    • Views: 318
    21st December 2018, 17:29 Go to last post
  19. Correct design to work with MIPI and SPI

    Started by Ironlord, 18th December 2018 08:33
    • Replies: 13
    • Views: 678
    21st December 2018, 13:19 Go to last post
  20. [SOLVED] Techniques for logic cell estimation - FPGA

    Started by mjuneja, 21st December 2018 05:13
    • Replies: 1
    • Views: 215
    21st December 2018, 12:27 Go to last post
  21. Lattice Radiant Warnings list

    Started by ilik, 19th December 2018 15:06
    • Replies: 0
    • Views: 116
    19th December 2018, 15:06 Go to last post
    • Replies: 1
    • Views: 289
    16th December 2018, 20:03 Go to last post
  22. PLS explain how to make BRAM

    Started by abimann, 2nd December 2018 07:00
    • Replies: 10
    • Views: 704
    15th December 2018, 21:41 Go to last post
  23. Input and output delay values for FPGA

    Started by Alauddin123, 15th December 2018 06:47
    • Replies: 1
    • Views: 259
    15th December 2018, 20:06 Go to last post