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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Sticky Thread Sticky: IEEE Standard for Standard SystemC® Language Reference Manual

    Started by bassa, 17th January 2012 04:22
    • Replies: 2
    • Views: 30,843
    2nd June 2013, 16:13 Go to last post
  2. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED !!!

    Started by klug, 21st March 2007 21:21
    • Replies: 0
    • Views: 35,663
    21st March 2007, 21:21 Go to last post
  1. ZYNQ Power Requirement

    Started by joniengr, 24th January 2020 17:57
    • Replies: 5
    • Views: 348
    Yesterday, 17:16 Go to last post
    • Replies: 1
    • Views: 184
    26th January 2020, 11:09 Go to last post
    • Replies: 5
    • Views: 287
    24th January 2020, 14:02 Go to last post
    • Replies: 7
    • Views: 306
    23rd January 2020, 18:12 Go to last post
  2. Modelsim Microsemi Pro 2019.2

    Started by dpaul, 22nd January 2020 11:59
    • Replies: 3
    • Views: 286
    23rd January 2020, 12:18 Go to last post
    • Replies: 17
    • Views: 1,489
    21st January 2020, 09:50 Go to last post
    • Replies: 2
    • Views: 411
    16th January 2020, 16:51 Go to last post
  3. question regarding timing analysis or slack time

    Started by dayana42200, 13th January 2020 00:11
    • Replies: 3
    • Views: 413
    13th January 2020, 17:09 Go to last post
    • Replies: 2
    • Views: 492
    13th January 2020, 16:11 Go to last post
  4. ZYNQ 7Z030 LVDS IO - 910 Mbps and Ethernet

    Started by joniengr, 13th January 2020 11:45
    • Replies: 3
    • Views: 299
    13th January 2020, 15:00 Go to last post
  5. Free image fro PYNQ Z1

    Started by adwnis123, 22nd December 2019 20:30
    • Replies: 3
    • Views: 514
    9th January 2020, 13:13 Go to last post
  6. Pipeline: For Loop comparing Module (VHDL)

    Started by yashjain, 23rd December 2019 10:30
    • Replies: 9
    • Views: 704
    8th January 2020, 17:57 Go to last post
  7. P1500 Wrapper implementation

    Started by sami154, 7th January 2020 19:30
    • Replies: 3
    • Views: 329
    8th January 2020, 11:49 Go to last post
  8. FATAL ERROR while loading design in VHDL

    Started by mohit11511, 4th January 2020 15:50
    • Replies: 3
    • Views: 403
    5th January 2020, 00:30 Go to last post
  9. Counter cİrcuİt (3 forward 2 back)

    Started by electriccc01, 19th December 2019 19:34
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,672
    26th December 2019, 03:27 Go to last post
  10. 0-9 2 forward 1 back counter design

    Started by Laskon, 23rd December 2019 23:03
    • Replies: 6
    • Views: 691
    25th December 2019, 08:56 Go to last post
  11. Implement a serial transmission system

    Started by love3cyou, 24th December 2019 05:14
    • Replies: 8
    • Views: 680
    24th December 2019, 14:30 Go to last post
  12. AXI4 VHDL BFM Options

    Started by ptkinzer, 24th October 2019 13:32
    • Replies: 18
    • Views: 2,628
    23rd December 2019, 19:04 Go to last post
  13. [SOLVED] Send one parameter from systemverilog to another in Vivado 2017.3

    Started by Cesar0182, 17th December 2019 23:36
    • Replies: 4
    • Views: 671
    20th December 2019, 14:51 Go to last post
  14. [SOLVED] VHDL - creation of files with unique file names

    Started by dpaul, 19th December 2019 14:34
    • Replies: 2
    • Views: 495
    20th December 2019, 12:49 Go to last post
  15. Convert real to 2's complement & vice versa in Verilog

    Started by nader.skf, 13th December 2019 20:27
    • Replies: 1
    • Views: 473
    14th December 2019, 11:57 Go to last post
  16. Tracking Phase comparator Logic

    Started by curious_mind, 11th December 2019 05:52
    • Replies: 12
    • Views: 1,087
    12th December 2019, 20:11 Go to last post
  17. explanation about bram and ddr3

    Started by abimann, 11th December 2019 08:26
    • Replies: 2
    • Views: 501
    11th December 2019, 14:52 Go to last post
  18. Solve Equations Verilog

    Started by Chinmaye, 28th November 2019 07:05
    • Replies: 11
    • Views: 1,295
    10th December 2019, 08:02 Go to last post
  19. fastest multiplication alghorithms

    Started by Zerox100, 2nd December 2019 14:51
    • Replies: 13
    • Views: 1,299
    6th December 2019, 03:59 Go to last post
    • Replies: 9
    • Views: 1,076
    5th December 2019, 15:24 Go to last post
  20. Verilator width warnings

    Started by promach, 3rd December 2019 06:37
    • Replies: 3
    • Views: 555
    4th December 2019, 17:00 Go to last post
  21. Multiplication in vhdl

    Started by sonika111, 3rd December 2019 15:10
    • Replies: 1
    • Views: 421
    3rd December 2019, 16:02 Go to last post
  22. QMTECH Xilinx FPGA Artix7 Artix-7 Development Board

    Started by FlyingDutch, 29th November 2019 17:30
    • Replies: 5
    • Views: 807
    2nd December 2019, 14:52 Go to last post