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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Closed: Openings for ASIC verification(Specman)

    Started by vijaymails, 6th August 2008 07:38
    • Replies: 0
    • Views: 1,502
    vijaymails
    6th August 2008, 07:38 Go to last post

  2. Closed: How to export the output of "data list model_pin $m" to a file in Magma M-TCL?

    Started by alchemist1, 6th August 2008 04:31
    • Replies: 1
    • Views: 926
    karthiktr
    6th August 2008, 06:48 Go to last post

  3. Closed: MAGMA Physical Verification

    Started by pd_engineer, 6th August 2008 05:52
    • Replies: 0
    • Views: 852
    pd_engineer
    6th August 2008, 05:52 Go to last post

  4. Closed: DC command for searching a command

    Started by anssprasad, 5th August 2008 12:05
    • Replies: 1
    • Views: 858
    vlsi_eda_guy
    5th August 2008, 19:15 Go to last post

  5. Closed: How to test EDK generated ethernet code?

    Started by Tan, 5th August 2008 13:08
    • Replies: 0
    • Views: 918
    Tan
    5th August 2008, 13:08 Go to last post

  6. Closed: Doubt about AHB and split transfers

    Started by hurricanebomb, 15th May 2008 09:22
    • Replies: 4
    • Views: 1,748
    anssprasad
    5th August 2008, 12:11 Go to last post

  7. Closed: Constraint for input pin in synthesis

    Started by cafukarfoo, 1st August 2008 11:01
    • Replies: 7
    • Views: 1,327
    cafukarfoo
    5th August 2008, 11:31 Go to last post

  8. Closed: Will the clock gating affect the setup/hold time of the flop?

    Started by sareene, 5th August 2008 10:24
    • Replies: 1
    • Views: 1,534
    vipulsinha
    5th August 2008, 11:21 Go to last post

  9. Closed: How to analyse SoC architecture?

    Started by zjushmily, 5th August 2008 11:13
    • Replies: 0
    • Views: 710
    zjushmily
    5th August 2008, 11:13 Go to last post

  10. Closed: Looking for DFTadvisor Training Labs

    Started by alam.tauqueer, 29th July 2008 13:01
    • Replies: 4
    • Views: 1,655
    alam.tauqueer
    5th August 2008, 11:10 Go to last post

  11. Closed: verilog race condition on Async Reset

    Started by vipulsinha, 5th August 2008 09:46
    • Replies: 2
    • Views: 2,146
    sareene
    5th August 2008, 10:29 Go to last post

  12. Closed: Suggestion regarding USB2 or USB3 projects

    Started by mallikmarasu, 5th August 2008 09:00
    • Replies: 0
    • Views: 1,004
    mallikmarasu
    5th August 2008, 09:00 Go to last post

  13. Closed: Topics for research proposal in the field of System Level Integration

    Started by usmanstar2, 5th August 2008 08:05
    • Replies: 0
    • Views: 854
    usmanstar2
    5th August 2008, 08:05 Go to last post

  14. Closed: How to report the area per block/module in Synopsys Astro?

    Started by ryodan_2004, 25th July 2008 03:52
    • Replies: 1
    • Views: 1,571
    chyau
    5th August 2008, 07:22 Go to last post

  15. Closed: can anybody talk about "Clock Gating"

    Started by nine8, 4th August 2008 14:04
    • Replies: 1
    • Views: 867
    natg9
    5th August 2008, 06:01 Go to last post

  16. Closed: Fast-Track course on Verification Using SystemVerilog @ BLR

    Started by aji_vlsi, 1st June 2008 15:53
    • Replies: 3
    • Views: 1,685
    aji_vlsi
    5th August 2008, 05:16 Go to last post

  17. Closed: Double buffering Synchronisation

    Started by abhihegde, 4th August 2008 15:06
    • Replies: 0
    • Views: 961
    abhihegde
    4th August 2008, 15:06 Go to last post

  18. Closed: Suitable max transition number

    Started by cafukarfoo, 4th August 2008 10:45
    • Replies: 0
    • Views: 1,220
    cafukarfoo
    4th August 2008, 10:45 Go to last post

  19. Closed: Why we don't use power domains for IO?

    Started by chintalaudaykumar, 30th July 2008 12:41
    • Replies: 4
    • Views: 1,108
    natg9
    4th August 2008, 08:24 Go to last post

  20. Closed: How to check my standard cel library syntax in synopsys tool

    Started by venkat25, 30th July 2008 11:18
    • Replies: 4
    • Views: 1,587
    muthamil
    4th August 2008, 05:53 Go to last post

  21. Closed: Full custom design of datapath for use in CPU

    Started by iamxo, 2nd August 2008 03:09
    • Replies: 3
    • Views: 1,236
    ljxpjpjljx
    4th August 2008, 05:11 Go to last post

  22. Closed: One problem on dumping fsdb file of verdi.

    Started by Merlionfire, 1st August 2008 06:16
    • Replies: 2
    • Views: 27,956
    ljxpjpjljx
    3rd August 2008, 15:44 Go to last post

  23. Closed: Explain me the calculation of minimum clock period

    Started by vikram789, 3rd August 2008 12:40
    • Replies: 1
    • Views: 2,226
    vikram789
    3rd August 2008, 12:53 Go to last post

  24. Closed: Synthsis error using DC

    Started by bzaki, 3rd August 2008 07:50
    • Replies: 0
    • Views: 887
    bzaki
    3rd August 2008, 07:50 Go to last post

  25. Closed: what is sanity check?where it can use?

    Started by vamsi_addagada, 31st July 2008 11:01
    • Replies: 2
    • Views: 1,508
    uditkumar1983
    2nd August 2008, 13:36 Go to last post

  26. Closed: min time period, questions

    Started by vikram789, 2nd August 2008 10:55
    • Replies: 0
    • Views: 1,117
    vikram789
    2nd August 2008, 10:55 Go to last post

  27. Closed: Power estimation after synthesis and Place-&-route

    Started by naderi, 2nd August 2008 01:16
    • Replies: 1
    • Views: 2,076
    MarcS
    2nd August 2008, 08:42 Go to last post

  28. Closed: how clock skew can be beneficial

    Started by vikram789, 2nd August 2008 04:08
    • Replies: 1
    • Views: 2,026
    MarcS
    2nd August 2008, 08:27 Go to last post

  29. Closed: anyone who knows about design of card againt attacking?

    Started by gogogo, 24th March 2005 09:13
    • Replies: 4
    • Views: 1,190
    QELEC
    2nd August 2008, 06:03 Go to last post

  30. Closed: How to estimate and set optimization constraints using DC tool?

    Started by engr, 31st July 2008 23:06
    • Replies: 4
    • Views: 1,371
    engr
    1st August 2008, 18:19 Go to last post
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