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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Closed: CAN ANYBODY SEND ME MATERIAL RELATED TO PHYSICAL DESIGN

    Started by natg9, 17th July 2008 12:01
    • Replies: 2
    • Views: 1,364
    natg9
    18th July 2008, 11:36 Go to last post

  2. Closed: difference btw a level and pulse

    Started by ls000rhb, 16th July 2008 07:29
    • Replies: 2
    • Views: 1,073
    ls000rhb
    18th July 2008, 07:40 Go to last post

  3. Closed: Can I make a digital design with 0.5V cell library?

    Started by jcpu, 18th July 2008 00:21
    • Replies: 1
    • Views: 910
    MarcS
    18th July 2008, 06:19 Go to last post

  4. Closed: About Error Messages on Quartus, Need a hand.

    Started by wufei, 18th July 2008 04:24
    • Replies: 0
    • Views: 1,722
    wufei
    18th July 2008, 04:24 Go to last post

  5. Closed: Why does core are change when core utilization ratio is changed?

    Started by gopakumargnair, 17th July 2008 09:56
    • Replies: 2
    • Views: 1,536
    gliss
    17th July 2008, 21:27 Go to last post

  6. Closed: Device that test if signal is 5V for 1sec

    Started by zelsenussi, 17th July 2008 16:18
    • Replies: 0
    • Views: 673
    zelsenussi
    17th July 2008, 16:18 Go to last post

  7. Closed: Antenna Violation Fix

    Started by S.Nikhil, 15th July 2008 12:33
    • Replies: 5
    • Views: 4,024
    MarcS
    17th July 2008, 15:50 Go to last post

  8. Closed: What are the factors that determine the setup time of a flip-flop?

    Started by S.Nikhil, 15th July 2008 12:30
    • Replies: 5
    • Views: 1,669
    ericyuan
    17th July 2008, 14:29 Go to last post

  9. Closed: Warnings in The log file.

    Started by suresh etikala, 14th July 2008 21:49
    • Replies: 4
    • Views: 1,714
    suresh etikala
    17th July 2008, 14:25 Go to last post

  10. Closed: which ESL tool do you use?

    Started by maxsnail, 17th July 2008 08:04
    • Replies: 0
    • Views: 831
    maxsnail
    17th July 2008, 08:04 Go to last post

  11. Closed: difference b/w contention latency and serializtion latency

    Started by rockgird, 15th July 2008 08:08
    • Replies: 1
    • Views: 1,929
    MarcS
    17th July 2008, 07:15 Go to last post

  12. Closed: why holdtime is not considerd for Tclkmax calculation

    Started by kil, 16th July 2008 10:09
    • Replies: 1
    • Views: 1,558
    MarcS
    17th July 2008, 06:41 Go to last post

  13. Closed: implementing small size memory on design

    Started by childs, 7th July 2008 10:51
    • Replies: 1
    • Views: 957
    FLEXcertifydll
    17th July 2008, 06:06 Go to last post

  14. Closed: SETUPHOLD and SETUP in one SDF ?

    Started by ishwar, 16th July 2008 05:32
    • Replies: 2
    • Views: 2,771
    ljxpjpjljx
    17th July 2008, 05:45 Go to last post

  15. Closed: Difference between Latency and Delay

    Started by spartanthewarrior, 26th April 2008 09:00
    • Replies: 4
    • Views: 5,552
    rockgird
    15th July 2008, 08:04 Go to last post

  16. Closed: NCSIM's command script magic?

    Started by kelvin_sg, 15th July 2008 07:51
    • Replies: 0
    • Views: 1,783
    kelvin_sg
    15th July 2008, 07:51 Go to last post

  17. Closed: Interface between IPs on Chip

    Started by Mirzaaur, 11th July 2008 10:01
    • Replies: 1
    • Views: 856
    ls000rhb
    15th July 2008, 07:29 Go to last post

  18. Closed: How to solve the error "CDSDOC-002" in opening th

    Started by hgby2209, 15th July 2008 06:39
    • Replies: 0
    • Views: 1,008
    hgby2209
    15th July 2008, 06:39 Go to last post

  19. Closed: Looking for UPF labs (including rtl, script and upf files)

    Started by arunragavan, 15th July 2008 02:08
    • Replies: 1
    • Views: 1,762
    carv_13
    15th July 2008, 02:11 Go to last post

  20. Closed: How to put 2 ports output (each port 4 bit) into a device?

    Started by zelsenussi, 14th July 2008 13:03
    • Replies: 0
    • Views: 811
    zelsenussi
    14th July 2008, 13:03 Go to last post

  21. Closed: Help me with gate level simulation using VCS

    Started by balasub, 11th June 2008 14:22
    • Replies: 12
    • Views: 7,171
    jonyRoyal
    14th July 2008, 10:44 Go to last post

  22. Closed: Clock Generation Block

    Started by omara007, 10th July 2008 15:39
    • Replies: 3
    • Views: 1,161
    koppolu1981
    14th July 2008, 05:59 Go to last post

  23. Closed: Functional Coverage in Sytem Verilog

    Started by carrot, 9th July 2008 12:21
    • Replies: 1
    • Views: 1,281
    ljxpjpjljx
    14th July 2008, 03:05 Go to last post

  24. Closed: What is \***SEQGEN***\ in synthesis of netlist using Design Compiler?

    Started by ASIC_intl, 12th July 2008 16:03
    • Replies: 3
    • Views: 8,934
    ASIC_intl
    13th July 2008, 08:53 Go to last post

  25. Closed: help needed regarding the topic

    Started by himadrisinghraghav, 13th July 2008 07:21
    • Replies: 0
    • Views: 638
    himadrisinghraghav
    13th July 2008, 07:21 Go to last post

  26. Closed: can anybody upload ebook 'The art of verification with VERA'

    Started by owen_li, 23rd March 2008 11:27
    • Replies: 1
    • Views: 1,334
    xhui
    12th July 2008, 18:45 Go to last post

  27. Closed: Steps of the ASIC design process

    Started by swetha.incore, 9th July 2008 13:13
    • Replies: 3
    • Views: 2,354
    MarcS
    12th July 2008, 13:27 Go to last post

  28. Closed: Few doubts regarding RTL compiler

    Started by barath_87, 16th June 2008 16:45
    • Replies: 2
    • Views: 1,084
    MarcS
    12th July 2008, 06:16 Go to last post

  29. Closed: A beginner question,please help

    Started by elec-eng, 7th July 2008 15:41
    • Replies: 3
    • Views: 1,193
    MarcS
    12th July 2008, 06:08 Go to last post

  30. Closed: How to solve congestion problem after CTS without effecting skew and timing?

    Started by designer_ec, 6th July 2008 14:53
    • Replies: 4
    • Views: 2,469
    MarcS
    12th July 2008, 06:00 Go to last post
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