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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Closed: What's soft blockage ang hard blockage's mean in Astro?

    Started by hgby2209, 24th June 2008 12:12
    • Replies: 1
    • Views: 3,535
    shrbht
    24th June 2008, 13:39 Go to last post

  2. Closed: the vhdl code for the video processing

    Started by aasif, 24th November 2004 15:04
    • Replies: 14
    • Views: 9,601
    shobhitk
    24th June 2008, 13:28 Go to last post

  3. Closed: What is Verification Plan and Test Plan.........?

    Started by kushagrak, 20th June 2008 10:37
    • Replies: 7
    • Views: 8,691
    shobhitk
    24th June 2008, 13:21 Go to last post

  4. Closed: what is e path and HDL path in E...?

    Started by kushagrak, 24th June 2008 10:39
    • Replies: 1
    • Views: 1,447
    pintuinvlsi
    24th June 2008, 12:39 Go to last post

  5. Closed: sys struct or unit..?

    Started by kushagrak, 13th June 2008 09:39
    • Replies: 1
    • Views: 1,249
    kushagrak
    24th June 2008, 10:50 Go to last post

  6. Poll: Closed: PLease Vote: Electronics Engineer Vs Computer Engineer

    Started by nan_ishan, 14th December 2007 11:48
    6 Pages •
    1 2 3 ... 6
    • Replies: 101
    • Views: 16,699
    farhantariq
    24th June 2008, 10:36 Go to last post

  7. Closed: about design compiler analyze & elaborate command

    Started by ASIC_intl, 24th June 2008 08:46
    • Replies: 0
    • Views: 2,936
    ASIC_intl
    24th June 2008, 08:46 Go to last post

  8. Closed: Values for power mesh calculations

    Started by snr_vlsi, 18th June 2008 06:26
    • Replies: 4
    • Views: 1,478
    S.Nikhil
    24th June 2008, 06:35 Go to last post

  9. Closed: I need to get a paper from IEEE Xplore

    Started by Samoohaa, 21st June 2008 18:08
    • Replies: 3
    • Views: 1,082
    waqasbaig
    24th June 2008, 04:29 Go to last post

  10. Closed: Problem with I/O assignment in SOC Encounter

    Started by sachinmaheshwari, 16th June 2008 06:34
    • Replies: 7
    • Views: 4,168
    gliss
    23rd June 2008, 18:39 Go to last post

  11. Closed: From gate-level to transistor level

    Started by amsut, 14th June 2008 13:14
    • Replies: 2
    • Views: 2,043
    atena
    23rd June 2008, 13:05 Go to last post

  12. Closed: How to compile VHDL files that are below the Verilog at the top level using VCS MX?

    Started by india1234, 20th June 2008 13:33
    • Replies: 2
    • Views: 3,554
    atena
    23rd June 2008, 13:01 Go to last post

  13. Closed: How to calculate core ring width, macro ring width and strap

    Started by vamsi_addagada, 10th April 2008 06:09
    • Replies: 4
    • Views: 2,806
    ls000rhb
    23rd June 2008, 11:52 Go to last post

  14. Closed: What is a wire load model ?

    Started by santumevce1412, 20th June 2008 11:49
    • Replies: 3
    • Views: 2,412
    ls000rhb
    23rd June 2008, 10:52 Go to last post

  15. Closed: use 10000M ethenet to exchange a JPEG200 IP

    Started by maxsnail, 23rd June 2008 10:31
    • Replies: 0
    • Views: 751
    maxsnail
    23rd June 2008, 10:31 Go to last post

  16. Closed: how wil you build verification environment for AND gate

    Started by kushagrak, 20th June 2008 14:05
    • Replies: 2
    • Views: 959
    kushagrak
    23rd June 2008, 09:50 Go to last post

  17. Closed: Programmable ROM in ASIC

    Started by kevinj, 21st June 2008 21:47
    • Replies: 3
    • Views: 1,681
    FvM
    22nd June 2008, 20:21 Go to last post

  18. Closed: Spyglass Querry :: Message ( Warning and Info export querry)

    Started by shobhitk, 20th June 2008 09:20
    • Replies: 1
    • Views: 1,239
    shobhitk
    22nd June 2008, 07:14 Go to last post

  19. Closed: about ASIC design flow for 0.13um logic?

    Started by shrbht, 27th April 2008 13:54
    • Replies: 3
    • Views: 1,672
    faiflay
    21st June 2008, 20:33 Go to last post

  20. Closed: cmos layout file of instrumentation amplifer

    Started by suru, 1st March 2008 08:52
    • Replies: 1
    • Views: 981
    faiflay
    21st June 2008, 20:27 Go to last post

  21. Closed: relation between metal density rule and yield

    Started by sp3, 9th June 2008 07:59
    • Replies: 2
    • Views: 1,541
    sunjimmy
    21st June 2008, 15:23 Go to last post

  22. Closed: clock data recovery (all digital)

    Started by gold_kiss, 11th June 2008 11:17
    • Replies: 3
    • Views: 1,489
    sunjimmy
    21st June 2008, 15:17 Go to last post

  23. Closed: FSM design questions...

    Started by sp3, 21st June 2008 07:38
    • Replies: 1
    • Views: 4,311
    soloktanjung
    21st June 2008, 08:39 Go to last post

  24. Closed: CMOS related questions..

    Started by sp3, 21st June 2008 07:34
    • Replies: 0
    • Views: 1,089
    sp3
    21st June 2008, 07:34 Go to last post

  25. Closed: how to add delay for sram?

    Started by shield, 20th June 2008 16:46
    • Replies: 0
    • Views: 810
    shield
    20th June 2008, 16:46 Go to last post

  26. Closed: synthesis with buildgates

    Started by dario84, 20th June 2008 15:43
    • Replies: 0
    • Views: 660
    dario84
    20th June 2008, 15:43 Go to last post

  27. Closed: Looking for documents about Netlist Validation

    Started by spartanthewarrior, 16th June 2008 14:29
    • Replies: 1
    • Views: 1,084
    pintuinvlsi
    20th June 2008, 15:31 Go to last post

  28. Closed: Manual Place and route

    Started by sandeep_sggs, 20th June 2008 11:16
    • Replies: 1
    • Views: 997
    gliss
    20th June 2008, 15:21 Go to last post

  29. Closed: question about this.ports in systemverilog

    Started by THUNDERRr, 19th June 2008 13:43
    • Replies: 2
    • Views: 1,111
    pintuinvlsi
    20th June 2008, 11:17 Go to last post

  30. Closed: What are the *free* tools supporting SystemVerilog?

    Started by kelvin_sg, 9th April 2008 07:09
    • Replies: 4
    • Views: 3,608
    soloktanjung
    19th June 2008, 22:26 Go to last post
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