1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    121,666
Page 501 of 814 FirstFirst ... 401 451 491 499 500 501 502 503 511 551 601 ... LastLast
Threads 15001 to 15030 of 24419

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Closed: What's soft blockage ang hard blockage's mean in Astro?

    Started by hgby2209, 24th June 2008 12:12
    • Replies: 1
    • Views: 3,535
    24th June 2008, 13:39 Go to last post
  2. Closed: the vhdl code for the video processing

    Started by aasif, 24th November 2004 15:04
    • Replies: 14
    • Views: 9,601
    24th June 2008, 13:28 Go to last post
  3. Closed: What is Verification Plan and Test Plan.........?

    Started by kushagrak, 20th June 2008 10:37
    • Replies: 7
    • Views: 8,691
    24th June 2008, 13:21 Go to last post
  4. Closed: what is e path and HDL path in E...?

    Started by kushagrak, 24th June 2008 10:39
    • Replies: 1
    • Views: 1,447
    24th June 2008, 12:39 Go to last post
  5. Closed: sys struct or unit..?

    Started by kushagrak, 13th June 2008 09:39
    • Replies: 1
    • Views: 1,249
    24th June 2008, 10:50 Go to last post
  6. Poll: Closed: PLease Vote: Electronics Engineer Vs Computer Engineer

    Started by nan_ishan, 14th December 2007 11:48
    6 Pages
    1 2 3 ... 6
    • Replies: 101
    • Views: 16,699
    24th June 2008, 10:36 Go to last post
  7. Closed: about design compiler analyze & elaborate command

    Started by ASIC_intl, 24th June 2008 08:46
    • Replies: 0
    • Views: 2,936
    24th June 2008, 08:46 Go to last post
  8. Closed: Values for power mesh calculations

    Started by snr_vlsi, 18th June 2008 06:26
    • Replies: 4
    • Views: 1,478
    24th June 2008, 06:35 Go to last post
  9. Closed: I need to get a paper from IEEE Xplore

    Started by Samoohaa, 21st June 2008 18:08
    • Replies: 3
    • Views: 1,082
    24th June 2008, 04:29 Go to last post
  10. Closed: Problem with I/O assignment in SOC Encounter

    Started by sachinmaheshwari, 16th June 2008 06:34
    • Replies: 7
    • Views: 4,168
    23rd June 2008, 18:39 Go to last post
  11. Closed: From gate-level to transistor level

    Started by amsut, 14th June 2008 13:14
    • Replies: 2
    • Views: 2,043
    23rd June 2008, 13:05 Go to last post
    • Replies: 2
    • Views: 3,554
    23rd June 2008, 13:01 Go to last post
    • Replies: 4
    • Views: 2,806
    23rd June 2008, 11:52 Go to last post
  12. Closed: What is a wire load model ?

    Started by santumevce1412, 20th June 2008 11:49
    • Replies: 3
    • Views: 2,412
    23rd June 2008, 10:52 Go to last post
  13. Closed: use 10000M ethenet to exchange a JPEG200 IP

    Started by maxsnail, 23rd June 2008 10:31
    • Replies: 0
    • Views: 751
    23rd June 2008, 10:31 Go to last post
  14. Closed: how wil you build verification environment for AND gate

    Started by kushagrak, 20th June 2008 14:05
    • Replies: 2
    • Views: 959
    23rd June 2008, 09:50 Go to last post
  15. Closed: Programmable ROM in ASIC

    Started by kevinj, 21st June 2008 21:47
    • Replies: 3
    • Views: 1,681
    22nd June 2008, 20:21 Go to last post
  16. Closed: Spyglass Querry :: Message ( Warning and Info export querry)

    Started by shobhitk, 20th June 2008 09:20
    • Replies: 1
    • Views: 1,239
    22nd June 2008, 07:14 Go to last post
  17. Closed: about ASIC design flow for 0.13um logic?

    Started by shrbht, 27th April 2008 13:54
    • Replies: 3
    • Views: 1,672
    21st June 2008, 20:33 Go to last post
  18. Closed: cmos layout file of instrumentation amplifer

    Started by suru, 1st March 2008 08:52
    • Replies: 1
    • Views: 981
    21st June 2008, 20:27 Go to last post
  19. Closed: relation between metal density rule and yield

    Started by sp3, 9th June 2008 07:59
    • Replies: 2
    • Views: 1,541
    21st June 2008, 15:23 Go to last post
  20. Closed: clock data recovery (all digital)

    Started by gold_kiss, 11th June 2008 11:17
    • Replies: 3
    • Views: 1,489
    21st June 2008, 15:17 Go to last post
  21. Closed: FSM design questions...

    Started by sp3, 21st June 2008 07:38
    • Replies: 1
    • Views: 4,311
    21st June 2008, 08:39 Go to last post
  22. Closed: CMOS related questions..

    Started by sp3, 21st June 2008 07:34
    • Replies: 0
    • Views: 1,089
    21st June 2008, 07:34 Go to last post
  23. Closed: how to add delay for sram?

    Started by shield, 20th June 2008 16:46
    • Replies: 0
    • Views: 810
    20th June 2008, 16:46 Go to last post
  24. Closed: synthesis with buildgates

    Started by dario84, 20th June 2008 15:43
    • Replies: 0
    • Views: 660
    20th June 2008, 15:43 Go to last post
  25. Closed: Looking for documents about Netlist Validation

    Started by spartanthewarrior, 16th June 2008 14:29
    • Replies: 1
    • Views: 1,084
    20th June 2008, 15:31 Go to last post
  26. Closed: Manual Place and route

    Started by sandeep_sggs, 20th June 2008 11:16
    • Replies: 1
    • Views: 997
    20th June 2008, 15:21 Go to last post
  27. Closed: question about this.ports in systemverilog

    Started by THUNDERRr, 19th June 2008 13:43
    • Replies: 2
    • Views: 1,111
    20th June 2008, 11:17 Go to last post
  28. Closed: What are the *free* tools supporting SystemVerilog?

    Started by kelvin_sg, 9th April 2008 07:09
    • Replies: 4
    • Views: 3,608
    19th June 2008, 22:26 Go to last post