1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    125,265
Page 501 of 818 FirstFirst ... 401 451 491 499 500 501 502 503 511 551 601 ... LastLast
Threads 15001 to 15030 of 24524

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Closed: Steps of the ASIC design process

    Started by swetha.incore, 9th July 2008 13:13
    • Replies: 3
    • Views: 2,327
    MarcS
    12th July 2008, 13:27 Go to last post

  2. Closed: Few doubts regarding RTL compiler

    Started by barath_87, 16th June 2008 16:45
    • Replies: 2
    • Views: 1,067
    MarcS
    12th July 2008, 06:16 Go to last post

  3. Closed: A beginner question,please help

    Started by elec-eng, 7th July 2008 15:41
    • Replies: 3
    • Views: 1,172
    MarcS
    12th July 2008, 06:08 Go to last post

  4. Closed: How to solve congestion problem after CTS without effecting skew and timing?

    Started by designer_ec, 6th July 2008 14:53
    • Replies: 4
    • Views: 2,420
    MarcS
    12th July 2008, 06:00 Go to last post

  5. Closed: equivalent function in Verilog for VHDL 'LENGTH function?

    Started by korgull, 9th July 2008 21:02
    • Replies: 3
    • Views: 17,134
    boardlanguage
    11th July 2008, 16:57 Go to last post

  6. Closed: Synopsys DC 2001 libraries

    Started by elec-eng, 11th July 2008 16:06
    • Replies: 0
    • Views: 848
    elec-eng
    11th July 2008, 16:06 Go to last post

  7. Closed: relation between static power dissippation and speed of opat

    Started by sp3, 10th July 2008 09:34
    • Replies: 5
    • Views: 983
    jivijaya
    11th July 2008, 12:39 Go to last post

  8. Closed: objets not found in questsim waveform window

    Started by praneethkpt, 10th July 2008 14:42
    • Replies: 1
    • Views: 865
    nand_gates
    11th July 2008, 07:40 Go to last post

  9. Closed: How to generate sdf using max & min libs so sdf will consists of corresponding delays

    Started by viswanadh_babu, 6th June 2008 06:26
    • Replies: 4
    • Views: 2,607
    viswanadh_babu
    11th July 2008, 06:32 Go to last post

  10. [SOLVED]Closed: Post-synthesis simulation with ModelSim

    Started by Pti_Biscuit22, 10th July 2008 16:33
    • Replies: 0
    • Views: 3,802
    Pti_Biscuit22
    10th July 2008, 16:33 Go to last post

  11. Closed: What are the differences between signal assignments and variable assignments in VHDL?

    Started by ASIC_intl, 9th July 2008 15:34
    • Replies: 2
    • Views: 3,074
    himadrisinghraghav
    10th July 2008, 06:12 Go to last post

  12. Closed: suggest me some good books/articles

    Started by sp3, 9th July 2008 07:20
    • Replies: 1
    • Views: 1,147
    sachinmaheshwari
    10th July 2008, 05:56 Go to last post

  13. What is the typical setting of transition time in CTS constraint?

    Started by jason.wei, 10th July 2008 02:45
    • Replies: 1
    • Views: 1,625
    ljxpjpjljx
    10th July 2008, 04:27 Go to last post

  14. Closed: question about memory bist

    Started by quake, 9th July 2008 14:52
    • Replies: 1
    • Views: 1,283
    quake
    10th July 2008, 03:55 Go to last post

  15. Closed: Max cap & tran limit in SDC

    Started by fail1, 7th July 2008 23:39
    • Replies: 5
    • Views: 1,722
    fail1
    10th July 2008, 00:26 Go to last post

  16. Closed: Using TCL in NCSIM Postlayout

    Started by alagendranc, 9th July 2008 13:30
    • Replies: 0
    • Views: 1,477
    alagendranc
    9th July 2008, 13:30 Go to last post

  17. Closed: Verilog Compilation problem in module instantiation

    Started by rmmy, 8th July 2008 13:19
    • Replies: 2
    • Views: 3,041
    nand_gates
    9th July 2008, 05:54 Go to last post

  18. Closed: Xilinx ISE Synthesis tool

    Started by mpatel, 26th August 2006 03:55
    • Replies: 4
    • Views: 2,866
    ljxpjpjljx
    9th July 2008, 03:15 Go to last post

  19. Closed: missing presto_vhdl.prims

    Started by Clunixchit, 8th July 2008 16:00
    • Replies: 0
    • Views: 760
    Clunixchit
    8th July 2008, 16:00 Go to last post

  20. Closed: anyone has source codes in systemverilog ie: *.sv files?

    Started by THUNDERRr, 21st June 2008 14:49
    • Replies: 2
    • Views: 916
    mezhihuan
    8th July 2008, 14:42 Go to last post

  21. Closed: Help me with working with VHDL text I/O to read data

    Started by modukuri, 13th May 2004 00:41
    • Replies: 7
    • Views: 7,295
    manish12
    8th July 2008, 10:30 Go to last post

  22. Closed: non-volatile memory usage

    Started by childs, 8th July 2008 10:18
    • Replies: 0
    • Views: 904
    childs
    8th July 2008, 10:18 Go to last post

  23. Closed: What should be the scope of my sdf file?

    Started by bossbebes, 3rd July 2008 10:19
    • Replies: 2
    • Views: 1,463
    bossbebes
    8th July 2008, 10:01 Go to last post

  24. Closed: ncelab // synplify_pro // quartus // stratixii

    Started by bossbebes, 8th July 2008 09:53
    • Replies: 0
    • Views: 1,256
    bossbebes
    8th July 2008, 09:53 Go to last post

  25. Closed: which language is used to "makefile" run simulatoi

    Started by THUNDERRr, 6th July 2008 09:25
    • Replies: 1
    • Views: 885
    sree205
    8th July 2008, 07:35 Go to last post

  26. Closed: How Wind Turbine related to course BSCoE? please help

    Started by sinichi000, 8th July 2008 01:28
    • Replies: 1
    • Views: 1,239
    carl_arc3x4
    8th July 2008, 07:17 Go to last post

  27. Closed: Generate LEF files with Abstract！

    Started by keithma, 20th March 2007 03:24
    • Replies: 2
    • Views: 2,297
    290702500
    8th July 2008, 06:55 Go to last post

  28. Closed: what is meant by "glue logic component"?

    Started by THUNDERRr, 6th July 2008 09:10
    • Replies: 2
    • Views: 3,003
    jimaaa0
    8th July 2008, 05:33 Go to last post

  29. Closed: Asynchronous Circuit design ICFB

    Started by AdvaRes, 7th July 2008 11:02
    • Replies: 0
    • Views: 741
    AdvaRes
    7th July 2008, 11:02 Go to last post

  30. Closed: Verilog Compilation problem in module instantiation

    Started by rmmy, 5th July 2008 17:21
    • Replies: 2
    • Views: 3,800
    pete_lu
    7th July 2008, 10:20 Go to last post
Powered by vBulletin
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.