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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. DRC problem with layout in cadence 617

    Started by abdoboua, 8th July 2019 19:05
    • Replies: 1
    • Views: 263
    16th July 2019, 11:35 Go to last post
  2. Problem when installing Calibre

    Started by abdoboua, 10th July 2019 20:35
    • Replies: 1
    • Views: 262
    15th July 2019, 16:22 Go to last post
  3. ModelSim simulation error

    Started by garvind25, 11th July 2019 10:42
    • Replies: 11
    • Views: 700
    15th July 2019, 15:59 Go to last post
  4. Cannot find vdd in the design

    Started by kartikpujari, 14th July 2019 05:25
    • Replies: 2
    • Views: 314
    14th July 2019, 19:44 Go to last post
    • Replies: 1
    • Views: 398
    14th July 2019, 18:48 Go to last post
  5. Systemverilog type cast or integer division

    Started by parafux, 10th July 2019 13:51
    • Replies: 2
    • Views: 287
    13th July 2019, 18:53 Go to last post
  6. Global Buffer Access Normalized Energy Cost

    Started by moa375, 12th July 2019 21:51
    • Replies: 0
    • Views: 211
    12th July 2019, 21:51 Go to last post
  7. What do you mean by Predictive FIFO?

    Started by rameshbabur, 11th July 2019 08:01
    • Replies: 2
    • Views: 322
    12th July 2019, 19:01 Go to last post
    • Replies: 2
    • Views: 287
    12th July 2019, 18:46 Go to last post
  8. Digital design of a GPU

    Started by adwnis123, 11th July 2019 14:06
    • Replies: 3
    • Views: 369
    12th July 2019, 14:00 Go to last post
  9. Saving the layout in innovus

    Started by Chinmaye, 10th July 2019 11:45
    • Replies: 7
    • Views: 442
    11th July 2019, 17:44 Go to last post
    • Replies: 3
    • Views: 306
    10th July 2019, 21:41 Go to last post
  10. [SOLVED] Error during clock tree synthesis in innovus

    Started by Chinmaye, 10th July 2019 10:51
    • Replies: 1
    • Views: 150
    10th July 2019, 17:34 Go to last post
  11. pins of symbol and layout do not match

    Started by abdoboua, 9th July 2019 12:01
    • Replies: 4
    • Views: 281
    9th July 2019, 21:59 Go to last post
  12. Help in understanding innovus

    Started by Chinmaye, 5th July 2019 06:56
    • Replies: 5
    • Views: 530
    9th July 2019, 14:30 Go to last post
    • Replies: 2
    • Views: 194
    8th July 2019, 15:51 Go to last post
  13. Clock Buffer Questions

    Started by promach, 8th July 2019 15:26
    • Replies: 0
    • Views: 170
    8th July 2019, 15:26 Go to last post
  14. problem when zooming to see layers

    Started by abdoboua, 5th July 2019 11:23
    • Replies: 7
    • Views: 456
    8th July 2019, 14:11 Go to last post
    • Replies: 6
    • Views: 525
    7th July 2019, 14:35 Go to last post
  15. Getting an error in icc2_shell. Need help

    Started by nitheeshm, 6th July 2019 21:57
    • Replies: 0
    • Views: 242
    6th July 2019, 21:57 Go to last post
  16. [SOLVED] Timing slack showing Unconstrained after synthesis in genus

    Started by Chinmaye, 4th July 2019 08:37
    • Replies: 5
    • Views: 341
    5th July 2019, 14:08 Go to last post
  17. Asynchronous Scan clocks

    Started by Varun124, 3rd July 2019 20:17
    • Replies: 1
    • Views: 205
    4th July 2019, 19:33 Go to last post
    • Replies: 2
    • Views: 251
    3rd July 2019, 18:13 Go to last post
    • Replies: 0
    • Views: 206
    3rd July 2019, 17:18 Go to last post
  18. [SOLVED] How to load an already compiled design in Design Compiler?

    Started by asic_architect, 23rd June 2019 08:26
    • Replies: 3
    • Views: 356
    3rd July 2019, 09:26 Go to last post
  19. Problem when starting cadence virtuoso

    Started by abdoboua, 2nd July 2019 06:13
    • Replies: 1
    • Views: 168
    2nd July 2019, 12:57 Go to last post