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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. [SOLVED]Closed: Synposys Tcyc not observed

    Started by blindscience, 19th June 2019 18:29
    • Replies: 1
    • Views: 647
    21st June 2019, 18:24 Go to last post
  2. Closed: Ripple-borrow binary subtraction circuit

    Started by promach, 20th June 2019 08:52
    • Replies: 2
    • Views: 478
    20th June 2019, 15:55 Go to last post
  3. Closed: [Synopsys] ICC1 Multi-thread problem. plz help me.

    Started by sebas.lee, 20th June 2019 04:53
    • Replies: 0
    • Views: 330
    20th June 2019, 04:53 Go to last post
  4. Closed: How to clock gate in hierarchy?

    Started by DimitrisStathis, 17th June 2019 17:29
    • Replies: 5
    • Views: 710
    18th June 2019, 18:06 Go to last post
  5. Closed: Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 4
    • Views: 674
    18th June 2019, 09:29 Go to last post
    • Replies: 2
    • Views: 628
    18th June 2019, 09:18 Go to last post
  6. Closed: Coverage improvement from AU.TC faults

    Started by aakashaspires, 17th June 2019 08:59
    • Replies: 1
    • Views: 377
    17th June 2019, 16:17 Go to last post
  7. Closed: meaning of placeable cells

    Started by sharanbr123, 14th June 2019 12:52
    • Replies: 2
    • Views: 460
    14th June 2019, 17:23 Go to last post
    • Replies: 1
    • Views: 432
    13th June 2019, 14:50 Go to last post
  8. Closed: TimeDesign in innovus with value 0 of Shift Phase

    Started by chineselboy, 12th June 2019 03:37
    • Replies: 1
    • Views: 555
    12th June 2019, 14:16 Go to last post
    • Replies: 0
    • Views: 338
    12th June 2019, 09:00 Go to last post
  9. Closed: ATPG Test Coverage for stuck@ and @speed

    Started by sandy2811, 25th March 2019 15:08
    • Replies: 3
    • Views: 689
    11th June 2019, 07:16 Go to last post
  10. Closed: What is Tranisition Delay and Path Delay Fault models in DFT ATPG?

    Started by Nanda_DFT, 19th February 2019 07:03
    • Replies: 1
    • Views: 483
    11th June 2019, 07:07 Go to last post
  11. Closed: [moved] Digital Transition Capture

    Started by minhchau, 8th June 2019 16:40
    • Replies: 11
    • Views: 1,227
    10th June 2019, 19:40 Go to last post
  12. Closed: Delay a signal in a system verilog testbench using jaspergold

    Started by haammzzaa, 10th June 2019 13:29
    • Replies: 4
    • Views: 679
    10th June 2019, 16:01 Go to last post
  13. [SOLVED]Closed: How to re-synthesize a circuit with ABC synthesizer?

    Started by amin-ea, 25th May 2019 12:06
    • Replies: 5
    • Views: 804
    10th June 2019, 08:40 Go to last post
  14. [SOLVED]Closed: Methodology to calculate the Clock Uncertainity values.

    Started by Wyre, 9th June 2019 10:35
    • Replies: 1
    • Views: 373
    9th June 2019, 16:13 Go to last post
    • Replies: 1
    • Views: 561
    6th June 2019, 19:18 Go to last post
  15. Closed: System verilog, fork join_any

    Started by surerdra, 4th June 2019 08:49
    • Replies: 3
    • Views: 714
    5th June 2019, 07:05 Go to last post
  16. Closed: Add output signal to reliability analysis virtuoso-cadence

    Started by antlhem, 31st May 2019 12:11
    • Replies: 2
    • Views: 566
    3rd June 2019, 15:19 Go to last post
    • Replies: 1
    • Views: 443
    2nd June 2019, 21:31 Go to last post
  17. Closed: Optimizing case statement with large input

    Started by stanford, 30th May 2019 03:01
    • Replies: 8
    • Views: 1,335
    1st June 2019, 02:42 Go to last post
  18. Closed: if/else vs. if/if in combo logic

    Started by stanford, 30th May 2019 02:09
    • Replies: 10
    • Views: 1,103
    1st June 2019, 02:39 Go to last post
  19. Closed: Overloading Arithmethic operators in Design Compiler

    Started by javierh.santiago, 31st May 2019 17:57
    • Replies: 2
    • Views: 631
    1st June 2019, 01:46 Go to last post
  20. [SOLVED]Closed: Code coverage of a design

    Started by vyella1, 31st May 2019 04:12
    • Replies: 1
    • Views: 473
    31st May 2019, 15:50 Go to last post
  21. Closed: blocking assignment in always_comb

    Started by stanford, 28th May 2019 04:25
    • Replies: 3
    • Views: 595
    28th May 2019, 19:22 Go to last post
    • Replies: 9
    • Views: 1,145
    28th May 2019, 14:05 Go to last post
  22. Closed: Need to Make Monte Carlo Simulation fast

    Started by Syfulcste, 23rd May 2019 03:18
    • Replies: 9
    • Views: 1,784
    27th May 2019, 02:27 Go to last post
  23. [SOLVED]Closed: Innovus changing pin connections

    Started by Alexxk, 20th May 2019 13:08
    • Replies: 6
    • Views: 1,672
    22nd May 2019, 16:50 Go to last post