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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Closed: [AHB] How connect Memory?

    Started by ivlsi, 25th July 2014 21:42
    • Replies: 9
    • Views: 1,146
    18th August 2014, 19:11 Go to last post
    • Replies: 10
    • Views: 1,365
    18th August 2014, 13:37 Go to last post
  2. Closed: simulation failed with elc

    Started by hatame, 18th August 2014 07:39
    • Replies: 0
    • Views: 726
    18th August 2014, 07:39 Go to last post
  3. Closed: problem having fixed.pkg in VHDL

    Started by nick123, 16th August 2014 11:45
    • Replies: 2
    • Views: 1,004
    18th August 2014, 06:43 Go to last post
  4. Closed: AMBA AHB Specifications

    Started by ivlsi, 16th August 2014 00:03
    • Replies: 1
    • Views: 840
    16th August 2014, 00:33 Go to last post
  5. Closed: How to distinguish always on gates in power off block?

    Started by RCircuit, 14th August 2014 23:38
    • Replies: 2
    • Views: 606
    16th August 2014, 00:13 Go to last post
  6. Closed: How to change the fractional point between two sfixed numbers in VHDL

    Started by brou, 15th August 2014 18:34
    • Replies: 0
    • Views: 589
    15th August 2014, 18:34 Go to last post
  7. Closed: Extracting area-delay pareto curve using Design compiler

    Started by ifforums, 15th August 2014 15:36
    • Replies: 1
    • Views: 591
    15th August 2014, 16:36 Go to last post
  8. Closed: Dynamic power is reduced when I increased frequency

    Started by makanaky, 12th July 2014 17:29
    • Replies: 9
    • Views: 1,215
    15th August 2014, 16:33 Go to last post
  9. [SOLVED]Closed: Difference between PVS and Assura check ?

    Started by Prashanthanilm, 9th July 2014 08:09
    • Replies: 1
    • Views: 5,327
    15th August 2014, 16:05 Go to last post
  10. Closed: Connecting to an unpacked array in System verilog

    Started by lostinxlation, 14th August 2014 23:53
    • Replies: 9
    • Views: 5,738
    15th August 2014, 04:08 Go to last post
  11. [SOLVED]Closed: orientation propert in SOC encounter

    Started by vahey, 13th August 2014 08:23
    • Replies: 3
    • Views: 843
    14th August 2014, 13:52 Go to last post
    • Replies: 0
    • Views: 550
    14th August 2014, 13:45 Go to last post
  12. Closed: Hold and Setup failures during Silicon Testing

    Started by priyutiru, 13th August 2014 22:01
    • Replies: 1
    • Views: 793
    13th August 2014, 22:31 Go to last post
  13. Closed: Silicon Scan Chain testing

    Started by priyutiru, 13th August 2014 22:03
    • Replies: 1
    • Views: 600
    13th August 2014, 22:29 Go to last post
  14. Closed: Real to decimal number conversion in VHDL

    Started by raghava216, 12th August 2014 12:28
    • Replies: 6
    • Views: 1,545
    13th August 2014, 15:49 Go to last post
  15. Closed: Conflicting exceptions - False path and Multicycle Path

    Started by harpv, 12th August 2014 07:18
    • Replies: 4
    • Views: 1,453
    13th August 2014, 06:29 Go to last post
    • Replies: 7
    • Views: 1,375
    13th August 2014, 06:25 Go to last post
    • Replies: 5
    • Views: 3,247
    13th August 2014, 06:23 Go to last post
  16. Closed: can anyone explain how scan works?

    Started by liletian, 8th August 2014 23:15
    • Replies: 1
    • Views: 822
    13th August 2014, 00:49 Go to last post
  17. Closed: [Interview] Low Power Design Methodologies

    Started by ivlsi, 1st November 2012 23:49
    • Replies: 7
    • Views: 4,671
    13th August 2014, 00:24 Go to last post
  18. Closed: An Error reported by DesignCompiler

    Started by RadHard, 12th August 2014 18:27
    • Replies: 1
    • Views: 651
    13th August 2014, 00:15 Go to last post
  19. Closed: Large Negative incr_delay causing hold violation

    Started by jdemma, 12th August 2014 16:02
    • Replies: 0
    • Views: 529
    12th August 2014, 16:02 Go to last post
    • Replies: 5
    • Views: 1,387
    12th August 2014, 07:39 Go to last post
  20. Closed: design of cache ways in w-way set associative cache

    Started by ssubha, 12th August 2014 07:32
    • Replies: 0
    • Views: 927
    12th August 2014, 07:32 Go to last post
  21. Closed: Synopsys VCS UCLI debugger

    Started by invlsi, 12th August 2014 05:48
    • Replies: 0
    • Views: 1,388
    12th August 2014, 05:48 Go to last post
  22. Closed: why metastablity state finally changes to the steady state?

    Started by Siva Teja, 7th August 2014 05:23
    • Replies: 3
    • Views: 932
    11th August 2014, 15:03 Go to last post
  23. Closed: clock frequency in hold time

    Started by rakesh@981, 6th August 2014 19:44
    • Replies: 2
    • Views: 742
    11th August 2014, 14:56 Go to last post
  24. Closed: cycle time, slew and slack

    Started by yannik33, 1st August 2014 13:02
    • Replies: 1
    • Views: 1,112
    11th August 2014, 14:43 Go to last post
  25. Closed: High Frequecy physical desgin challenges

    Started by Gaurav.jain88, 30th June 2014 16:45
    • Replies: 1
    • Views: 863
    10th August 2014, 09:03 Go to last post