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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,033
    25th March 2007, 08:41 Go to last post
  1. Closed: how to access e books in the internet?

    Started by , 8th April 2003 12:42
    • Replies: 0
    • Views: 1,170
    8th April 2003, 12:42 Go to last post
  2. Links to ASIC books for beginners

    Started by , 24th April 2003 07:36
    • Replies: 2
    • Views: 1,695
    25th April 2003, 03:55 Go to last post
  3. who can recommend a book on asic design

    Started by , 14th July 2003 12:57
    • Replies: 10
    • Views: 6,083
    7th June 2005, 08:16 Go to last post
  4. Closed: Looking for cocentric SystemC

    Started by , 17th July 2003 18:44
    • Replies: 7
    • Views: 2,672
    27th November 2003, 07:03 Go to last post
  5. What's the difference between micom and asic?

    Started by , 6th February 2008 00:05
    • Replies: 0
    • Views: 933
    6th February 2008, 00:05 Go to last post
  6. Closed: About SPEF,SBPF,DSPF,SDF

    Started by , 19th February 2008 13:44
    • Replies: 0
    • Views: 2,153
    19th February 2008, 13:44 Go to last post
  7. Closed: what is your best VHDL program?

    Started by 020170, 31st January 2005 19:13
    • Replies: 4
    • Views: 1,813
    1st February 2005, 01:28 Go to last post
  8. Closed: Can I create a netlist from GHDL?

    Started by 020170, 10th June 2005 18:33
    • Replies: 1
    • Views: 1,418
    11th June 2005, 02:23 Go to last post
  9. Closed: what does means this digital symbol?

    Started by 020170, 3rd April 2006 02:56
    • Replies: 4
    • Views: 1,779
    4th April 2006, 15:05 Go to last post
  10. Closed: what is "loop delay"?

    Started by 020170, 11th May 2007 05:06
    • Replies: 5
    • Views: 1,830
    11th May 2007, 10:55 Go to last post
  11. Closed: how to connect to irs2110

    Started by 100k, 9th March 2013 12:46
    • Replies: 0
    • Views: 1,174
    9th March 2013, 12:46 Go to last post
    • Replies: 5
    • Views: 2,341
    15th June 2005, 13:59 Go to last post
  12. Closed: Question in CTS of Astro:ov cannot legalize cell

    Started by 114142500, 11th August 2010 07:12
    • Replies: 0
    • Views: 1,389
    11th August 2010, 07:12 Go to last post
  13. Closed: what do you mean my 45nm in vlsi?

    Started by 1189raji, 4th March 2012 07:58
    • Replies: 3
    • Views: 1,678
    5th March 2012, 02:55 Go to last post
  14. Closed: SPI slew rate verification and integration

    Started by 123dhruv123, 17th October 2012 06:30
    • Replies: 0
    • Views: 888
    17th October 2012, 06:30 Go to last post
  15. Closed: Novice looking for pointers - design simple cpu

    Started by 123jack, 15th March 2016 15:06
    • Replies: 6
    • Views: 984
    15th March 2016, 23:47 Go to last post
  16. Closed: How to idenfity the ethernet frame data belong to which frame ?

    Started by 123zxc123, 25th January 2011 09:24
    • Replies: 2
    • Views: 1,494
    25th January 2011, 10:14 Go to last post
  17. Closed: cadence tool digital design

    Started by 173, 18th December 2017 12:34
    • Replies: 3
    • Views: 1,362
    19th December 2017, 15:50 Go to last post
  18. Closed: 0.6um AMS SPICE model for NMOS and PMOS

    Started by 2000, 17th May 2003 20:28
    • Replies: 5
    • Views: 3,146
    21st May 2003, 04:00 Go to last post
  19. Closed: ultrasonic transceiver switch

    Started by 24+, 18th February 2010 10:53
    • Replies: 8
    • Views: 2,599
    29th July 2010, 16:38 Go to last post
  20. Closed: some problem with Nanosim and VCS

    Started by 290702500, 1st July 2009 07:21
    • Replies: 0
    • Views: 1,064
    1st July 2009, 07:21 Go to last post
  21. Closed: speed and performance of a design

    Started by 2M, 31st August 2007 15:18
    • Replies: 1
    • Views: 1,009
    1st September 2007, 08:02 Go to last post
  22. Closed: HSPICE: Monte Carlo Simulation for CMOS widths

    Started by 2wice, 23rd April 2014 04:28
    • Replies: 1
    • Views: 1,600
    30th April 2014, 16:57 Go to last post
  23. Closed: Where can download S_Y_NOPSYS AMBA OCB Designware

    Started by 2xuillji, 25th May 2003 17:22
    • Replies: 3
    • Views: 2,595
    21st July 2003, 07:56 Go to last post
    • Replies: 2
    • Views: 897
    18th April 2013, 06:59 Go to last post
  24. Closed: what does hold time check mean in Design Compiler?

    Started by 39123811, 10th July 2013 04:22
    • Replies: 1
    • Views: 1,266
    11th July 2013, 00:25 Go to last post
  25. Closed: Nanosim Warning(DELC-004)

    Started by 3purple, 8th November 2011 07:07
    • Replies: 0
    • Views: 1,197
    8th November 2011, 07:07 Go to last post
  26. Closed: 6T Sram cell modeling

    Started by 3wais, 18th February 2013 01:50
    • Replies: 2
    • Views: 808
    18th February 2013, 14:30 Go to last post
  27. [SOLVED]Closed: Synopsys IC Compiler vs Custom Designer

    Started by 3wais, 2nd August 2013 16:42
    • Replies: 4
    • Views: 2,551
    3rd August 2013, 01:34 Go to last post