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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,562
    25th March 2007, 08:41 Go to last post
  1. Closed: How to initialize an array structure in verilog?

    Started by yuenkit, 15th March 2006 12:30
    • Replies: 19
    • Views: 133,931
    26th September 2012, 13:56 Go to last post
  2. Closed: NPI Engineer. what it does mean????

    Started by khaila, 23rd January 2007 00:16
    • Replies: 1
    • Views: 103,864
    23rd January 2007, 12:39 Go to last post
  3. How to declare two dimensional input ports in Verilog?

    Started by barkha, 21st November 2006 07:23
    • Replies: 11
    • Views: 87,587
    19th August 2013, 16:12 Go to last post
  4. Closed: Verilog While loop,For loop is synthesisable????

    Started by ankit12345, 29th January 2007 04:39
    2 Pages
    1 2
    • Replies: 36
    • Views: 84,966
    12th October 2010, 23:12 Go to last post
  5. Closed: What is the setup and hold time?

    Started by sachinmaheshwari, 11th August 2007 07:15
    • Replies: 16
    • Views: 83,850
    21st October 2010, 07:58 Go to last post
  6. Closed: difference between using signals and variables in vhdl

    Started by s3034585, 31st May 2004 09:28
    • Replies: 10
    • Views: 76,842
    11th August 2005, 18:49 Go to last post
  7. Closed: Difference between Block RAM and Distributed RAM in FPGA

    Started by richardyue, 3rd November 2006 11:45
    • Replies: 17
    • Views: 75,852
    11th October 2010, 15:10 Go to last post
  8. Closed: What does the precision value in Verilog Timescale represent?

    Started by verma.ind, 13th July 2007 10:57
    • Replies: 7
    • Views: 75,180
    31st March 2011, 06:48 Go to last post
  9. Closed: Mealy vs Moore Design

    Started by tronix, 22nd July 2006 09:35
    2 Pages
    1 2
    • Replies: 33
    • Views: 67,578
    24th August 2013, 14:12 Go to last post
  10. Closed: Fixing Setup & Hold Violations

    Started by carrot, 3rd January 2007 06:04
    2 Pages
    1 2
    • Replies: 33
    • Views: 67,257
    25th May 2012, 06:35 Go to last post
  11. Closed: what is clock latency and clock uncertainty

    Started by vamsi_addagada, 10th July 2008 11:50
    • Replies: 17
    • Views: 66,220
    14th April 2013, 07:26 Go to last post
  12. Closed: How to force a signal to certain value from Verilog testbench?

    Started by gold_kiss, 14th September 2004 13:54
    • Replies: 10
    • Views: 65,397
    27th October 2004, 12:09 Go to last post
  13. Closed: RACE AROUND CONDITION

    Started by bala9383, 20th March 2008 10:20
    • Replies: 5
    • Views: 64,683
    7th March 2012, 15:39 Go to last post
  14. Closed: Verilog - generate multiple interconnected modules

    Started by ktsangop, 2nd April 2008 15:39
    2 Pages
    1 2
    • Replies: 21
    • Views: 63,228
    3rd November 2011, 03:34 Go to last post
  15. Closed: What's the difference between behavioral and structural in vhdl?

    Started by iVenky, 29th July 2012 15:56
    • Replies: 3
    • Views: 61,293
    2nd August 2012, 18:40 Go to last post
  16. Closed: What's the best VHDL/Verilog/SystemVerilog editor?

    Started by darylz, 19th February 2007 04:40
    5 Pages
    1 2 3 ... 5
    • Replies: 96
    • Views: 58,881
    7th July 2010, 04:59 Go to last post
    • Replies: 15
    • Views: 58,745
    23rd January 2012, 06:56 Go to last post
  17. Closed: What is the setup and hold time?

    Started by richardyue, 10th November 2006 14:42
    3 Pages
    1 2 3
    • Replies: 56
    • Views: 58,447
    27th October 2013, 14:45 Go to last post
  18. Closed: what are level shifters?

    Started by deh_fuhrer, 31st May 2007 12:34
    • Replies: 11
    • Views: 57,373
    14th June 2007, 10:31 Go to last post
  19. Clock divider by 3 with 50% duty cycle?

    Started by davyzhu, 17th October 2005 08:49
    2 Pages
    1 2
    • Replies: 33
    • Views: 57,016
    7th December 2012, 19:07 Go to last post
  20. Closed: How to create a sine wave with verilog ?

    Started by feel_on_on, 5th June 2005 15:48
    2 Pages
    1 2
    • Replies: 34
    • Views: 54,389
    4th May 2013, 20:17 Go to last post
  21. Closed: SRL,ROR,... operator in VHDL

    Started by roger, 18th June 2004 08:14
    • Replies: 10
    • Views: 51,898
    1st July 2004, 14:54 Go to last post
  22. Closed: Difference between linear element and non-linear element

    Started by bala9383, 22nd March 2008 06:38
    • Replies: 9
    • Views: 50,623
    24th July 2014, 10:51 Go to last post
  23. Closed: How to write a logic in Verilog for creating a latch?

    Started by r_p_sanna, 19th March 2006 18:35
    • Replies: 11
    • Views: 50,216
    23rd January 2012, 15:40 Go to last post
  24. Closed: What is an IR drop and what causes it?

    Started by drizzle, 10th June 2006 12:33
    • Replies: 3
    • Views: 48,784
    10th June 2006, 15:58 Go to last post
  25. Closed: Conditional Instantiation of a Module in Verilog

    Started by omara007, 31st August 2008 09:43
    • Replies: 12
    • Views: 48,485
    9th March 2009, 08:13 Go to last post
  26. Closed: AND gate using XOR gate

    Started by spauls, 29th July 2005 11:26
    • Replies: 13
    • Views: 43,104
    18th August 2005, 12:59 Go to last post
  27. Closed: Difference btw Back end and Front end in VLSI

    Started by shivapugal, 11th August 2009 14:53
    • Replies: 5
    • Views: 43,041
    12th August 2009, 12:43 Go to last post
  28. Closed: What r the responsibilities of field Application Engineer

    Started by adityakant, 8th September 2006 06:39
    • Replies: 7
    • Views: 41,883
    26th March 2013, 20:33 Go to last post
    • Replies: 9
    • Views: 41,052
    27th October 2005, 03:06 Go to last post