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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,443
    25th March 2007, 08:41 Go to last post
  1. Closed: what is hot-topic in digital design now?

    Started by eexuke, 25th May 2004 07:15
    8 Pages
    1 2 3 ... 8
    • Replies: 157
    • Views: 24,833
    24th August 2007, 08:39 Go to last post
  2. Closed: VHDL vs Verilog which more popular?

    Started by cadb0y, 9th March 2002 18:13
    6 Pages
    1 2 3 ... 6
    • Replies: 113
    • Views: 20,047
    21st April 2004, 03:35 Go to last post
  3. Poll: Closed: VCS, NC-Verilog and Modelsim, which is the best simulator??

    Started by always@smart, 24th September 2003 08:59
    6 Pages
    1 2 3 ... 6
    • Replies: 101
    • Views: 23,765
    15th April 2005, 08:30 Go to last post
  4. Poll: Closed: PLease Vote: Electronics Engineer Vs Computer Engineer

    Started by nan_ishan, 14th December 2007 11:48
    6 Pages
    1 2 3 ... 6
    • Replies: 101
    • Views: 17,081
    24th June 2008, 10:36 Go to last post
  5. Closed: What's the best VHDL/Verilog/SystemVerilog editor?

    Started by darylz, 19th February 2007 04:40
    5 Pages
    1 2 3 ... 5
    • Replies: 96
    • Views: 59,599
    7th July 2010, 04:59 Go to last post
  6. Closed: What is the syntax of calling a procedure in TCL?

    Started by sun_ray, 31st August 2012 09:03
    4 Pages
    1 2 3 ... 4
    • Replies: 79
    • Views: 8,083
    14th September 2012, 10:22 Go to last post
  7. Closed: discrete fourier transform basics

    Started by nittinsharma80, 1st July 2005 12:25
    4 Pages
    1 2 3 ... 4
    • Replies: 73
    • Views: 29,637
    10th January 2009, 22:09 Go to last post
  8. Closed: SystemC , Systemverilog , vera , specman...

    Started by roadrunner, 28th September 2003 07:37
    4 Pages
    1 2 3 ... 4
    • Replies: 69
    • Views: 17,521
    6th January 2010, 13:24 Go to last post
  9. Closed: Why nobody has interest in DFT?

    Started by prisnow, 27th March 2002 05:55
    4 Pages
    1 2 3 ... 4
    • Replies: 64
    • Views: 13,992
    4th January 2007, 07:51 Go to last post
  10. Closed: how to practice PERL language

    Started by rakesh_aadhimoolam, 23rd August 2006 06:15
    3 Pages
    1 2 3
    • Replies: 59
    • Views: 9,714
    1st November 2007, 08:40 Go to last post
  11. Closed: What kind of ASIC designer is better off, frontend or backend?

    Started by steven852, 3rd August 2006 02:09
    3 Pages
    1 2 3
    • Replies: 56
    • Views: 16,783
    21st March 2012, 10:26 Go to last post
  12. Closed: What is the setup and hold time?

    Started by richardyue, 10th November 2006 14:42
    3 Pages
    1 2 3
    • Replies: 56
    • Views: 58,933
    27th October 2013, 14:45 Go to last post
  13. Closed: NAND or NOR is faster

    Started by amara, 9th June 2006 08:07
    3 Pages
    1 2 3
    • Replies: 54
    • Views: 12,682
    16th January 2007, 18:45 Go to last post
  14. Closed: blocking nature of blocking statements are not cared here-why?

    Started by ASIC_int, 11th June 2011 12:23
    3 Pages
    1 2 3
    • Replies: 53
    • Views: 4,604
    5th January 2012, 14:34 Go to last post
  15. [SOLVED]Closed: 3-digit Frequency Counter

    Started by Eshal, 15th April 2013 16:49
    3 Pages
    1 2 3
    • Replies: 53
    • Views: 17,411
    29th April 2013, 18:07 Go to last post
  16. Closed: How to write a script for synthesis

    Started by tutx, 6th October 2004 16:18
    3 Pages
    1 2 3
    • Replies: 47
    • Views: 12,752
    29th June 2012, 16:54 Go to last post
  17. Closed: Analog IC design in Windows environment

    Started by mwpro, 7th June 2003 07:28
    3 Pages
    1 2 3
    • Replies: 46
    • Views: 11,122
    23rd November 2010, 00:12 Go to last post
  18. Poll: VHDL and Verilog which one you use more often?

    Started by always@smart, 28th January 2003 02:54
    3 Pages
    1 2 3
    • Replies: 45
    • Views: 6,904
    2nd April 2004, 16:28 Go to last post
  19. Closed: Which country has best opportunities (work and Pay) in VLSI

    Started by kanagavel_docs, 25th October 2007 05:36
    3 Pages
    1 2 3
    • Replies: 45
    • Views: 24,927
    21st June 2009, 18:40 Go to last post
  20. A Revolutionary Massively Parallel Processing Architecture

    Started by paulpawlenko, 14th July 2018 01:16
    3 Pages
    1 2 3
    • Replies: 44
    • Views: 4,018
    24th July 2018, 01:41 Go to last post
  21. Closed: What is better for a digital designer: Cadence or Synopsis?

    Started by etherios, 18th January 2004 16:37
    3 Pages
    1 2 3
    • Replies: 42
    • Views: 32,216
    3rd April 2007, 07:40 Go to last post
  22. Closed: SystemC will die? Why, can anybody give an explain?

    Started by bigrice911, 21st June 2004 16:51
    3 Pages
    1 2 3
    • Replies: 42
    • Views: 5,898
    27th January 2008, 21:38 Go to last post
  23. Closed: lint tools for verilog

    Started by raju, 11th July 2004 21:20
    3 Pages
    1 2 3
    • Replies: 41
    • Views: 26,931
    30th October 2005, 13:19 Go to last post
  24. Closed: synopsys design compiler workshop

    Started by roger, 12th April 2005 10:41
    3 Pages
    1 2 3
    • Replies: 41
    • Views: 21,574
    12th March 2010, 07:56 Go to last post
  25. Closed: $ynplify ASIC vs. Design C0mpiler

    Started by joe2moon, 20th December 2002 16:25
    3 Pages
    1 2 3
    • Replies: 40
    • Views: 10,106
    22nd December 2005, 16:10 Go to last post
  26. Closed: which is better to use : Registers or RAM ?

    Started by omara007, 19th September 2005 08:59
    3 Pages
    1 2 3
    • Replies: 40
    • Views: 5,089
    6th October 2005, 18:36 Go to last post
  27. Closed: VLSI career in Bangalore & Schools on VLSI

    Started by honnaraj.t, 14th January 2008 12:12
    3 Pages
    1 2 3
    • Replies: 40
    • Views: 9,129
    9th May 2012, 14:28 Go to last post
  28. Closed: How to delay a clock signal having a period T by T/4 ?

    Started by master_picengineer, 31st January 2008 13:54
    3 Pages
    1 2 3
    • Replies: 40
    • Views: 9,948
    5th September 2008, 12:42 Go to last post
  29. Closed: Opinions on VCS 7.0 software

    Started by DeepIC, 1st January 2003 14:34
    2 Pages
    1 2
    • Replies: 39
    • Views: 12,519
    25th August 2005, 20:47 Go to last post
  30. [SOLVED]Closed: synopsys design compiler error: mismatch signals width

    Started by soloktanjung, 6th July 2011 09:28
    2 Pages
    1 2
    • Replies: 38
    • Views: 9,023
    21st April 2012, 12:23 Go to last post