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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,799
    25th March 2007, 08:41 Go to last post
    • Replies: 1
    • Views: 164
    Today, 16:16 Go to last post
  1. TSMC LVS errors after sealring

    Started by AllenD, Yesterday 08:50
    • Replies: 1
    • Views: 122
    Today, 16:14 Go to last post
  2. Innovus changing pin connections

    Started by Alexxk, Today 13:08
    • Replies: 1
    • Views: 65
    Today, 16:12 Go to last post
    • Replies: 0
    • Views: 114
    17th May 2019, 17:23 Go to last post
  3. [SOLVED] Hz vs number of bits

    Started by tahirsengine, 3rd May 2019 11:47
    • Replies: 6
    • Views: 418
    17th May 2019, 06:42 Go to last post
  4. LEC at top level of a SOC

    Started by fragnen, 7th May 2019 14:22
    • Replies: 1
    • Views: 134
    17th May 2019, 06:28 Go to last post
  5. How does Foundry provide different Process Models?

    Started by Wyre, 13th May 2019 09:22
    • Replies: 1
    • Views: 210
    13th May 2019, 16:35 Go to last post
  6. recovery time of sync reset vs. async reset

    Started by stanford, 9th May 2019 02:29
    • Replies: 5
    • Views: 2,071
    9th May 2019, 18:36 Go to last post
  7. TSMC 65nm Calibre dummy insertion tool

    Started by AllenD, 5th May 2019 11:36
    • Replies: 8
    • Views: 2,904
    9th May 2019, 09:26 Go to last post
  8. synthesizing memory as latches

    Started by vyella1, 8th May 2019 17:19
    • Replies: 1
    • Views: 688
    8th May 2019, 18:23 Go to last post
  9. How to create *.mpf in the "middle of work"?

    Started by ldm.eth, 5th May 2019 14:59
    • Replies: 0
    • Views: 84
    5th May 2019, 14:59 Go to last post
  10. How PA/PTPX handle analog macro

    Started by tarkyss, 5th May 2019 10:11
    • Replies: 0
    • Views: 104
    5th May 2019, 10:11 Go to last post
    • Replies: 2
    • Views: 232
    3rd May 2019, 17:13 Go to last post
  11. How to use the verilog obfuscator?

    Started by nagulapatigirireddy, 2nd May 2019 14:54
    • Replies: 3
    • Views: 282
    3rd May 2019, 16:41 Go to last post
  12. DC Optimize Registers message

    Started by mwb, 1st May 2019 17:22
    • Replies: 0
    • Views: 229
    1st May 2019, 17:22 Go to last post
  13. Design Compiler Register Retiming and CDC

    Started by mwb, 24th April 2019 10:48
    • Replies: 2
    • Views: 1,209
    1st May 2019, 17:13 Go to last post
    • Replies: 7
    • Views: 3,902
    1st May 2019, 10:41 Go to last post
  14. Writing ModelSim do files

    Started by tahirsengine, 18th April 2019 07:54
    • Replies: 3
    • Views: 646
    26th April 2019, 15:02 Go to last post
    • Replies: 1
    • Views: 249
    25th April 2019, 06:20 Go to last post
  15. 32x32 Single Cycle Fast Multiplier

    Started by Mr.PAP, 18th April 2019 12:56
    • Replies: 10
    • Views: 6,688
    24th April 2019, 06:25 Go to last post
  16. Synth. area reduced when adding a pipeline register

    Started by oAwad, 22nd April 2019 22:02
    • Replies: 4
    • Views: 1,535
    23rd April 2019, 14:56 Go to last post
  17. priority on two asynch triggered events

    Started by stanford, 18th April 2019 23:50
    • Replies: 13
    • Views: 2,024
    22nd April 2019, 18:14 Go to last post
  18. what $finish will be sythesis to in verilog?

    Started by liletian, 21st April 2019 19:05
    • Replies: 5
    • Views: 328
    22nd April 2019, 15:54 Go to last post
  19. Generated clocks in design compiler

    Started by xdaanx, 20th April 2019 12:52
    • Replies: 0
    • Views: 210
    20th April 2019, 12:52 Go to last post
  20. 6T SRAM read/write current

    Started by Windywast, 18th April 2019 20:30
    • Replies: 2
    • Views: 203
    18th April 2019, 22:03 Go to last post
    • Replies: 3
    • Views: 2,254
    16th April 2019, 18:10 Go to last post