1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    119,274
Page 1 of 812 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24331

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,815
    25th March 2007, 08:41 Go to last post
  1. [SOLVED] Innovus changing pin connections

    Started by Alexxk, 20th May 2019 13:08
    • Replies: 5
    • Views: 278
    Today, 11:57 Go to last post
    • Replies: 2
    • Views: 160
    Today, 02:17 Go to last post
  2. Multiple sources for a clock

    Started by kishoresai1996, Yesterday 18:04
    • Replies: 1
    • Views: 77
    Yesterday, 19:16 Go to last post
  3. Handling LEC for multibit flipflop

    Started by fragnen, 3rd April 2019 14:47
    • Replies: 1
    • Views: 368
    Yesterday, 06:55 Go to last post
  4. Hierarchical and Flat LEC

    Started by fragnen, 5th April 2019 08:37
    • Replies: 1
    • Views: 349
    Yesterday, 06:54 Go to last post
    • Replies: 1
    • Views: 243
    20th May 2019, 16:16 Go to last post
  5. TSMC LVS errors after sealring

    Started by AllenD, 19th May 2019 08:50
    • Replies: 1
    • Views: 199
    20th May 2019, 16:14 Go to last post
    • Replies: 6
    • Views: 486
    20th May 2019, 01:30 Go to last post
    • Replies: 0
    • Views: 126
    17th May 2019, 17:23 Go to last post
  6. [SOLVED] Hz vs number of bits

    Started by tahirsengine, 3rd May 2019 11:47
    • Replies: 6
    • Views: 419
    17th May 2019, 06:42 Go to last post
  7. LEC at top level of a SOC

    Started by fragnen, 7th May 2019 14:22
    • Replies: 1
    • Views: 137
    17th May 2019, 06:28 Go to last post
  8. How does Foundry provide different Process Models?

    Started by Wyre, 13th May 2019 09:22
    • Replies: 1
    • Views: 212
    13th May 2019, 16:35 Go to last post
  9. recovery time of sync reset vs. async reset

    Started by stanford, 9th May 2019 02:29
    • Replies: 5
    • Views: 2,238
    9th May 2019, 18:36 Go to last post
  10. TSMC 65nm Calibre dummy insertion tool

    Started by AllenD, 5th May 2019 11:36
    • Replies: 8
    • Views: 3,083
    9th May 2019, 09:26 Go to last post
  11. synthesizing memory as latches

    Started by vyella1, 8th May 2019 17:19
    • Replies: 1
    • Views: 747
    8th May 2019, 18:23 Go to last post
  12. How to create *.mpf in the "middle of work"?

    Started by ldm.eth, 5th May 2019 14:59
    • Replies: 0
    • Views: 84
    5th May 2019, 14:59 Go to last post
  13. How PA/PTPX handle analog macro

    Started by tarkyss, 5th May 2019 10:11
    • Replies: 0
    • Views: 106
    5th May 2019, 10:11 Go to last post
    • Replies: 2
    • Views: 232
    3rd May 2019, 17:13 Go to last post
  14. How to use the verilog obfuscator?

    Started by nagulapatigirireddy, 2nd May 2019 14:54
    • Replies: 3
    • Views: 282
    3rd May 2019, 16:41 Go to last post
  15. DC Optimize Registers message

    Started by mwb, 1st May 2019 17:22
    • Replies: 0
    • Views: 230
    1st May 2019, 17:22 Go to last post
  16. Design Compiler Register Retiming and CDC

    Started by mwb, 24th April 2019 10:48
    • Replies: 2
    • Views: 1,269
    1st May 2019, 17:13 Go to last post
    • Replies: 7
    • Views: 4,112
    1st May 2019, 10:41 Go to last post
  17. Writing ModelSim do files

    Started by tahirsengine, 18th April 2019 07:54
    • Replies: 3
    • Views: 649
    26th April 2019, 15:02 Go to last post
    • Replies: 1
    • Views: 249
    25th April 2019, 06:20 Go to last post
  18. 32x32 Single Cycle Fast Multiplier

    Started by Mr.PAP, 18th April 2019 12:56
    • Replies: 10
    • Views: 7,085
    24th April 2019, 06:25 Go to last post
  19. Synth. area reduced when adding a pipeline register

    Started by oAwad, 22nd April 2019 22:02
    • Replies: 4
    • Views: 1,597
    23rd April 2019, 14:56 Go to last post
  20. priority on two asynch triggered events

    Started by stanford, 18th April 2019 23:50
    • Replies: 13
    • Views: 2,026
    22nd April 2019, 18:14 Go to last post