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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,027
    25th March 2007, 08:41 Go to last post
  1. How to clock gate in hierarchy?

    Started by DimitrisStathis, 17th June 2019 17:29
    • Replies: 5
    • Views: 123
    Yesterday, 18:06 Go to last post
  2. Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 4
    • Views: 245
    Yesterday, 09:29 Go to last post
  3. Coverage improvement from AU.TC faults

    Started by aakashaspires, 17th June 2019 08:59
    • Replies: 1
    • Views: 70
    17th June 2019, 16:17 Go to last post
  4. meaning of placeable cells

    Started by sharanbr123, 14th June 2019 12:52
    • Replies: 2
    • Views: 151
    14th June 2019, 17:23 Go to last post
    • Replies: 1
    • Views: 154
    12th June 2019, 14:16 Go to last post
    • Replies: 0
    • Views: 93
    12th June 2019, 09:00 Go to last post
  5. ATPG Test Coverage for stuck@ and @speed

    Started by sandy2811, 25th March 2019 15:08
    • Replies: 3
    • Views: 304
    11th June 2019, 07:16 Go to last post
    • Replies: 1
    • Views: 193
    11th June 2019, 07:07 Go to last post
  6. [moved] Digital Transition Capture

    Started by minhchau, 8th June 2019 16:40
    • Replies: 11
    • Views: 445
    10th June 2019, 19:40 Go to last post
    • Replies: 4
    • Views: 143
    10th June 2019, 16:01 Go to last post
  7. [SOLVED] How to re-synthesize a circuit with ABC synthesizer?

    Started by amin-ea, 25th May 2019 12:06
    • Replies: 5
    • Views: 321
    10th June 2019, 08:40 Go to last post
  8. [SOLVED] Methodology to calculate the Clock Uncertainity values.

    Started by Wyre, 9th June 2019 10:35
    • Replies: 1
    • Views: 117
    9th June 2019, 16:13 Go to last post
  9. System verilog, fork join_any

    Started by surerdra, 4th June 2019 08:49
    • Replies: 3
    • Views: 269
    5th June 2019, 07:05 Go to last post
    • Replies: 2
    • Views: 232
    3rd June 2019, 15:19 Go to last post
  10. Optimizing case statement with large input

    Started by stanford, 30th May 2019 03:01
    • Replies: 8
    • Views: 671
    1st June 2019, 02:42 Go to last post
  11. if/else vs. if/if in combo logic

    Started by stanford, 30th May 2019 02:09
    • Replies: 10
    • Views: 462
    1st June 2019, 02:39 Go to last post
    • Replies: 2
    • Views: 375
    1st June 2019, 01:46 Go to last post
  12. Code coverage of a design

    Started by vyella1, 31st May 2019 04:12
    • Replies: 1
    • Views: 194
    31st May 2019, 15:50 Go to last post
  13. blocking assignment in always_comb

    Started by stanford, 28th May 2019 04:25
    • Replies: 3
    • Views: 268
    28th May 2019, 19:22 Go to last post
    • Replies: 9
    • Views: 467
    28th May 2019, 14:05 Go to last post
  14. Need to Make Monte Carlo Simulation fast

    Started by Syfulcste, 23rd May 2019 03:18
    • Replies: 9
    • Views: 1,147
    27th May 2019, 02:27 Go to last post
  15. [SOLVED] Innovus changing pin connections

    Started by Alexxk, 20th May 2019 13:08
    • Replies: 6
    • Views: 983
    22nd May 2019, 16:50 Go to last post
  16. Output of exors are showing x in EDA playground

    Started by sushl, 21st May 2019 11:58
    • Replies: 2
    • Views: 324
    22nd May 2019, 02:17 Go to last post