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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,324
    25th March 2007, 08:41 Go to last post
    • Replies: 3
    • Views: 102
    Today, 13:43 Go to last post
  1. Clock slew and data slew

    Started by sjt1003, Yesterday 05:52
    • Replies: 0
    • Views: 59
    Yesterday, 05:52 Go to last post
  2. Vcd to saif conversion

    Started by Swethav, 21st June 2018 12:14
    • Replies: 3
    • Views: 110
    21st June 2018, 14:48 Go to last post
  3. [SOLVED] Common POLY layer in the digital standard cells

    Started by ua6bqg, 19th June 2018 18:23
    • Replies: 7
    • Views: 117
    20th June 2018, 15:03 Go to last post
  4. Script for adding wires in Encounter

    Started by Mahmoud_Dagher, 19th June 2018 03:10
    • Replies: 4
    • Views: 97
    20th June 2018, 14:50 Go to last post
  5. Non clock cells on clock path

    Started by stanford, 18th June 2018 23:01
    • Replies: 4
    • Views: 128
    20th June 2018, 14:42 Go to last post
  6. Synopsys VP Virtualizer installation

    Started by yuhiub90, 19th June 2018 09:09
    • Replies: 0
    • Views: 51
    19th June 2018, 09:09 Go to last post
  7. async fifo - almost full/empty

    Started by stanford, 10th June 2018 08:24
    • Replies: 6
    • Views: 264
    19th June 2018, 00:53 Go to last post
    • Replies: 0
    • Views: 56
    19th June 2018, 00:33 Go to last post
    • Replies: 2
    • Views: 79
    18th June 2018, 22:42 Go to last post
  8. Memory/macro internal clock insertion delay

    Started by argha, 16th June 2018 20:12
    • Replies: 1
    • Views: 161
    18th June 2018, 14:17 Go to last post
  9. Import a layout from Encounter to Virtuoso

    Started by Mahmoud_Dagher, 14th June 2018 14:53
    • Replies: 5
    • Views: 223
    18th June 2018, 14:15 Go to last post
    • Replies: 1
    • Views: 97
    18th June 2018, 10:16 Go to last post
    • Replies: 2
    • Views: 165
    15th June 2018, 15:36 Go to last post
  10. SPI Slave with strange behavior

    Started by rmachado, 9th June 2018 13:59
    2 Pages
    1 2
    • Replies: 25
    • Views: 615
    15th June 2018, 10:57 Go to last post
  11. SDC constraints for asynchronous reset

    Started by Alexxk, 14th June 2018 12:04
    • Replies: 2
    • Views: 117
    15th June 2018, 10:36 Go to last post
  12. Timing Sign off from Primetime

    Started by sreejinair, 11th June 2018 14:38
    • Replies: 4
    • Views: 285
    12th June 2018, 15:33 Go to last post
  13. UMC 65nm without TLU+ files

    Started by ua6bqg, 8th June 2018 16:30
    • Replies: 1
    • Views: 136
    8th June 2018, 18:00 Go to last post
  14. [moved] Physical design placement timing issue

    Started by prabhu14, 7th June 2018 19:05
    • Replies: 2
    • Views: 183
    8th June 2018, 14:54 Go to last post
  15. Cadence lint error: CLKDMN

    Started by Sam26, 7th June 2018 10:45
    • Replies: 3
    • Views: 197
    8th June 2018, 12:37 Go to last post
  16. [moved] 50Mz to 1 kHz clock generator

    Started by sanjaysharmaiitk, 8th June 2018 09:26
    • Replies: 1
    • Views: 139
    8th June 2018, 10:14 Go to last post
    • Replies: 10
    • Views: 534
    4th June 2018, 11:41 Go to last post
  17. bit width for addition

    Started by sky_above, 2nd June 2018 14:04
    • Replies: 3
    • Views: 234
    3rd June 2018, 22:22 Go to last post
    • Replies: 7
    • Views: 399
    2nd June 2018, 16:10 Go to last post
  18. Output combinational output and valid sequential

    Started by sky_above, 26th May 2018 16:22
    • Replies: 9
    • Views: 404
    2nd June 2018, 15:28 Go to last post