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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 35,599
    25th March 2007, 08:41 Go to last post
  1. Interface Logic Model in Synosys is obsolete

    Started by ldhung, 22nd January 2020 13:35
    • Replies: 2
    • Views: 365
    26th January 2020, 10:56 Go to last post
  2. [ Describing PG Pins at RTL Level UPF ]

    Started by whizkid123, 23rd January 2020 07:49
    • Replies: 1
    • Views: 188
    23rd January 2020, 08:31 Go to last post
  3. DFT Reset Constraints Handling in Spyglass DFT SGDC

    Started by whizkid123, 14th January 2020 08:58
    • Replies: 2
    • Views: 527
    17th January 2020, 06:47 Go to last post
  4. Verdi: Assertion debug mode question

    Started by swabhi812, 15th January 2020 00:02
    • Replies: 0
    • Views: 252
    15th January 2020, 00:02 Go to last post
  5. Why not simulate ATPG pattern in ATPG TetraMAX tool

    Started by abgohil013, 17th December 2019 11:05
    • Replies: 4
    • Views: 663
    14th January 2020, 09:53 Go to last post
  6. Why we insert Mbist before scan ?

    Started by alp507, 3rd January 2020 05:52
    • Replies: 4
    • Views: 471
    14th January 2020, 09:02 Go to last post
  7. Innovus CTS .tcl Script Qustions

    Started by EEPuppyPuppy, 16th December 2019 22:12
    • Replies: 5
    • Views: 866
    14th January 2020, 08:20 Go to last post
  8. Innovus Command Questions

    Started by EEPuppyPuppy, 13th January 2020 23:22
    • Replies: 1
    • Views: 216
    14th January 2020, 08:19 Go to last post
  9. Synopsys TetraMax ATPG B16-1 and B12-1 Error

    Started by ibtesam90, 13th January 2020 16:57
    • Replies: 0
    • Views: 167
    13th January 2020, 16:57 Go to last post
  10. Understanding LVS results (hierarchical)

    Started by aditya1579, 12th January 2020 08:31
    • Replies: 2
    • Views: 346
    13th January 2020, 04:27 Go to last post
  11. Smaller die size by tighter SPICE corners?

    Started by Macduff, 8th January 2020 11:05
    • Replies: 4
    • Views: 400
    10th January 2020, 19:24 Go to last post
  12. [SOLVED] Short violations in Innovus (due to special route)

    Started by Fati_hv, 9th January 2020 11:19
    • Replies: 4
    • Views: 441
    10th January 2020, 17:30 Go to last post
  13. Does Opentimer tool for STA support VHDL netlist

    Started by garvind25, 6th January 2020 19:37
    • Replies: 2
    • Views: 405
    8th January 2020, 08:19 Go to last post
  14. DIE Size calculations in TSMC22ULL GF""FDX

    Started by Elec Singh, 8th January 2020 01:13
    • Replies: 1
    • Views: 228
    8th January 2020, 08:17 Go to last post
  15. Regarding synthesis of HDLs

    Started by garvind25, 26th December 2019 10:33
    • Replies: 4
    • Views: 548
    5th January 2020, 17:21 Go to last post
    • Replies: 3
    • Views: 581
    3rd January 2020, 18:20 Go to last post
  16. CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 1
    • Views: 307
    3rd January 2020, 08:59 Go to last post
  17. [SOLVED] Derate Factor while calculating delay

    Started by akhil_psm, 1st January 2020 06:14
    • Replies: 1
    • Views: 288
    3rd January 2020, 08:56 Go to last post
    • Replies: 0
    • Views: 290
    1st January 2020, 12:30 Go to last post
    • Replies: 0
    • Views: 257
    1st January 2020, 07:20 Go to last post
  18. How test data reduce in compression ?

    Started by alp507, 30th December 2019 13:31
    • Replies: 2
    • Views: 288
    31st December 2019, 05:41 Go to last post
  19. Verilog modulus % operator

    Started by TonyLS, 27th December 2019 05:10
    • Replies: 5
    • Views: 553
    27th December 2019, 19:10 Go to last post
  20. Phase Detect Circuitry

    Started by promach, 18th December 2019 03:16
    • Replies: 3
    • Views: 734
    24th December 2019, 08:02 Go to last post
  21. .sdc file into Innovus WARN and ERROR

    Started by EEPuppyPuppy, 17th December 2019 23:01
    • Replies: 3
    • Views: 514
    19th December 2019, 11:46 Go to last post
  22. How hold violation caused by below mentioned Scenceio

    Started by Varun124, 6th December 2019 14:06
    • Replies: 2
    • Views: 505
    17th December 2019, 18:51 Go to last post
  23. Can not run simv after compile Verilog project by VCS

    Started by nmphus, 7th December 2019 11:44
    • Replies: 1
    • Views: 578
    16th December 2019, 09:46 Go to last post
  24. Tracing clock net in Tetramax

    Started by dft1978, 16th December 2019 09:16
    • Replies: 0
    • Views: 296
    16th December 2019, 09:16 Go to last post