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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,702
    25th March 2007, 08:41 Go to last post
  1. Pico second precision up counter

    Started by npsnpsnps, 14th November 2018 12:21
    • Replies: 7
    • Views: 376
    Today, 19:32 Go to last post
  2. I have a Micro Code design assignment, how to proceed?

    Started by kaushikrvs, 17th November 2018 20:51
    • Replies: 1
    • Views: 255
    Yesterday, 15:51 Go to last post
    • Replies: 1
    • Views: 177
    15th November 2018, 03:17 Go to last post
    • Replies: 1
    • Views: 191
    14th November 2018, 09:05 Go to last post
  3. Ringing between pads and digital inputs?

    Started by Alexxk, 13th November 2018 08:28
    • Replies: 4
    • Views: 197
    13th November 2018, 18:50 Go to last post
  4. What does this mean in standard cell library?

    Started by liletian, 13th November 2018 07:14
    • Replies: 1
    • Views: 120
    13th November 2018, 08:32 Go to last post
  5. Prime Time power estimation whith .spef file

    Started by jmaileh.b, 12th November 2018 08:00
    • Replies: 0
    • Views: 129
    12th November 2018, 08:00 Go to last post
  6. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 5
    • Views: 517
    10th November 2018, 17:51 Go to last post
  7. How do I synthesize an inout port using DC?

    Started by kos8108, 27th August 2018 14:55
    • Replies: 1
    • Views: 225
    9th November 2018, 21:41 Go to last post
    • Replies: 1
    • Views: 208
    9th November 2018, 15:22 Go to last post
  8. what is the usage of the port in the fpga?

    Started by liletian, 28th August 2018 19:12
    • Replies: 4
    • Views: 357
    9th November 2018, 10:26 Go to last post
    • Replies: 3
    • Views: 191
    8th November 2018, 08:35 Go to last post
  9. SiliconSmart set_config_opt for individual bus pins

    Started by jiminization, 8th November 2018 07:21
    • Replies: 0
    • Views: 80
    8th November 2018, 07:21 Go to last post
  10. What does this mean in RC?

    Started by liletian, 6th November 2018 01:17
    • Replies: 6
    • Views: 366
    7th November 2018, 23:46 Go to last post
  11. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 3
    • Views: 342
    6th November 2018, 22:32 Go to last post
  12. Bottom up synthesis using dc compiler

    Started by IngleA, 23rd October 2018 18:45
    • Replies: 1
    • Views: 160
    6th November 2018, 22:25 Go to last post
  13. SiliconSmart Multi-Bit definition

    Started by jiminization, 6th November 2018 12:00
    • Replies: 0
    • Views: 92
    6th November 2018, 12:00 Go to last post
    • Replies: 6
    • Views: 342
    5th November 2018, 21:30 Go to last post
  14. [SOLVED] Parasitic Extraction for New Standard Cells

    Started by ranaya, 5th November 2018 10:23
    • Replies: 0
    • Views: 132
    5th November 2018, 10:23 Go to last post
  15. SiliconSmart clock gating cells

    Started by jiminization, 5th November 2018 04:51
    • Replies: 0
    • Views: 93
    5th November 2018, 04:51 Go to last post
  16. What are the port in the digital design?

    Started by liletian, 3rd November 2018 03:09
    • Replies: 2
    • Views: 293
    4th November 2018, 01:57 Go to last post
  17. Bencmakrak Circuits - Verilog Netlis

    Started by frasheed, 3rd November 2018 15:23
    • Replies: 3
    • Views: 195
    3rd November 2018, 19:19 Go to last post
  18. Which is more susceptible to variation, HVT or LVT?

    Started by kyon_lee, 2nd November 2018 00:52
    • Replies: 2
    • Views: 194
    2nd November 2018, 17:34 Go to last post
  19. port CLASS BUMP in output LEF

    Started by alphus, 29th October 2018 11:18
    • Replies: 5
    • Views: 277
    2nd November 2018, 14:22 Go to last post
    • Replies: 15
    • Views: 566
    2nd November 2018, 10:43 Go to last post
    • Replies: 3
    • Views: 213
    2nd November 2018, 00:34 Go to last post
  20. Static & Dynamic IR analysis operating conditions

    Started by sdbot, 23rd September 2018 23:55
    • Replies: 4
    • Views: 434
    1st November 2018, 16:47 Go to last post
  21. SiliconSmart Import Errors

    Started by jiminization, 30th October 2018 10:17
    • Replies: 1
    • Views: 153
    31st October 2018, 15:38 Go to last post
  22. Layers for blocking metal auto fill in TSMC

    Started by Potatoze, 30th October 2018 23:15
    • Replies: 2
    • Views: 186
    31st October 2018, 15:31 Go to last post
  23. Format of CDL netlist

    Started by joharali, 31st October 2018 15:09
    • Replies: 0
    • Views: 125
    31st October 2018, 15:09 Go to last post