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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,022
    klug
    25th March 2007, 08:41 Go to last post

  1. What cells are placed around RAM? Why?

    Started by Dan_Yang, 8th October 2019 15:04
    • Replies: 2
    • Views: 345
    visky2096
    Today, 10:44 Go to last post

  2. Can IP(Intellectual Property) open source, what does good business model?

    Started by luoyanghero, 13th October 2019 04:07
    • Replies: 4
    • Views: 504
    ads-ee
    14th October 2019, 15:48 Go to last post

  3. How to create parallel TDL patters in tetramax

    Started by Varun124, 13th October 2019 21:26
    • Replies: 0
    • Views: 139
    Varun124
    13th October 2019, 21:26 Go to last post

  4. What is meant by Split CODEC IN DFT ?

    Started by Varun124, 12th October 2019 10:18
    • Replies: 0
    • Views: 146
    Varun124
    12th October 2019, 10:18 Go to last post

  5. What does RLS Flow stands for in Physical Design?

    Started by naveenakkapally, 11th October 2019 04:50
    • Replies: 1
    • Views: 370
    oratie
    11th October 2019, 09:19 Go to last post

  6. Finding certain string in file using bash shell scriot

    Started by Abdo_Mgdy, 9th October 2019 17:36
    • Replies: 4
    • Views: 431
    Abdo_Mgdy
    10th October 2019, 10:45 Go to last post

  7. Suggest Junior project at university (digital electronics)

    Started by gokush, 9th October 2019 01:25
    • Replies: 1
    • Views: 165
    schmitt trigger
    9th October 2019, 01:46 Go to last post

  8. Formal verification of AHB bus, arbiter confusion

    Started by Haraldovs, 8th October 2019 07:57
    • Replies: 0
    • Views: 141
    Haraldovs
    8th October 2019, 07:57 Go to last post

  9. default statement in case

    Started by stanford, 5th October 2019 23:15
    2 Attachment(s)
    • Replies: 6
    • Views: 511
    FvM
    7th October 2019, 23:54 Go to last post

  10. Generating chain patterns in tetramax tool

    Started by Varun124, 7th October 2019 16:19
    • Replies: 0
    • Views: 132
    Varun124
    7th October 2019, 16:19 Go to last post

  11. Site row overlapping

    Started by kartikpujari, 2nd October 2019 17:00
    • Replies: 5
    • Views: 574
    ThisIsNotSam
    5th October 2019, 09:02 Go to last post

  12. How to identify design in terms of track ?

    Started by kartikpujari, 4th October 2019 09:49
    • Replies: 1
    • Views: 193
    ThisIsNotSam
    4th October 2019, 11:43 Go to last post

  13. [SOLVED] Post place & route netlist simulation is failing although STA is ok

    Started by mifio, 25th September 2019 14:04
    1 Attachment(s)
    • Replies: 8
    • Views: 580
    ThisIsNotSam
    2nd October 2019, 06:52 Go to last post

  14. For DFT perspective ,what happens when there are no capture clock

    Started by Varun124, 28th September 2019 08:31
    • Replies: 3
    • Views: 286
    Varun124
    30th September 2019, 20:06 Go to last post

  15. Multiple scan clocks

    Started by Varun124, 28th September 2019 09:06
    • Replies: 1
    • Views: 206
    Tieny
    30th September 2019, 13:57 Go to last post

  16. scan chain inside memory

    Started by fragnen, 13th September 2019 09:19
    • Replies: 12
    • Views: 716
    Tieny
    30th September 2019, 13:52 Go to last post

  17. FAN OUT /FAN IN for Logic Families

    Started by Robotduck, 25th September 2019 20:54
    • Replies: 2
    • Views: 205
    FvM
    25th September 2019, 23:08 Go to last post

  18. output and input impedance impedance

    Started by zuirgham, 24th September 2019 13:13
    4 Attachment(s)
    • Replies: 1
    • Views: 226
    BradtheRad
    25th September 2019, 04:13 Go to last post

  19. EBD file simulation in cadence virtuoso ADE simulation with Spectre

    Started by kenambo, 23rd September 2019 13:36
    • Replies: 0
    • Views: 188
    kenambo
    23rd September 2019, 13:36 Go to last post

  20. Extracting MOSRA LEVEL 3 Parameters and values

    Started by tanish, 20th September 2019 21:37
    • Replies: 0
    • Views: 252
    tanish
    20th September 2019, 21:37 Go to last post

  21. Gate Level Simulation

    Started by fragnen, 16th September 2019 10:13
    • Replies: 11
    • Views: 802
    ThisIsNotSam
    19th September 2019, 15:02 Go to last post

  22. Error to run simv when using VCS to simulate both Verilog and Vhdl

    Started by wbr, 19th September 2019 02:02
    1 Attachment(s)
    • Replies: 0
    • Views: 219
    wbr
    19th September 2019, 02:02 Go to last post

  23. P10 DMD-2PANEL-CCS C-18F2520__why ended up each panel individually while scrolling

    Started by saramah, 18th September 2019 14:06
    1 Attachment(s)
    • Replies: 0
    • Views: 174
    saramah
    18th September 2019, 14:15 Go to last post

  24. Lockup Latch for DFT purpose

    Started by Varun124, 3rd July 2019 19:34
    • Replies: 8
    • Views: 676
    vijay82
    18th September 2019, 11:46 Go to last post

  25. Problem adding reset to master slave D-FF for phase detector

    Started by yefj, 13th September 2019 12:46
    12 Attachment(s)
    • Replies: 5
    • Views: 485
    FvM
    17th September 2019, 18:33 Go to last post

  26. vcd file generation for netlist

    Started by maru2488, 4th September 2019 07:19
    • Replies: 2
    • Views: 304
    vipul982
    17th September 2019, 12:45 Go to last post

  27. The collection of VLSI/ASIC logic design interview questions

    Started by vlsifaq, 23rd August 2019 14:51
    • Replies: 1
    • Views: 416
    vlsifaq
    17th September 2019, 11:27 Go to last post

  28. I2C not working properly

    Started by rmachado, 2nd September 2019 14:39
    2 Pages •
    1 2
    7 Attachment(s)
    • Replies: 20
    • Views: 1,326
    vGoodtimes
    14th September 2019, 20:36 Go to last post

  29. Overwrite cell delay.

    Started by Yussef, 11th September 2019 13:46
    • Replies: 4
    • Views: 411
    Yussef
    12th September 2019, 14:04 Go to last post

  30. How to fix errors in lint summary (check_timing_intent) during synthesis in Genus?

    Started by asic_architect, 8th September 2019 04:25
    • Replies: 3
    • Views: 472
    ThisIsNotSam
    9th September 2019, 08:37 Go to last post
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