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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,477
    25th March 2007, 08:41 Go to last post
  1. Logarithmic number system

    Started by krishvamsi, Yesterday 11:51
    • Replies: 1
    • Views: 70
    Today, 00:04 Go to last post
  2. Tile size, gates and infrastructure

    Started by peen1, 19th August 2018 03:26
    • Replies: 3
    • Views: 150
    20th August 2018, 02:12 Go to last post
  3. What does followpin option do edit wire in Innovus

    Started by saket91, 19th August 2018 03:33
    • Replies: 0
    • Views: 109
    19th August 2018, 03:33 Go to last post
  4. how to solve a setup hold conflicting path

    Started by preethi19, 15th August 2018 05:38
    • Replies: 4
    • Views: 304
    19th August 2018, 03:28 Go to last post
  5. How to re-run irun simulation?

    Started by liletian, 18th August 2018 05:47
    • Replies: 4
    • Views: 207
    18th August 2018, 20:22 Go to last post
    • Replies: 0
    • Views: 114
    18th August 2018, 19:44 Go to last post
  6. How to Optimize power with Design Compiler

    Started by javierh.santiago, 17th August 2018 20:01
    • Replies: 2
    • Views: 142
    17th August 2018, 22:42 Go to last post
  7. Design Constraints in Design Compiler

    Started by javierh.santiago, 17th August 2018 19:33
    • Replies: 0
    • Views: 107
    17th August 2018, 19:33 Go to last post
    • Replies: 4
    • Views: 150
    17th August 2018, 17:52 Go to last post
    • Replies: 1
    • Views: 112
    17th August 2018, 16:01 Go to last post
    • Replies: 2
    • Views: 140
    17th August 2018, 03:13 Go to last post
  8. Serdes IP integration to ASIC

    Started by preethi19, 3rd August 2018 07:16
    • Replies: 4
    • Views: 313
    15th August 2018, 21:50 Go to last post
  9. Interview questions on serdes

    Started by preethi19, 15th August 2018 05:28
    • Replies: 0
    • Views: 102
    15th August 2018, 05:28 Go to last post
  10. Need some tutorial for golden netlist flow

    Started by smsskil, 10th August 2018 06:02
    • Replies: 4
    • Views: 324
    13th August 2018, 14:26 Go to last post
  11. Noise analysis in cmos inverter using ngspice

    Started by smita1811, 9th August 2018 09:19
    • Replies: 6
    • Views: 310
    13th August 2018, 02:49 Go to last post
    • Replies: 0
    • Views: 212
    12th August 2018, 23:28 Go to last post
  12. how to include a module in another module?

    Started by liletian, 9th August 2018 19:25
    • Replies: 13
    • Views: 457
    11th August 2018, 20:01 Go to last post
  13. how to print integer in the verilog module

    Started by liletian, 8th August 2018 18:30
    • Replies: 8
    • Views: 378
    11th August 2018, 02:55 Go to last post
  14. Test Coverage loss scan chains

    Started by priyutiru, 10th August 2018 01:38
    • Replies: 2
    • Views: 158
    11th August 2018, 00:34 Go to last post
    • Replies: 1
    • Views: 160
    10th August 2018, 14:29 Go to last post
  15. Pattern count increase

    Started by priyutiru, 10th August 2018 01:40
    • Replies: 0
    • Views: 119
    10th August 2018, 01:40 Go to last post
  16. Antenna violation and its effects

    Started by maniroop, 8th August 2018 13:53
    • Replies: 2
    • Views: 140
    8th August 2018, 18:33 Go to last post
  17. Effective width of pmos and nmos in series

    Started by smita1811, 4th August 2018 02:39
    • Replies: 4
    • Views: 540
    8th August 2018, 04:57 Go to last post
  18. Aske for help, about PNP in TSMC180nm technology

    Started by pecroger, 3rd August 2018 16:42
    • Replies: 1
    • Views: 246
    3rd August 2018, 17:58 Go to last post
  19. Observation points for Fault grading

    Started by rmk423, 24th July 2018 14:23
    • Replies: 3
    • Views: 261
    3rd August 2018, 13:54 Go to last post
  20. VHDL attribute enum_encoding in INCISIVE

    Started by digitalo, 2nd August 2018 12:21
    • Replies: 0
    • Views: 162
    2nd August 2018, 12:21 Go to last post
  21. timing analysis with generated clocks

    Started by stanford, 31st July 2018 18:11
    • Replies: 5
    • Views: 298
    1st August 2018, 05:57 Go to last post