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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,136
    25th March 2007, 08:41 Go to last post
  1. Clock domain crossing problem in DFT

    Started by Nanda_DFT, Today 07:06
    • Replies: 1
    • Views: 73
    Today, 15:39 Go to last post
  2. Post layout delay in cadence

    Started by umaizameh, 14th February 2019 06:53
    • Replies: 7
    • Views: 420
    Today, 06:34 Go to last post
  3. How to Dump e-vcd File in Verilog HDL ?

    Started by sreejeesh_sreedharan, 14th February 2019 08:28
    • Replies: 2
    • Views: 133
    14th February 2019, 16:39 Go to last post
  4. Sample files needed for working with Automatic PnR

    Started by LostEagle, 14th February 2019 00:17
    • Replies: 1
    • Views: 111
    14th February 2019, 02:05 Go to last post
    • Replies: 4
    • Views: 189
    13th February 2019, 09:34 Go to last post
  5. Using SPEF files for STA in INNOVUS

    Started by Windywast, 12th February 2019 01:37
    • Replies: 3
    • Views: 185
    12th February 2019, 17:49 Go to last post
    • Replies: 4
    • Views: 308
    11th February 2019, 19:41 Go to last post
    • Replies: 1
    • Views: 94
    11th February 2019, 17:19 Go to last post
  6. synthesized netlists simulation issue

    Started by manpmanp, 7th February 2019 17:42
    • Replies: 6
    • Views: 235
    11th February 2019, 16:19 Go to last post
  7. DFT issues on scan clock input as "x"

    Started by skyworld_cy, 9th February 2019 10:08
    • Replies: 5
    • Views: 296
    10th February 2019, 03:47 Go to last post
  8. How do you simulate a mixed-signal system?

    Started by blacki, 8th February 2019 17:22
    • Replies: 2
    • Views: 133
    9th February 2019, 05:40 Go to last post
    • Replies: 1
    • Views: 82
    8th February 2019, 18:46 Go to last post
  9. MCR - Metal Cap Reduction

    Started by Studentofknowledge, 8th February 2019 17:44
    • Replies: 1
    • Views: 82
    8th February 2019, 18:11 Go to last post
    • Replies: 0
    • Views: 122
    8th February 2019, 02:15 Go to last post
  10. Automatize simulations in Modelsim

    Started by javierh.santiago, 5th February 2019 22:44
    • Replies: 2
    • Views: 280
    8th February 2019, 00:12 Go to last post
  11. what are the inputs and outputs for floorplanning?

    Started by lh-, 3rd February 2019 18:28
    • Replies: 8
    • Views: 402
    7th February 2019, 19:42 Go to last post
  12. Digital filter projects

    Started by blacki, 6th February 2019 04:53
    • Replies: 7
    • Views: 302
    7th February 2019, 14:16 Go to last post
  13. finFET's behavior with Temperature

    Started by Wyre, 6th February 2019 10:28
    • Replies: 1
    • Views: 215
    7th February 2019, 02:58 Go to last post
    • Replies: 4
    • Views: 211
    6th February 2019, 04:38 Go to last post
  14. Report detailed area in Design Compiler/ Cadence Innovus

    Started by oAwad, 6th February 2019 02:24
    • Replies: 1
    • Views: 133
    6th February 2019, 04:36 Go to last post
  15. Optimize shifter synthesis in Design Compiler

    Started by oAwad, 2nd February 2019 22:19
    • Replies: 3
    • Views: 291
    3rd February 2019, 02:21 Go to last post
  16. High-Level Synthesis (HLS) vs RTL for ASIC flow

    Started by oAwad, 31st December 2018 22:51
    • Replies: 3
    • Views: 852
    21st January 2019, 18:08 Go to last post
  17. ADE9078 Energy Meter & Rogowski Coil Clarification

    Started by eebhoi01, 21st January 2019 08:19
    • Replies: 1
    • Views: 180
    21st January 2019, 09:08 Go to last post
  18. Using a CDL file in LTSpice

    Started by youngguns21, 16th January 2019 17:13
    • Replies: 3
    • Views: 356
    16th January 2019, 21:51 Go to last post
  19. Clock gate set up and hold checks

    Started by mailsrikanth007, 15th January 2019 07:18
    • Replies: 1
    • Views: 253
    15th January 2019, 15:56 Go to last post
  20. FIFO implementation using RAM

    Started by biju4u90, 8th January 2019 19:16
    • Replies: 3
    • Views: 705
    9th January 2019, 11:47 Go to last post
  21. TSMC 65nm GP operating voltage

    Started by oAwad, 6th January 2019 21:10
    • Replies: 1
    • Views: 287
    7th January 2019, 14:25 Go to last post