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Threads 1 to 30 of 24666

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 37,378
    klug
    25th March 2007, 08:41 Go to last post

  1. Input rise time of start/stop pulse to the TDC

    Started by vinogunasekaran, Today 03:43
    • Replies: 2
    • Views: 149
    FvM
    Today, 10:36 Go to last post

  2. Need help to understand spice statement

    Started by vasaroopak, Today 05:17
    • Replies: 1
    • Views: 103
    ThisIsNotSam
    Today, 07:20 Go to last post

  3. micron ddr sysverilog model | Read rand addr | how to get 0s ( not Xs ) ?

    Started by ranke, 1st June 2020 10:12
    • Replies: 2
    • Views: 236
    dpaul
    Yesterday, 08:24 Go to last post

  4. How to add PTM libraries in Tanner EDA

    Started by iamshahidrana, 4th April 2020 12:07
    • Replies: 3
    • Views: 821
    TechbitDiva
    29th May 2020, 17:35 Go to last post

  5. How to set_multicycle_path for latch in sta

    Started by CambridgeLv, 28th May 2020 04:33
    • Replies: 7
    • Views: 352
    ThisIsNotSam
    29th May 2020, 07:52 Go to last post

  6. Results for hierarchical LVS

    Started by aditya1579, 4th March 2020 12:54
    • Replies: 2
    • Views: 448
    CambridgeLv
    29th May 2020, 07:05 Go to last post

  7. Is there prime time command that find down size cell in auto?

    Started by tedkim, 29th May 2020 03:21
    • Replies: 1
    • Views: 167
    tedkim
    29th May 2020, 06:08 Go to last post

  8. DRC rules for Double Pattern Test

    Started by aditya1579, 25th May 2020 08:53
    • Replies: 2
    • Views: 266
    CambridgeLv
    29th May 2020, 02:26 Go to last post

  9. Can you read Cadence OA format routing techfile in Synopsys ICC2 tool?

    Started by tro2212, 28th May 2020 16:17
    • Replies: 0
    • Views: 121
    tro2212
    28th May 2020, 16:17 Go to last post

  10. DFT -lbist pattern simulation

    Started by avinashkumar, 26th May 2020 12:57
    • Replies: 0
    • Views: 222
    avinashkumar
    26th May 2020, 12:57 Go to last post

  11. DFT compiler commands

    Started by chis4yu, 26th May 2020 08:20
    • Replies: 0
    • Views: 162
    chis4yu
    26th May 2020, 08:20 Go to last post

  12. Memory repair with efuse and bira

    Started by mona_patel, 26th May 2020 06:09
    • Replies: 0
    • Views: 158
    mona_patel
    26th May 2020, 06:09 Go to last post

  13. Tetramax custom patterns

    Started by chis4yu, 25th May 2020 22:26
    • Replies: 0
    • Views: 158
    chis4yu
    25th May 2020, 22:26 Go to last post

  14. Floorplanning Guidelines for TSMC 7nm

    Started by aditya1579, 21st May 2020 12:47
    • Replies: 5
    • Views: 543
    ThisIsNotSam
    24th May 2020, 09:54 Go to last post

  15. DFT compiler with multimodes

    Started by chis4yu, 23rd May 2020 01:21
    • Replies: 0
    • Views: 206
    chis4yu
    23rd May 2020, 01:21 Go to last post

  16. Port placement in a design block

    Started by karthikshetty, 22nd May 2020 05:01
    • Replies: 0
    • Views: 328
    karthikshetty
    22nd May 2020, 05:01 Go to last post

  17. COmparator using xor gate

    Started by djc, 20th May 2020 07:41
    • Replies: 6
    • Views: 486
    djc
    21st May 2020, 10:13 Go to last post

  18. CADENCE is disabling functions alone

    Started by lufer17, 18th May 2020 14:28
    2 Attachment(s)
    • Replies: 6
    • Views: 480
    dick_freebird
    20th May 2020, 22:20 Go to last post

  19. CADENCE: layout error

    Started by lufer17, 18th May 2020 14:45
    3 Attachment(s)
    • Replies: 8
    • Views: 552
    lufer17
    20th May 2020, 15:05 Go to last post

  20. MBIST clocks synchronization

    Started by mona_patel, 19th May 2020 07:13
    • Replies: 2
    • Views: 327
    mona_patel
    20th May 2020, 10:32 Go to last post

  21. How to do post layout simulation during digital ASIC design?

    Started by daskk62, 12th May 2020 17:41
    • Replies: 7
    • Views: 749
    ranaya
    19th May 2020, 15:30 Go to last post

  22. [SOLVED] P&R Buffer Reduction in a Shift Register

    Started by ranaya, 17th May 2020 18:02
    2 Attachment(s)
    • Replies: 8
    • Views: 542
    ThisIsNotSam
    19th May 2020, 15:28 Go to last post

  23. Capacitance effect due to more vias and metal straps.

    Started by reddvoid, 17th May 2020 19:00
    • Replies: 2
    • Views: 392
    ranaya
    19th May 2020, 15:20 Go to last post

  24. Plotting delay vs. load capacitance in Hspice

    Started by reddvoid, 19th May 2020 08:34
    • Replies: 0
    • Views: 183
    reddvoid
    19th May 2020, 08:34 Go to last post

  25. VCS2016 cannot compile ok

    Started by luoyanghero, 18th May 2020 11:09
    • Replies: 0
    • Views: 293
    luoyanghero
    18th May 2020, 11:09 Go to last post

  26. Characterisation of standard cell libraries using cadence tool

    Started by BB11, 13th May 2020 09:09
    • Replies: 1
    • Views: 308
    reddvoid
    17th May 2020, 19:05 Go to last post

  27. Creating Verilog wrapper around a system Verilog DDR4 memory model from micron

    Started by Dude99, 15th May 2020 01:07
    • Replies: 2
    • Views: 371
    dave_59
    16th May 2020, 01:33 Go to last post

  28. ModelSim/QuestaSim SE/PE versions -> what's mean?

    Started by ivlsi, 15th May 2020 13:17
    • Replies: 1
    • Views: 251
    srizbf
    15th May 2020, 15:34 Go to last post

  29. Sequential depth in DFT

    Started by msancheti, 15th May 2020 12:49
    • Replies: 0
    • Views: 157
    msancheti
    15th May 2020, 12:49 Go to last post

  30. TCL script to automate macro placement in icc shell

    Started by Hamsha22, 15th May 2020 02:06
    • Replies: 0
    • Views: 204
    Hamsha22
    15th May 2020, 02:06 Go to last post
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