1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    121,763
Page 1 of 815 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24421

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,533
    25th March 2007, 08:41 Go to last post
  1. LEC between two netlists

    Started by fragnen, Today 13:22
    • Replies: 0
    • Views: 12
    Today, 13:22 Go to last post
    • Replies: 1
    • Views: 92
    Today, 02:16 Go to last post
  2. Convert ITF file to ict for captable generation

    Started by Chinmaye, 14th August 2019 17:30
    • Replies: 4
    • Views: 381
    16th August 2019, 10:10 Go to last post
  3. Protocol Design - System Verilog

    Started by fazimohd, 12th August 2019 12:53
    • Replies: 5
    • Views: 360
    14th August 2019, 09:24 Go to last post
    • Replies: 0
    • Views: 126
    12th August 2019, 10:52 Go to last post
    • Replies: 6
    • Views: 348
    11th August 2019, 17:53 Go to last post
  4. Max tran, max cap ,max fanout

    Started by Akshaykumarbm, 8th August 2019 07:49
    • Replies: 2
    • Views: 214
    9th August 2019, 19:41 Go to last post
  5. What is a Via Ladder ?

    Started by akshay0993, 9th August 2019 19:40
    • Replies: 0
    • Views: 97
    9th August 2019, 19:40 Go to last post
    • Replies: 2
    • Views: 245
    7th August 2019, 18:40 Go to last post
  6. How to get all Objects in the Design in ICC2

    Started by Seshas241, 3rd August 2019 16:13
    • Replies: 0
    • Views: 223
    3rd August 2019, 16:13 Go to last post
  7. generic ancillary data extractor and inserter

    Started by yashjain, 28th July 2019 08:01
    • Replies: 2
    • Views: 314
    28th July 2019, 14:20 Go to last post
    • Replies: 5
    • Views: 542
    25th July 2019, 19:52 Go to last post
  8. [SOLVED] $urandom_range is generating same values

    Started by swabhi812, 23rd July 2019 22:26
    • Replies: 2
    • Views: 345
    24th July 2019, 06:25 Go to last post
    • Replies: 2
    • Views: 208
    23rd July 2019, 16:33 Go to last post
    • Replies: 2
    • Views: 277
    23rd July 2019, 15:17 Go to last post
  9. FERROCORE FR3 more information?

    Started by Coper, 22nd July 2019 10:42
    • Replies: 2
    • Views: 427
    22nd July 2019, 14:47 Go to last post
  10. CRC Error insertion and detection

    Started by rrucha, 17th July 2019 21:01
    • Replies: 4
    • Views: 474
    19th July 2019, 19:19 Go to last post
  11. dft-how to use .bench format

    Started by avinashkumar, 18th July 2019 09:18
    • Replies: 1
    • Views: 287
    19th July 2019, 12:16 Go to last post
    • Replies: 0
    • Views: 200
    17th July 2019, 19:12 Go to last post
  12. Tech library problem

    Started by abdoboua, 16th July 2019 12:15
    • Replies: 3
    • Views: 326
    16th July 2019, 18:49 Go to last post
    • Replies: 4
    • Views: 364
    16th July 2019, 17:30 Go to last post
  13. Help needed for Spice conversion from MDL Syntax

    Started by smurtuzah, 16th July 2019 13:29
    • Replies: 0
    • Views: 191
    16th July 2019, 13:29 Go to last post
  14. DRC problem with layout in cadence 617

    Started by abdoboua, 8th July 2019 19:05
    • Replies: 1
    • Views: 263
    16th July 2019, 11:35 Go to last post