1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    109,017
Page 1 of 803 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24063

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,414
    klug
    25th March 2007, 08:41 Go to last post

  1. Unpacked array in SV is treated as packed array during instantiation

    Started by swabhi812, Yesterday 16:40
    • Replies: 0
    • Views: 72
    swabhi812
    Yesterday, 17:01 Go to last post

  2. RTL auto code generation

    Started by ctzof, 21st July 2018 13:20
    • Replies: 3
    • Views: 201
    swabhi812
    Yesterday, 16:49 Go to last post

  3. mod % vs divider (are they synthesizable?)

    Started by stanford, 20th July 2018 23:10
    • Replies: 3
    • Views: 149
    dpaul
    21st July 2018, 21:18 Go to last post

  4. A Revolutionary Massively Parallel Processing Architecture

    Started by paulpawlenko, 14th July 2018 01:16
    2 Pages •
    1 2
    • Replies: 38
    • Views: 1,315
    ThisIsNotSam
    21st July 2018, 17:00 Go to last post

  5. Create Block in innovus to use on other designs

    Started by rmachado, 4th July 2018 17:43
    9 Attachment(s)
    • Replies: 16
    • Views: 322
    ThisIsNotSam
    20th July 2018, 18:45 Go to last post

  6. DFT command operation doubt

    Started by Baskar, 14th February 2018 13:29
    • Replies: 2
    • Views: 604
    Adarsh24
    20th July 2018, 16:53 Go to last post

  7. DFT: Simulation of ATPG has mismatches for SDF MTM Spec maximum only.

    Started by Adarsh24, 13th July 2018 08:43
    • Replies: 2
    • Views: 94
    Adarsh24
    20th July 2018, 16:48 Go to last post

  8. Moved: Re: A Revolutionary Massively Parallel Processing Architecture

    Started by paulpawlenko, 20th July 2018 16:48
    •  
    •  

  9. difference between priority case and case

    Started by stanford, 19th July 2018 23:15
    • Replies: 1
    • Views: 90
    swabhi812
    20th July 2018, 01:12 Go to last post

  10. Post layout Simulation without Physical verification

    Started by Mahmoud_Dagher, 17th July 2018 14:38
    • Replies: 4
    • Views: 193
    dick_freebird
    18th July 2018, 19:05 Go to last post

  11. Explain tech file name rule

    Started by faunusest, 18th July 2018 04:02
    • Replies: 1
    • Views: 102
    ThisIsNotSam
    18th July 2018, 14:12 Go to last post

  12. What is this IC? Nand flash or memory? What is part number?

    Started by alibarghi, 18th July 2018 06:46
    2 Attachment(s)
    • Replies: 1
    • Views: 133
    rho-bot
    18th July 2018, 08:13 Go to last post

  13. latency of the dsync output

    Started by stanford, 11th July 2018 19:58
    • Replies: 9
    • Views: 336
    swabhi812
    17th July 2018, 19:30 Go to last post

  14. X propagation on input when else is not there

    Started by stanford, 12th July 2018 23:00
    • Replies: 8
    • Views: 335
    swabhi812
    17th July 2018, 19:24 Go to last post

  15. lw, sw in a processor

    Started by stanford, 16th July 2018 06:14
    • Replies: 3
    • Views: 203
    swabhi812
    17th July 2018, 19:17 Go to last post

  16. TCL Script for adding wires on SoC Encounter

    Started by Mahmoud_Dagher, 17th July 2018 14:49
    • Replies: 0
    • Views: 81
    Mahmoud_Dagher
    17th July 2018, 14:49 Go to last post

  17. Comparing two numbers

    Started by Pravesh_Rathee, 11th July 2018 17:54
    • Replies: 12
    • Views: 358
    ads-ee
    13th July 2018, 20:29 Go to last post

  18. [SOLVED] Regarding placement legalization in cadence

    Started by pavan muvvala, 12th July 2018 07:45
    • Replies: 3
    • Views: 149
    ThisIsNotSam
    13th July 2018, 19:47 Go to last post

  19. Parallel Pattern Simulation

    Started by sandy2811, 3rd July 2018 18:28
    • Replies: 4
    • Views: 234
    Adarsh24
    13th July 2018, 11:39 Go to last post

  20. How can we make D flip-flop with clear using 2:1 mux only.

    Started by aincrad, 12th July 2018 06:47
    1 Attachment(s)
    • Replies: 2
    • Views: 141
    aincrad
    12th July 2018, 09:27 Go to last post

  21. Encrypt verilog with ablity to synthesize in cadence tool

    Started by smsskil, 11th July 2018 08:48
    • Replies: 3
    • Views: 132
    pancho_hideboo
    11th July 2018, 12:00 Go to last post

  22. [Moved]: Verilog code to read .txt (hexa value)file and and to store in PC

    Started by vachanukb, 6th July 2018 19:41
    • Replies: 3
    • Views: 296
    dave_59
    9th July 2018, 20:14 Go to last post

  23. [SOLVED] 5 connectivity problems in my ASIC implementation: [The net has an antenna]

    Started by Mahmoud_Dagher, 9th July 2018 15:31
    5 Attachment(s)
    • Replies: 1
    • Views: 165
    ThisIsNotSam
    9th July 2018, 17:27 Go to last post

  24. fifo memory initialization

    Started by stanford, 6th July 2018 23:28
    • Replies: 3
    • Views: 325
    ThisIsNotSam
    7th July 2018, 20:59 Go to last post

  25. which default is taken in a case block inside an always_comb

    Started by stanford, 5th July 2018 22:16
    • Replies: 2
    • Views: 182
    asdf44
    6th July 2018, 01:34 Go to last post

  26. Manual Intentional Routing

    Started by Mahmoud_Dagher, 3rd July 2018 20:01
    • Replies: 5
    • Views: 257
    ThisIsNotSam
    5th July 2018, 14:12 Go to last post

  27. How do I do an ASIC post-synthesis timing simulation in Modelsim for Verilog

    Started by AlexKeys, 4th July 2018 04:25
    • Replies: 2
    • Views: 210
    rmachado
    4th July 2018, 17:57 Go to last post

  28. [SOLVED] Request for Cadance Encounter commands of different violations

    Started by pavan muvvala, 4th July 2018 09:14
    • Replies: 1
    • Views: 118
    ThisIsNotSam
    4th July 2018, 16:51 Go to last post

  29. Synopsys: DC synthesis of design with different clocks

    Started by Vivek2Keviv, 2nd July 2018 22:21
    1 Attachment(s)
    • Replies: 4
    • Views: 256
    ThisIsNotSam
    3rd July 2018, 17:05 Go to last post

  30. Recovery and removal time of async reset

    Started by stanford, 29th June 2018 09:32
    • Replies: 3
    • Views: 250
    FvM
    2nd July 2018, 22:26 Go to last post
Powered by vBulletin™
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.