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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 36,695
    klug
    25th March 2007, 08:41 Go to last post

  1. Conflict between two axi masters.

    Started by hcu, Today 06:04
    • Replies: 2
    • Views: 117
    hcu
    Today, 14:08 Go to last post

  2. How to parallel process foreach_in_collection in ICC?

    Started by pradeep5344, Yesterday 08:57
    • Replies: 2
    • Views: 149
    pradeep5344
    Today, 04:08 Go to last post

  3. How to write patterns to multiple files - Cadence ATPG

    Started by srirao, Today 01:54
    • Replies: 0
    • Views: 135
    srirao
    Today, 01:54 Go to last post

  4. How to write a top-level DEF file/hierarchical DEF files

    Started by rhilai, Yesterday 11:23
    • Replies: 1
    • Views: 132
    ThisIsNotSam
    Yesterday, 15:44 Go to last post

  5. UPF for low power design in DC/ICC2

    Started by riti, 24th March 2020 17:55
    • Replies: 3
    • Views: 546
    riti
    27th March 2020, 12:51 Go to last post

  6. How to estimate power consumption at the IP design level?

    Started by luoyanghero, 27th March 2020 03:38
    • Replies: 0
    • Views: 200
    luoyanghero
    27th March 2020, 03:38 Go to last post

  7. How to evaluate the energy of an arithmetic operation

    Started by noureddine-as, 20th March 2020 14:46
    • Replies: 3
    • Views: 343
    noureddine-as
    26th March 2020, 16:04 Go to last post

  8. Latency and skew of clock tree

    Started by riti, 19th March 2020 17:34
    • Replies: 5
    • Views: 469
    ThisIsNotSam
    21st March 2020, 10:12 Go to last post

  9. [SOLVED] Low power optimization problem in competitive vendor economics ?

    Started by BeckettColt, 19th March 2020 10:31
    • Replies: 2
    • Views: 292
    BeckettColt
    21st March 2020, 06:16 Go to last post

  10. [SOLVED] How to automate the maximum frequency estimation

    Started by noureddine-as, 20th March 2020 03:07
    • Replies: 4
    • Views: 329
    noureddine-as
    20th March 2020, 14:29 Go to last post

  11. Max Overdrive Supply Voltage in SoC 5nmFinFet

    Started by Mister_hass, 19th March 2020 20:53
    • Replies: 3
    • Views: 254
    ThisIsNotSam
    20th March 2020, 08:30 Go to last post

  12. LTspice and Electric – (VLSI) - Simulation error

    Started by lufer17, 14th March 2020 13:54
    2 Attachment(s)
    • Replies: 2
    • Views: 272
    lufer17
    18th March 2020, 12:39 Go to last post

  13. Troubles with TetraMAX test patterns

    Started by TelpDmtr, 11th March 2020 10:59
    7 Attachment(s)
    • Replies: 7
    • Views: 626
    kungchuking
    17th March 2020, 04:47 Go to last post

  14. [SOLVED] How to check un-clocked flops and how to trace the source point for the problem ?

    Started by purushotham.vlsi, 12th March 2020 10:51
    • Replies: 12
    • Views: 773
    FvM
    15th March 2020, 12:33 Go to last post

  15. PrimeTime provides different Power analysis results for FSDB vs. VCD files

    Started by noureddine-as, 13th March 2020 17:10
    • Replies: 0
    • Views: 225
    noureddine-as
    13th March 2020, 17:10 Go to last post

  16. two test case clock gating check circuit & clock divide generation circiut

    Started by kumarprakash1980, 13th March 2020 14:21
    • Replies: 1
    • Views: 162
    dpaul
    13th March 2020, 14:47 Go to last post

  17. Regarding synthesis of HDLs

    Started by garvind25, 26th December 2019 10:33
    • Replies: 5
    • Views: 898
    uditkumar1983
    12th March 2020, 10:40 Go to last post

  18. [SOLVED] CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 3
    • Views: 735
    uditkumar1983
    12th March 2020, 10:33 Go to last post

  19. Best Books for Learning Synopsys ASIC Tools and Cadence ASIC Tools

    Started by Puppet123, 12th March 2020 07:07
    • Replies: 1
    • Views: 250
    dpaul
    12th March 2020, 10:11 Go to last post

  20. Finding an IP Power Analysis Tool

    Started by luoyanghero, 3rd March 2020 03:02
    • Replies: 3
    • Views: 335
    uditkumar1983
    12th March 2020, 10:05 Go to last post

  21. Electric VLSI Design System - SEQUENTIAL COMMAND

    Started by lufer17, 12th March 2020 02:01
    • Replies: 0
    • Views: 297
    lufer17
    12th March 2020, 02:01 Go to last post

  22. Verdi GUI addsignal command line option

    Started by sandeepj, 7th March 2020 16:51
    3 Attachment(s)
    • Replies: 1
    • Views: 265
    kungchuking
    10th March 2020, 14:01 Go to last post

  23. RTL design (system/Verilog) for Linked list with buffer/SRAM storage

    Started by sandeepj, 7th March 2020 17:01
    • Replies: 0
    • Views: 478
    sandeepj
    7th March 2020, 17:01 Go to last post

  24. Results for hierarchical LVS

    Started by aditya1579, 4th March 2020 12:54
    • Replies: 1
    • Views: 297
    Prashanthanilm
    7th March 2020, 11:16 Go to last post

  25. Is .CDL netlist format proprietary to Cadence? Where can I find its syntax manual?

    Started by majd229, 6th March 2020 20:20
    • Replies: 0
    • Views: 244
    majd229
    6th March 2020, 20:20 Go to last post

  26. How to display ASCII state when simulating one-hot encoding FSM ?

    Started by lx1019, 5th March 2020 15:38
    • Replies: 2
    • Views: 336
    ThisIsNotSam
    6th March 2020, 09:17 Go to last post

  27. Capacitacne tables in UMC 130nm

    Started by shlooky, 3rd March 2020 18:18
    • Replies: 3
    • Views: 359
    ThisIsNotSam
    4th March 2020, 09:07 Go to last post

  28. Unbuffered cells and how does it affect timing constraints

    Started by janthonym, 27th February 2020 17:38
    • Replies: 4
    • Views: 540
    ThisIsNotSam
    29th February 2020, 15:53 Go to last post

  29. PrimeTime : How to manually assign the content of the nets

    Started by kevin5059, 28th February 2020 09:56
    1 Attachment(s)
    • Replies: 1
    • Views: 323
    ThisIsNotSam
    28th February 2020, 11:07 Go to last post

  30. Boundary Cell in Core Chip

    Started by akhil_psm, 9th December 2019 17:50
    • Replies: 3
    • Views: 1,047
    ThisIsNotSam
    25th February 2020, 08:31 Go to last post
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