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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,251
    25th March 2007, 08:41 Go to last post
    • Replies: 7
    • Views: 313
    18th May 2018, 19:38 Go to last post
  1. Selecting CTS topology in ICC

    Started by Vamsi Srikanth S, 17th May 2018 12:57
    • Replies: 2
    • Views: 119
    17th May 2018, 19:04 Go to last post
    • Replies: 8
    • Views: 229
    17th May 2018, 16:12 Go to last post
  2. Questions on DFT autofix

    Started by childs72, 17th May 2018 02:54
    • Replies: 1
    • Views: 86
    17th May 2018, 07:06 Go to last post
  3. DC-topo and ICC environment comparison

    Started by ua6bqg, 7th May 2018 17:19
    • Replies: 4
    • Views: 176
    17th May 2018, 05:40 Go to last post
  4. PTPX Switching power calculation

    Started by Mohammed Abrar, 16th May 2018 01:06
    • Replies: 1
    • Views: 96
    17th May 2018, 05:34 Go to last post
  5. RTL for linear search

    Started by sky_above, 14th May 2018 13:59
    • Replies: 19
    • Views: 462
    16th May 2018, 15:11 Go to last post
  6. 4 bit multiplier from 2 bit multiplier

    Started by sky_above, 14th May 2018 13:56
    • Replies: 3
    • Views: 92
    14th May 2018, 15:24 Go to last post
    • Replies: 1
    • Views: 213
    11th May 2018, 13:40 Go to last post
    • Replies: 3
    • Views: 252
    10th May 2018, 14:34 Go to last post
  7. Merging pin-tagged nets in Cadence

    Started by sci-fi_guy, 4th May 2018 11:42
    • Replies: 1
    • Views: 116
    9th May 2018, 13:05 Go to last post
    • Replies: 1
    • Views: 152
    8th May 2018, 15:55 Go to last post
    • Replies: 6
    • Views: 237
    7th May 2018, 20:24 Go to last post
  8. Prime time tool of Synopsys

    Started by harshahari, 12th April 2018 09:38
    • Replies: 4
    • Views: 532
    4th May 2018, 03:08 Go to last post
    • Replies: 1
    • Views: 124
    3rd May 2018, 16:01 Go to last post
    • Replies: 1
    • Views: 591
    3rd May 2018, 11:32 Go to last post
    • Replies: 1
    • Views: 178
    3rd May 2018, 11:25 Go to last post
  9. Force in Synopsys DVE

    Started by rmk423, 25th April 2018 06:50
    • Replies: 1
    • Views: 251
    3rd May 2018, 10:15 Go to last post
  10. parallel chain and scan simulation

    Started by palanis29, 3rd January 2018 10:48
    • Replies: 9
    • Views: 1,710
    3rd May 2018, 10:08 Go to last post
  11. UVM predictor error: Pending reg items

    Started by jiminization, 3rd May 2018 03:10
    • Replies: 0
    • Views: 111
    3rd May 2018, 03:10 Go to last post
  12. Async reset to clk gate

    Started by stanford, 30th April 2018 22:27
    • Replies: 1
    • Views: 244
    2nd May 2018, 18:23 Go to last post
    • Replies: 0
    • Views: 93
    2nd May 2018, 04:59 Go to last post
  13. Innovus CTS for a range of clock

    Started by Anklon, 16th April 2018 06:34
    • Replies: 3
    • Views: 387
    30th April 2018, 15:48 Go to last post
  14. 4-phases dual-rail logic : always valid data

    Started by knoxknox, 30th April 2018 08:35
    • Replies: 0
    • Views: 142
    30th April 2018, 08:35 Go to last post