1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    118,609
Page 1 of 811 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24313

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,656
    klug
    25th March 2007, 08:41 Go to last post

  1. ADS1115 issue for taking values of 4th digit after decimal point

    Started by RenesasT, Yesterday 09:36
    • Replies: 2
    • Views: 67
    FvM
    Yesterday, 14:22 Go to last post

  2. [moved] Learning DFT as an intern and need help with .dft.v files

    Started by linaxus, 12th April 2019 01:08
    • Replies: 1
    • Views: 177
    vipul982
    Yesterday, 06:20 Go to last post

  3. Design Compiler Register Retiming and CDC

    Started by mwb, 24th April 2019 10:48
    • Replies: 1
    • Views: 93
    ThisIsNotSam
    24th April 2019, 13:30 Go to last post

  4. 32x32 Single Cycle Fast Multiplier

    Started by Mr.PAP, 18th April 2019 12:56
    • Replies: 10
    • Views: 1,535
    Mr.PAP
    24th April 2019, 06:25 Go to last post

  5. Moved: How to design a crystall oscilator circuit using CMOS 40106 DESIGN

    Started by thandana, 23rd April 2019 13:45
    •  
    •  

  6. Synth. area reduced when adding a pipeline register

    Started by oAwad, 22nd April 2019 22:02
    • Replies: 4
    • Views: 304
    ThisIsNotSam
    23rd April 2019, 14:56 Go to last post

  7. priority on two asynch triggered events

    Started by stanford, 18th April 2019 23:50
    2 Attachment(s)
    • Replies: 13
    • Views: 1,015
    ads-ee
    22nd April 2019, 18:14 Go to last post

  8. what $finish will be sythesis to in verilog?

    Started by liletian, 21st April 2019 19:05
    • Replies: 5
    • Views: 204
    dave_59
    22nd April 2019, 15:54 Go to last post

  9. Generated clocks in design compiler

    Started by xdaanx, 20th April 2019 12:52
    1 Attachment(s)
    • Replies: 0
    • Views: 146
    xdaanx
    20th April 2019, 12:52 Go to last post

  10. 6T SRAM read/write current

    Started by Windywast, 18th April 2019 20:30
    • Replies: 2
    • Views: 125
    dick_freebird
    18th April 2019, 22:03 Go to last post

  11. Writing ModelSim do files

    Started by tahirsengine, 18th April 2019 07:54
    • Replies: 1
    • Views: 194
    dpaul
    18th April 2019, 10:55 Go to last post

  12. Trouble inserting level shifters with upf and design compiler

    Started by beeflobill, 8th April 2019 19:20
    • Replies: 3
    • Views: 1,005
    ThisIsNotSam
    16th April 2019, 18:10 Go to last post

  13. [Verilog] Asynchronous Reset

    Started by EEPuppyPuppy, 15th April 2019 21:13
    • Replies: 5
    • Views: 285
    FvM
    16th April 2019, 07:58 Go to last post

  14. Design to state position of first one from lsb every clock for parallel data coming

    Started by fragnen, 12th April 2019 14:18
    • Replies: 8
    • Views: 1,080
    stanford
    15th April 2019, 18:53 Go to last post

  15. Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 1
    • Views: 122
    oratie
    12th April 2019, 16:53 Go to last post

  16. DFT pins disabled during LEC

    Started by fragnen, 12th April 2019 14:41
    • Replies: 0
    • Views: 112
    fragnen
    12th April 2019, 14:41 Go to last post

  17. Reset during lec between rtl and synthesized netlist

    Started by fragnen, 12th April 2019 14:12
    • Replies: 1
    • Views: 392
    ThisIsNotSam
    12th April 2019, 14:30 Go to last post

  18. Single SPI SS to control multiple devices

    Started by tahirsengine, 12th April 2019 08:07
    • Replies: 1
    • Views: 202
    KlausST
    12th April 2019, 08:25 Go to last post

  19. [SOLVED] [moved] Parameterized Module in Design Compiler

    Started by blindscience, 10th April 2019 18:49
    • Replies: 1
    • Views: 159
    blindscience
    10th April 2019, 22:17 Go to last post

  20. RedHawk PowerGrid analysis. what are key parameters

    Started by reddvoid, 8th April 2019 07:24
    1 Attachment(s)
    • Replies: 0
    • Views: 168
    reddvoid
    8th April 2019, 08:49 Go to last post

  21. Hierarchical and Flat LEC

    Started by fragnen, 5th April 2019 08:37
    • Replies: 0
    • Views: 280
    fragnen
    5th April 2019, 08:37 Go to last post

  22. Cadence SimVision waveform dump for parameterized multibit signals

    Started by swabhi812, 4th April 2019 22:53
    • Replies: 0
    • Views: 164
    swabhi812
    4th April 2019, 22:53 Go to last post

  23. Handling LEC for multibit flipflop

    Started by fragnen, 3rd April 2019 14:47
    • Replies: 0
    • Views: 291
    fragnen
    3rd April 2019, 14:47 Go to last post

  24. Digital on top mixed signal design

    Started by Alexxk, 2nd April 2019 14:41
    • Replies: 1
    • Views: 589
    ThisIsNotSam
    2nd April 2019, 18:24 Go to last post

  25. Verdi dump wave compatibility setting

    Started by luoyanghero, 2nd April 2019 07:26
    • Replies: 0
    • Views: 139
    luoyanghero
    2nd April 2019, 07:26 Go to last post

  26. Test vector patterns in LEC

    Started by Fati_hv, 20th February 2019 09:40
    • Replies: 1
    • Views: 347
    Fati_hv
    1st April 2019, 09:38 Go to last post

  27. SCRIPT Find out all the logical drivers of a pin of any standard cell in the netlist?

    Started by QuyVo, 28th March 2019 19:50
    1 Attachment(s)
    • Replies: 8
    • Views: 2,356
    ThisIsNotSam
    31st March 2019, 20:11 Go to last post

  28. Three-state buffer cell characterization

    Started by dr_kca, 29th March 2019 08:57
    • Replies: 0
    • Views: 169
    dr_kca
    29th March 2019, 08:57 Go to last post

  29. fsm for detecting if a number is divisible by 5 when lsb comes first

    Started by rtldesign, 25th March 2019 22:01
    1 Attachment(s)
    • Replies: 16
    • Views: 1,811
    dpaul
    28th March 2019, 09:27 Go to last post

  30. How does Primetime work?

    Started by badari259, 27th March 2019 14:59
    • Replies: 1
    • Views: 212
    ThisIsNotSam
    27th March 2019, 16:40 Go to last post
Powered by vBulletin™
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.