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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,776
    25th March 2007, 08:41 Go to last post
  1. Timing during Synthesis: Max clock frequency

    Started by Alexxk, 13th December 2018 14:34
    • Replies: 3
    • Views: 139
    Yesterday, 18:44 Go to last post
  2. fifo with ram or flops

    Started by stanford, 13th December 2018 01:40
    • Replies: 4
    • Views: 177
    13th December 2018, 15:46 Go to last post
    • Replies: 1
    • Views: 121
    12th December 2018, 11:05 Go to last post
  3. Sanity check of NETLIST

    Started by Alishetty, 8th December 2018 17:26
    • Replies: 3
    • Views: 315
    9th December 2018, 17:53 Go to last post
  4. DFT interview questions

    Started by Nitin1245, 29th November 2018 05:36
    • Replies: 2
    • Views: 540
    30th November 2018, 23:12 Go to last post
  5. Difference between NETLIST and GOLDEN NETLIST?

    Started by Alishetty, 23rd November 2018 07:25
    • Replies: 5
    • Views: 466
    29th November 2018, 14:40 Go to last post
  6. How do you reduce Atpg Abort faults?

    Started by g_eashwar, 23rd November 2018 14:53
    • Replies: 0
    • Views: 213
    23rd November 2018, 14:53 Go to last post
  7. Where can I find an IFC Verilog implementation?

    Started by oho, 21st November 2018 12:00
    • Replies: 1
    • Views: 235
    21st November 2018, 17:13 Go to last post
    • Replies: 1
    • Views: 197
    21st November 2018, 05:54 Go to last post
  8. Pico second precision up counter

    Started by npsnpsnps, 14th November 2018 12:21
    • Replies: 9
    • Views: 692
    20th November 2018, 05:47 Go to last post
  9. I have a Micro Code design assignment, how to proceed?

    Started by kaushikrvs, 17th November 2018 20:51
    • Replies: 1
    • Views: 343
    18th November 2018, 15:51 Go to last post
    • Replies: 1
    • Views: 255
    15th November 2018, 03:17 Go to last post
    • Replies: 1
    • Views: 262
    14th November 2018, 09:05 Go to last post
  10. Ringing between pads and digital inputs?

    Started by Alexxk, 13th November 2018 08:28
    • Replies: 4
    • Views: 296
    13th November 2018, 18:50 Go to last post
  11. What does this mean in standard cell library?

    Started by liletian, 13th November 2018 07:14
    • Replies: 1
    • Views: 194
    13th November 2018, 08:32 Go to last post
  12. Prime Time power estimation whith .spef file

    Started by jmaileh.b, 12th November 2018 08:00
    • Replies: 0
    • Views: 200
    12th November 2018, 08:00 Go to last post
  13. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 5
    • Views: 656
    10th November 2018, 17:51 Go to last post
  14. How do I synthesize an inout port using DC?

    Started by kos8108, 27th August 2018 14:55
    • Replies: 1
    • Views: 287
    9th November 2018, 21:41 Go to last post
    • Replies: 1
    • Views: 260
    9th November 2018, 15:22 Go to last post
  15. what is the usage of the port in the fpga?

    Started by liletian, 28th August 2018 19:12
    • Replies: 4
    • Views: 449
    9th November 2018, 10:26 Go to last post
    • Replies: 3
    • Views: 275
    8th November 2018, 08:35 Go to last post
  16. SiliconSmart set_config_opt for individual bus pins

    Started by jiminization, 8th November 2018 07:21
    • Replies: 0
    • Views: 116
    8th November 2018, 07:21 Go to last post
  17. What does this mean in RC?

    Started by liletian, 6th November 2018 01:17
    • Replies: 6
    • Views: 490
    7th November 2018, 23:46 Go to last post
  18. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 3
    • Views: 419
    6th November 2018, 22:32 Go to last post
  19. Bottom up synthesis using dc compiler

    Started by IngleA, 23rd October 2018 18:45
    • Replies: 1
    • Views: 224
    6th November 2018, 22:25 Go to last post
  20. SiliconSmart Multi-Bit definition

    Started by jiminization, 6th November 2018 12:00
    • Replies: 0
    • Views: 132
    6th November 2018, 12:00 Go to last post
    • Replies: 6
    • Views: 456
    5th November 2018, 21:30 Go to last post
  21. [SOLVED] Parasitic Extraction for New Standard Cells

    Started by ranaya, 5th November 2018 10:23
    • Replies: 0
    • Views: 179
    5th November 2018, 10:23 Go to last post
  22. SiliconSmart clock gating cells

    Started by jiminization, 5th November 2018 04:51
    • Replies: 0
    • Views: 129
    5th November 2018, 04:51 Go to last post
  23. What are the port in the digital design?

    Started by liletian, 3rd November 2018 03:09
    • Replies: 2
    • Views: 383
    4th November 2018, 01:57 Go to last post