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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 37,288
    klug
    25th March 2007, 08:41 Go to last post

  1. DFT -lbist pattern simulation

    Started by avinashkumar, Yesterday 12:57
    • Replies: 0
    • Views: 71
    avinashkumar
    Yesterday, 12:57 Go to last post

  2. DFT compiler commands

    Started by chis4yu, Yesterday 08:20
    • Replies: 0
    • Views: 98
    chis4yu
    Yesterday, 08:20 Go to last post

  3. Memory repair with efuse and bira

    Started by mona_patel, Yesterday 06:09
    • Replies: 0
    • Views: 99
    mona_patel
    Yesterday, 06:09 Go to last post

  4. Tetramax custom patterns

    Started by chis4yu, 25th May 2020 22:26
    • Replies: 0
    • Views: 94
    chis4yu
    25th May 2020, 22:26 Go to last post

  5. DRC rules for Double Pattern Test

    Started by aditya1579, 25th May 2020 08:53
    • Replies: 1
    • Views: 157
    ThisIsNotSam
    25th May 2020, 18:39 Go to last post

  6. Floorplanning Guidelines for TSMC 7nm

    Started by aditya1579, 21st May 2020 12:47
    • Replies: 5
    • Views: 394
    ThisIsNotSam
    24th May 2020, 09:54 Go to last post

  7. DFT compiler with multimodes

    Started by chis4yu, 23rd May 2020 01:21
    • Replies: 0
    • Views: 153
    chis4yu
    23rd May 2020, 01:21 Go to last post

  8. Port placement in a design block

    Started by karthikshetty, 22nd May 2020 05:01
    • Replies: 0
    • Views: 253
    karthikshetty
    22nd May 2020, 05:01 Go to last post

  9. COmparator using xor gate

    Started by djc, 20th May 2020 07:41
    • Replies: 6
    • Views: 355
    djc
    21st May 2020, 10:13 Go to last post

  10. CADENCE is disabling functions alone

    Started by lufer17, 18th May 2020 14:28
    2 Attachment(s)
    • Replies: 6
    • Views: 363
    dick_freebird
    20th May 2020, 22:20 Go to last post

  11. CADENCE: layout error

    Started by lufer17, 18th May 2020 14:45
    3 Attachment(s)
    • Replies: 8
    • Views: 414
    lufer17
    20th May 2020, 15:05 Go to last post

  12. MBIST clocks synchronization

    Started by mona_patel, 19th May 2020 07:13
    • Replies: 2
    • Views: 246
    mona_patel
    20th May 2020, 10:32 Go to last post

  13. How to do post layout simulation during digital ASIC design?

    Started by daskk62, 12th May 2020 17:41
    • Replies: 7
    • Views: 604
    ranaya
    19th May 2020, 15:30 Go to last post

  14. [SOLVED] P&R Buffer Reduction in a Shift Register

    Started by ranaya, 17th May 2020 18:02
    2 Attachment(s)
    • Replies: 8
    • Views: 408
    ThisIsNotSam
    19th May 2020, 15:28 Go to last post

  15. Capacitance effect due to more vias and metal straps.

    Started by reddvoid, 17th May 2020 19:00
    • Replies: 2
    • Views: 340
    ranaya
    19th May 2020, 15:20 Go to last post

  16. Plotting delay vs. load capacitance in Hspice

    Started by reddvoid, 19th May 2020 08:34
    • Replies: 0
    • Views: 144
    reddvoid
    19th May 2020, 08:34 Go to last post

  17. VCS2016 cannot compile ok

    Started by luoyanghero, 18th May 2020 11:09
    • Replies: 0
    • Views: 243
    luoyanghero
    18th May 2020, 11:09 Go to last post

  18. Characterisation of standard cell libraries using cadence tool

    Started by BB11, 13th May 2020 09:09
    • Replies: 1
    • Views: 266
    reddvoid
    17th May 2020, 19:05 Go to last post

  19. Creating Verilog wrapper around a system Verilog DDR4 memory model from micron

    Started by Dude99, 15th May 2020 01:07
    • Replies: 2
    • Views: 321
    dave_59
    16th May 2020, 01:33 Go to last post

  20. ModelSim/QuestaSim SE/PE versions -> what's mean?

    Started by ivlsi, 15th May 2020 13:17
    • Replies: 1
    • Views: 211
    srizbf
    15th May 2020, 15:34 Go to last post

  21. Sequential depth in DFT

    Started by msancheti, 15th May 2020 12:49
    • Replies: 0
    • Views: 127
    msancheti
    15th May 2020, 12:49 Go to last post

  22. TCL script to automate macro placement in icc shell

    Started by Hamsha22, 15th May 2020 02:06
    • Replies: 0
    • Views: 168
    Hamsha22
    15th May 2020, 02:06 Go to last post

  23. In Synopsys ICC2, how do I view metal fill shapes for DEF?

    Started by tro2212, 14th May 2020 18:12
    • Replies: 0
    • Views: 158
    tro2212
    14th May 2020, 18:12 Go to last post

  24. Other end arrival time

    Started by guptya, 6th May 2020 13:19
    2 Attachment(s)
    • Replies: 7
    • Views: 825
    guptya
    14th May 2020, 11:02 Go to last post

  25. Modelsim Coverage Reporting

    Started by Battawi, 12th May 2020 22:16
    • Replies: 3
    • Views: 358
    Battawi
    13th May 2020, 15:34 Go to last post

  26. Design Compiler Input to Output Delay Constraints for A Shift Register

    Started by ranaya, 7th May 2020 09:52
    1 Attachment(s)
    • Replies: 7
    • Views: 529
    kungchuking
    8th May 2020, 11:43 Go to last post

  27. [SOLVED] Zero Values For Internal Power

    Started by janthonym, 6th May 2020 18:51
    • Replies: 2
    • Views: 290
    ranaya
    7th May 2020, 12:08 Go to last post

  28. RTL and constraints for DFT normal and scan clocks

    Started by sherif123, 7th May 2020 11:40
    • Replies: 0
    • Views: 194
    sherif123
    7th May 2020, 11:40 Go to last post

  29. How to convert DEF to LEF in Synopsys ICC2? (IC Compiler)

    Started by tro2212, 4th May 2020 17:34
    • Replies: 1
    • Views: 795
    ThisIsNotSam
    7th May 2020, 09:11 Go to last post

  30. Cadence simulation graph versus time

    Started by lufer17, 6th May 2020 20:28
    1 Attachment(s)
    • Replies: 1
    • Views: 282
    pancho_hideboo
    7th May 2020, 05:39 Go to last post
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