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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,377
    25th March 2007, 08:41 Go to last post
  1. Static timing analysis

    Started by gaurp, 17th March 2019 20:38
    • Replies: 3
    • Views: 172
    Yesterday, 18:57 Go to last post
  2. Clock cells adding jitter to clock

    Started by stanford, 18th March 2019 09:31
    • Replies: 6
    • Views: 151
    18th March 2019, 19:03 Go to last post
  3. minimum depth for data streaming through async fifo

    Started by stanford, 14th March 2019 19:46
    2 Pages
    1 2
    • Replies: 24
    • Views: 433
    18th March 2019, 16:40 Go to last post
  4. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 4
    • Views: 606
    18th March 2019, 08:22 Go to last post
  5. Question related to high latency

    Started by kirankumark0489, 19th February 2019 23:34
    • Replies: 4
    • Views: 334
    17th March 2019, 22:46 Go to last post
    • Replies: 1
    • Views: 157
    16th March 2019, 04:59 Go to last post
  6. Export Spectre XPS-MS simulation into VCD

    Started by LostEagle, 15th March 2019 00:22
    • Replies: 0
    • Views: 86
    15th March 2019, 00:22 Go to last post
  7. Clock domain crossing problem

    Started by biju4u90, 11th March 2019 19:39
    • Replies: 9
    • Views: 454
    14th March 2019, 19:45 Go to last post
  8. Mentor DFT tool- supra ATPG- EDT patterns

    Started by finsiherfish, 12th March 2019 21:29
    • Replies: 0
    • Views: 126
    12th March 2019, 21:29 Go to last post
    • Replies: 3
    • Views: 205
    12th March 2019, 15:17 Go to last post
    • Replies: 0
    • Views: 149
    10th March 2019, 23:40 Go to last post
  9. reliable low latency low complexity viterbi decoder

    Started by jisna, 8th March 2019 07:03
    • Replies: 1
    • Views: 265
    8th March 2019, 08:11 Go to last post
  10. Reverse case statement with multiple matches

    Started by stanford, 6th March 2019 00:52
    • Replies: 4
    • Views: 345
    7th March 2019, 03:30 Go to last post
    • Replies: 2
    • Views: 272
    6th March 2019, 20:38 Go to last post
  11. AI Accelerators hardware for AI applications

    Started by stanford, 3rd March 2019 07:43
    • Replies: 4
    • Views: 475
    4th March 2019, 14:25 Go to last post
  12. Export cadence schematic top view into hierarchy pdf

    Started by LostEagle, 27th February 2019 20:48
    • Replies: 0
    • Views: 105
    27th February 2019, 20:48 Go to last post
    • Replies: 1
    • Views: 206
    27th February 2019, 15:29 Go to last post
    • Replies: 0
    • Views: 118
    26th February 2019, 21:15 Go to last post
    • Replies: 2
    • Views: 230
    26th February 2019, 13:13 Go to last post
  13. Using libraries in Leonardo Spectrum.

    Started by NehaJain1234, 26th February 2019 09:52
    • Replies: 0
    • Views: 133
    26th February 2019, 09:52 Go to last post
  14. Up counter or down counter

    Started by stanford, 24th February 2019 11:20
    • Replies: 3
    • Views: 380
    25th February 2019, 11:12 Go to last post
  15. Logical and physical 0.13 or 0.18 um technology library

    Started by Abdo18, 20th February 2019 20:45
    • Replies: 1
    • Views: 225
    22nd February 2019, 22:10 Go to last post
  16. how does insertion delay affect timing

    Started by stanford, 22nd February 2019 20:02
    • Replies: 1
    • Views: 152
    22nd February 2019, 22:07 Go to last post
  17. Liberate - Custom Cell Characterization

    Started by manpmanp, 22nd February 2019 17:10
    • Replies: 1
    • Views: 136
    22nd February 2019, 19:53 Go to last post
    • Replies: 5
    • Views: 330
    22nd February 2019, 16:08 Go to last post
  18. rtl code to find the smallest

    Started by stanford, 20th February 2019 08:47
    • Replies: 10
    • Views: 529
    21st February 2019, 23:34 Go to last post
  19. LBIST architecture - Industry standards

    Started by Nanda_DFT, 20th February 2019 06:09
    • Replies: 1
    • Views: 141
    21st February 2019, 11:54 Go to last post
  20. Test-per-scan v/s Test-per-clock

    Started by Nanda_DFT, 20th February 2019 06:11
    • Replies: 1
    • Views: 153
    21st February 2019, 11:50 Go to last post