1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    122,542
Page 1 of 816 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24451

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,792
    25th March 2007, 08:41 Go to last post
  1. Gate Level Simulation

    Started by fragnen, 16th September 2019 10:13
    • Replies: 7
    • Views: 288
    Yesterday, 13:08 Go to last post
  2. Lockup Latch for DFT purpose

    Started by Varun124, 3rd July 2019 19:34
    • Replies: 8
    • Views: 449
    Yesterday, 11:46 Go to last post
    • Replies: 5
    • Views: 306
    17th September 2019, 18:33 Go to last post
  3. vcd file generation for netlist

    Started by maru2488, 4th September 2019 07:19
    • Replies: 2
    • Views: 190
    17th September 2019, 12:45 Go to last post
    • Replies: 1
    • Views: 299
    17th September 2019, 11:27 Go to last post
  4. scan chain inside memory

    Started by fragnen, 13th September 2019 09:19
    • Replies: 4
    • Views: 223
    16th September 2019, 12:32 Go to last post
  5. I2C not working properly

    Started by rmachado, 2nd September 2019 14:39
    2 Pages
    1 2
    • Replies: 20
    • Views: 976
    14th September 2019, 20:36 Go to last post
  6. Overwrite cell delay.

    Started by Yussef, 11th September 2019 13:46
    • Replies: 4
    • Views: 257
    12th September 2019, 14:04 Go to last post
  7. SAIF file generation in VCS tool

    Started by maru2488, 6th September 2019 10:23
    • Replies: 0
    • Views: 203
    6th September 2019, 10:23 Go to last post
    • Replies: 1
    • Views: 235
    6th September 2019, 06:55 Go to last post
  8. Inducing delays in WGL files

    Started by tahirsengine, 5th September 2019 14:17
    • Replies: 0
    • Views: 180
    5th September 2019, 14:17 Go to last post
  9. Warnings in nano route in innovus

    Started by Chinmaye, 5th September 2019 11:18
    • Replies: 1
    • Views: 160
    5th September 2019, 12:06 Go to last post
  10. DFT- Circuit Netlist

    Started by avinashkumar, 1st September 2019 15:57
    • Replies: 2
    • Views: 356
    5th September 2019, 03:53 Go to last post
  11. Using multilayer AHB-Lite

    Started by Haraldovs, 3rd September 2019 11:27
    • Replies: 3
    • Views: 275
    4th September 2019, 08:23 Go to last post
    • Replies: 3
    • Views: 426
    4th September 2019, 07:26 Go to last post
  12. Different ways of reading design in ICC

    Started by Dan_Yang, 2nd September 2019 16:14
    • Replies: 2
    • Views: 207
    3rd September 2019, 14:45 Go to last post
  13. Time Constraints in Placement

    Started by Dan_Yang, 2nd September 2019 16:19
    • Replies: 2
    • Views: 273
    3rd September 2019, 12:07 Go to last post
  14. SRAM1RW512x32 module for PULPino microprocessor

    Started by Abdo_Mgdy, 1st September 2019 10:05
    • Replies: 0
    • Views: 131
    1st September 2019, 10:05 Go to last post
  15. Difference between mebes & Job Deck

    Started by RohithRaj, 31st August 2019 17:02
    • Replies: 0
    • Views: 153
    31st August 2019, 17:02 Go to last post
    • Replies: 3
    • Views: 303
    31st August 2019, 08:19 Go to last post
  16. [SOLVED] [moved] Routing signal like clock tree in Cadence Encounter

    Started by Abdo_Mgdy, 27th August 2019 13:40
    • Replies: 3
    • Views: 297
    31st August 2019, 08:18 Go to last post
  17. power analysis using synopsys DC compiler

    Started by avishek_sinha_roy, 28th August 2019 19:03
    • Replies: 5
    • Views: 388
    30th August 2019, 11:54 Go to last post
  18. Beginning and end of a time step

    Started by stanford, 22nd August 2019 02:59
    • Replies: 11
    • Views: 779
    29th August 2019, 07:29 Go to last post
  19. Verifying Large ASIC

    Started by khtsoi, 26th August 2019 14:55
    • Replies: 6
    • Views: 596
    28th August 2019, 07:58 Go to last post
  20. AMBA AXI AxLOCK brief

    Started by surerdra, 27th August 2019 05:27
    • Replies: 1
    • Views: 255
    27th August 2019, 16:01 Go to last post
  21. For doing ECO on netlist

    Started by fragnen, 26th August 2019 08:16
    • Replies: 7
    • Views: 428
    27th August 2019, 10:03 Go to last post