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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,209
    klug
    25th March 2007, 08:41 Go to last post

  1. DFT parallel pattern simulation mismatch analysis

    Started by Vignesh_J, Yesterday 13:33
    • Replies: 1
    • Views: 82
    Tieny
    Today, 04:34 Go to last post

  2. max_transition Violation

    Started by vyella1, Yesterday 22:17
    • Replies: 0
    • Views: 72
    vyella1
    Yesterday, 22:17 Go to last post

  3. For DFT perspective ,what happens when there are no capture clock

    Started by Varun124, 28th September 2019 08:31
    • Replies: 4
    • Views: 436
    Tieny
    Yesterday, 09:46 Go to last post

  4. Synopsys DC: Tracing clock path

    Started by vaibhava, Yesterday 08:36
    • Replies: 0
    • Views: 54
    vaibhava
    Yesterday, 08:36 Go to last post

  5. What are the meaings of the following Calibre warnings

    Started by aditya1579, Yesterday 03:44
    • Replies: 1
    • Views: 109
    wwfeldman
    Yesterday, 04:10 Go to last post

  6. [moved] Value of lateral electric field(E0) in UMC 65 technology

    Started by abhishek260, 11th November 2019 12:41
    • Replies: 2
    • Views: 326
    timof
    12th November 2019, 02:31 Go to last post

  7. What is meant by Split CODEC IN DFT ?

    Started by Varun124, 12th October 2019 10:18
    • Replies: 1
    • Views: 293
    Tieny
    11th November 2019, 10:15 Go to last post

  8. LBIST low test coverage

    Started by vijay82, 23rd October 2019 08:21
    • Replies: 5
    • Views: 444
    Tieny
    11th November 2019, 10:07 Go to last post

  9. MBIST DONE & GO failing conditions

    Started by vipul982, 6th November 2019 14:13
    • Replies: 1
    • Views: 248
    Tieny
    11th November 2019, 10:03 Go to last post

  10. How to generate sine wave using Verilog?

    Started by h_upadhyay, 9th November 2019 06:59
    • Replies: 5
    • Views: 350
    FvM
    10th November 2019, 10:40 Go to last post

  11. [moved] What is Cadence genus synthesis, report power?

    Started by daskk62, 8th November 2019 18:50
    • Replies: 1
    • Views: 229
    ThisIsNotSam
    9th November 2019, 09:02 Go to last post

  12. External C++ compilation and DPI question

    Started by ghertz, 1st November 2019 23:39
    • Replies: 14
    • Views: 568
    ghertz
    6th November 2019, 00:20 Go to last post

  13. In PrimeTime, is there a similar command for setting output load cell to all outputs?

    Started by majd229, 5th November 2019 18:27
    • Replies: 0
    • Views: 174
    majd229
    5th November 2019, 18:27 Go to last post

  14. What is Negative timing checks

    Started by Varun124, 5th November 2019 11:32
    • Replies: 1
    • Views: 118
    ThisIsNotSam
    5th November 2019, 12:49 Go to last post

  15. SiliconSmart pin and lib file

    Started by xabosexi, 4th November 2019 08:04
    • Replies: 1
    • Views: 128
    ThisIsNotSam
    4th November 2019, 12:22 Go to last post

  16. Mipi D-phy physical layer implementation

    Started by MaheshC, 4th November 2019 10:33
    • Replies: 0
    • Views: 107
    MaheshC
    4th November 2019, 10:33 Go to last post

  17. How does aging is conducted exactly in Cadence?

    Started by antlhem, 31st October 2019 11:42
    3 Attachment(s)
    • Replies: 3
    • Views: 389
    antlhem
    2nd November 2019, 14:25 Go to last post

  18. How to measure the C parasitic (internal capacitance) of an inverter using Spectre ?

    Started by Puppet123, 26th October 2019 14:35
    2 Attachment(s)
    • Replies: 17
    • Views: 1,230
    timof
    31st October 2019, 17:22 Go to last post

  19. Moved: CMOS ring oscillator frequency degradation through years

    Started by antlhem, 2nd November 2019 15:00
    •  
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  20. Voltage drop of on die power gating cells

    Started by volsky, 29th October 2019 07:34
    • Replies: 4
    • Views: 300
    ThisIsNotSam
    30th October 2019, 12:19 Go to last post

  21. [SOLVED] Preventing using a certain cell in cadence encounter

    Started by Abdo_Mgdy, 29th October 2019 12:39
    • Replies: 2
    • Views: 196
    Abdo_Mgdy
    29th October 2019, 14:22 Go to last post

  22. Solution for ICC mismatch in units

    Started by Vlsi24, 29th October 2019 08:06
    • Replies: 0
    • Views: 96
    Vlsi24
    29th October 2019, 08:06 Go to last post

  23. Getting exact values of VIL, VOL, VIH and VOH ?

    Started by Robotduck, 25th October 2019 15:35
    • Replies: 0
    • Views: 243
    Robotduck
    25th October 2019, 15:35 Go to last post

  24. Transient Simulation in Cadence

    Started by KingDarius6288, 24th October 2019 02:33
    • Replies: 2
    • Views: 283
    ThisIsNotSam
    24th October 2019, 08:00 Go to last post

  25. How to identify design in terms of track ?

    Started by kartikpujari, 4th October 2019 09:49
    • Replies: 2
    • Views: 379
    vijay82
    24th October 2019, 06:03 Go to last post

  26. is accellera UVM free?

    Started by liletian, 23rd October 2019 18:56
    • Replies: 1
    • Views: 191
    dave_59
    23rd October 2019, 21:33 Go to last post

  27. How to fix unclocked register?

    Started by kartikpujari, 20th October 2019 18:50
    • Replies: 1
    • Views: 430
    ThisIsNotSam
    21st October 2019, 07:04 Go to last post

  28. Usage of Synchronous and Asynchronuos FIFOs

    Started by Muthuraja.M, 20th October 2019 09:29
    • Replies: 2
    • Views: 350
    ads-ee
    20th October 2019, 17:45 Go to last post

  29. Can IP(Intellectual Property) open source, what does good business model?

    Started by luoyanghero, 13th October 2019 04:07
    • Replies: 6
    • Views: 866
    dick_freebird
    20th October 2019, 01:50 Go to last post

  30. What cells are placed around RAM? Why?

    Started by Dan_Yang, 8th October 2019 15:04
    • Replies: 2
    • Views: 648
    visky2096
    17th October 2019, 10:44 Go to last post
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