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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,077
    25th March 2007, 08:41 Go to last post
  1. Design compiler synthesis

    Started by vyella1, Today 04:15
    • Replies: 0
    • Views: 11
    Today, 04:15 Go to last post
    • Replies: 1
    • Views: 97
    23rd June 2019, 15:07 Go to last post
    • Replies: 10
    • Views: 359
    22nd June 2019, 18:55 Go to last post
  2. [SOLVED] Synposys Tcyc not observed

    Started by blindscience, 19th June 2019 18:29
    • Replies: 1
    • Views: 132
    21st June 2019, 18:24 Go to last post
  3. Ripple-borrow binary subtraction circuit

    Started by promach, 20th June 2019 08:52
    • Replies: 2
    • Views: 153
    20th June 2019, 15:55 Go to last post
    • Replies: 0
    • Views: 97
    20th June 2019, 04:53 Go to last post
  4. How to clock gate in hierarchy?

    Started by DimitrisStathis, 17th June 2019 17:29
    • Replies: 5
    • Views: 211
    18th June 2019, 18:06 Go to last post
  5. Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 4
    • Views: 295
    18th June 2019, 09:29 Go to last post
  6. Coverage improvement from AU.TC faults

    Started by aakashaspires, 17th June 2019 08:59
    • Replies: 1
    • Views: 101
    17th June 2019, 16:17 Go to last post
  7. meaning of placeable cells

    Started by sharanbr123, 14th June 2019 12:52
    • Replies: 2
    • Views: 179
    14th June 2019, 17:23 Go to last post
    • Replies: 1
    • Views: 174
    12th June 2019, 14:16 Go to last post
    • Replies: 0
    • Views: 110
    12th June 2019, 09:00 Go to last post
  8. ATPG Test Coverage for stuck@ and @speed

    Started by sandy2811, 25th March 2019 15:08
    • Replies: 3
    • Views: 334
    11th June 2019, 07:16 Go to last post
    • Replies: 1
    • Views: 218
    11th June 2019, 07:07 Go to last post
  9. [moved] Digital Transition Capture

    Started by minhchau, 8th June 2019 16:40
    • Replies: 11
    • Views: 570
    10th June 2019, 19:40 Go to last post
    • Replies: 4
    • Views: 189
    10th June 2019, 16:01 Go to last post
  10. [SOLVED] How to re-synthesize a circuit with ABC synthesizer?

    Started by amin-ea, 25th May 2019 12:06
    • Replies: 5
    • Views: 369
    10th June 2019, 08:40 Go to last post
  11. [SOLVED] Methodology to calculate the Clock Uncertainity values.

    Started by Wyre, 9th June 2019 10:35
    • Replies: 1
    • Views: 136
    9th June 2019, 16:13 Go to last post
  12. System verilog, fork join_any

    Started by surerdra, 4th June 2019 08:49
    • Replies: 3
    • Views: 313
    5th June 2019, 07:05 Go to last post
    • Replies: 2
    • Views: 257
    3rd June 2019, 15:19 Go to last post
  13. Optimizing case statement with large input

    Started by stanford, 30th May 2019 03:01
    • Replies: 8
    • Views: 730
    1st June 2019, 02:42 Go to last post
  14. if/else vs. if/if in combo logic

    Started by stanford, 30th May 2019 02:09
    • Replies: 10
    • Views: 533
    1st June 2019, 02:39 Go to last post
    • Replies: 2
    • Views: 400
    1st June 2019, 01:46 Go to last post
  15. [SOLVED] Code coverage of a design

    Started by vyella1, 31st May 2019 04:12
    • Replies: 1
    • Views: 218
    31st May 2019, 15:50 Go to last post