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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,622
    klug
    25th March 2007, 08:41 Go to last post

  1. Logic for calculation of CCS NOISE and publishing in liberty

    Started by Knowledge.seeker, Yesterday 10:10
    • Replies: 1
    • Views: 88
    Knowledge.seeker
    Today, 10:32 Go to last post

  2. SiliconSmart incorrect instance file generated from import command

    Started by jiminization, Today 03:32
    • Replies: 0
    • Views: 76
    jiminization
    Today, 03:32 Go to last post

  3. [Synopsys VCS] Recommended Materials

    Started by ivlsi, Yesterday 17:26
    • Replies: 0
    • Views: 63
    ivlsi
    Yesterday, 17:26 Go to last post

  4. What does design for test engineer in VLSI do? How is the job?

    Started by Nitin1245, Yesterday 12:06
    • Replies: 1
    • Views: 76
    dpaul
    Yesterday, 13:25 Go to last post

  5. [SOLVED] Hold time violations in post layout simulation (Although STA is fine)

    Started by ranaya, 12th October 2018 10:00
    • Replies: 5
    • Views: 189
    ranaya
    Yesterday, 12:35 Go to last post

  6. Amba ahb slave interface for external memory control(rom,sram)

    Started by surerdra, Yesterday 04:27
    • Replies: 1
    • Views: 86
    dpaul
    Yesterday, 08:28 Go to last post

  7. Multi-vth design not performed

    Started by onta00, 15th October 2018 14:28
    • Replies: 4
    • Views: 144
    onta00
    Yesterday, 07:10 Go to last post

  8. Who will decide the number of metal layers in block level?

    Started by udayalakshmi91, 15th October 2018 09:35
    • Replies: 3
    • Views: 138
    ThisIsNotSam
    15th October 2018, 19:19 Go to last post

  9. CMOS inverter output ?

    Started by IngleA, 1st October 2018 18:49
    • Replies: 8
    • Views: 359
    dick_freebird
    15th October 2018, 18:24 Go to last post

  10. [LEC] Why needed in ASIC flow?

    Started by ivlsi, 23rd August 2018 19:16
    • Replies: 12
    • Views: 886
    NVenki
    15th October 2018, 12:52 Go to last post

  11. Critical Path in a design

    Started by onta00, 11th October 2018 12:06
    • Replies: 4
    • Views: 212
    arvinraj
    15th October 2018, 08:07 Go to last post

  12. SYNOPSIS - Clock creation and delivery to submodules

    Started by kls213, 11th October 2018 17:08
    • Replies: 3
    • Views: 217
    arvinraj
    15th October 2018, 08:05 Go to last post

  13. [SOLVED] Fatal error while running top module || UVM

    Started by ranayehya, 13th October 2018 18:33
    1 Attachment(s)
    • Replies: 4
    • Views: 160
    ranayehya
    14th October 2018, 19:36 Go to last post

  14. Max capacitance violation on macro clk pin

    Started by shragh, 14th October 2018 08:00
    • Replies: 2
    • Views: 103
    shragh
    14th October 2018, 19:10 Go to last post

  15. What is going on with my D flip-flop in Hspice?

    Started by Amamiya_Ren, 12th October 2018 14:35
    5 Attachment(s)
    • Replies: 3
    • Views: 138
    FvM
    12th October 2018, 14:55 Go to last post

  16. One clock cycle delay for the input data

    Started by riz1679, 12th October 2018 09:54
    1 Attachment(s)
    • Replies: 1
    • Views: 81
    KlausST
    12th October 2018, 10:04 Go to last post

  17. Cadence Virtuoso layout.oa file grows in size fast and causes slow rendering

    Started by borabut, 9th October 2018 19:45
    • Replies: 3
    • Views: 176
    ThisIsNotSam
    11th October 2018, 15:11 Go to last post

  18. Unable to resolve reference warning in ic compiler

    Started by gauravsharma93, 11th October 2018 11:41
    • Replies: 0
    • Views: 65
    gauravsharma93
    11th October 2018, 11:41 Go to last post

  19. Closed: Input reference library in synopsys ic compiler tool

    Started by harshahari, 20th April 2018 12:12
    • Replies: 1
    • Views: 373
    gauravsharma93
    11th October 2018, 11:31 Go to last post

  20. How to connect power and ground pads in IC COMPILER

    Started by gauravsharma93, 11th October 2018 11:09
    • Replies: 0
    • Views: 45
    gauravsharma93
    11th October 2018, 11:09 Go to last post

  21. Memory BIST insertion Synopsys flow

    Started by shmd19, 10th October 2018 17:05
    • Replies: 0
    • Views: 85
    shmd19
    10th October 2018, 17:05 Go to last post

  22. Cadence ATPG TCL script

    Started by Nitin1245, 5th October 2018 09:39
    • Replies: 4
    • Views: 238
    dpaul
    8th October 2018, 13:30 Go to last post

  23. ATPG ENCOUNTER TEST (what are the region for broken a scan chain)

    Started by anitha.madala, 8th October 2018 09:02
    • Replies: 1
    • Views: 76
    dpaul
    8th October 2018, 13:28 Go to last post

  24. What are some great papers every vlsi engineer should read?

    Started by kaushikrvs, 6th October 2018 09:22
    • Replies: 1
    • Views: 201
    ThisIsNotSam
    6th October 2018, 19:01 Go to last post

  25. [SOLVED] QuestaSim / ModelSim fatal error during simulation

    Started by riz1679, 5th October 2018 10:44
    1 Attachment(s)
    • Replies: 3
    • Views: 130
    FvM
    5th October 2018, 15:01 Go to last post

  26. Recommendations of tools to generate RTL from C/SystemC?

    Started by javierh.santiago, 28th September 2018 18:17
    • Replies: 5
    • Views: 423
    dpaul
    4th October 2018, 08:36 Go to last post

  27. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 4
    • Views: 314
    wimarshal
    4th October 2018, 08:34 Go to last post

  28. Power Gating Cells in SAED32/29 EDK

    Started by mumichang, 4th October 2018 06:37
    • Replies: 0
    • Views: 84
    mumichang
    4th October 2018, 06:37 Go to last post

  29. Power Measurement Error with Design Compiler?

    Started by mumichang, 4th October 2018 03:37
    • Replies: 0
    • Views: 95
    mumichang
    4th October 2018, 03:37 Go to last post

  30. NC verilog schematic to verilog

    Started by jiminization, 27th September 2018 09:02
    • Replies: 1
    • Views: 169
    ThisIsNotSam
    28th September 2018, 15:13 Go to last post
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