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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,372
    klug
    25th March 2007, 08:41 Go to last post

  1. Static timing analysis

    Started by gaurp, 17th March 2019 20:38
    • Replies: 2
    • Views: 114
    gaurp
    Today, 07:25 Go to last post

  2. Clock cells adding jitter to clock

    Started by stanford, Yesterday 09:31
    • Replies: 6
    • Views: 137
    ThisIsNotSam
    Yesterday, 19:03 Go to last post

  3. minimum depth for data streaming through async fifo

    Started by stanford, 14th March 2019 19:46
    2 Pages •
    1 2
    • Replies: 24
    • Views: 422
    KlausST
    Yesterday, 16:40 Go to last post

  4. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 4
    • Views: 605
    englishdogg
    Yesterday, 08:22 Go to last post

  5. Question related to high latency

    Started by kirankumark0489, 19th February 2019 23:34
    • Replies: 4
    • Views: 334
    Vlsi29
    17th March 2019, 22:46 Go to last post

  6. didn't find inverter for specified operating conditions

    Started by vyella1, 15th March 2019 21:03
    • Replies: 1
    • Views: 156
    stanford
    16th March 2019, 04:59 Go to last post

  7. Export Spectre XPS-MS simulation into VCD

    Started by LostEagle, 15th March 2019 00:22
    • Replies: 0
    • Views: 83
    LostEagle
    15th March 2019, 00:22 Go to last post

  8. Clock domain crossing problem

    Started by biju4u90, 11th March 2019 19:39
    • Replies: 9
    • Views: 454
    swabhi812
    14th March 2019, 19:45 Go to last post

  9. Mentor DFT tool- supra ATPG- EDT patterns

    Started by finsiherfish, 12th March 2019 21:29
    • Replies: 0
    • Views: 126
    finsiherfish
    12th March 2019, 21:29 Go to last post

  10. Async FIFO full generation when read and write frequencies are different

    Started by biju4u90, 12th March 2019 14:43
    • Replies: 3
    • Views: 202
    KlausST
    12th March 2019, 15:17 Go to last post

  11. Looking for Hint: How to output failing vectors in Synopsys Formality?

    Started by kingishm, 10th March 2019 23:40
    2 Attachment(s)
    • Replies: 0
    • Views: 149
    kingishm
    10th March 2019, 23:40 Go to last post

  12. reliable low latency low complexity viterbi decoder

    Started by jisna, 8th March 2019 07:03
    • Replies: 1
    • Views: 265
    KlausST
    8th March 2019, 08:11 Go to last post

  13. Why are the most critical signals in Digital Circuitry are Active low ?

    Started by kaushikrvs, 28th February 2019 21:09
    • Replies: 15
    • Views: 741
    andre_teprom
    7th March 2019, 12:52 Go to last post

  14. Reverse case statement with multiple matches

    Started by stanford, 6th March 2019 00:52
    • Replies: 4
    • Views: 344
    ThisIsNotSam
    7th March 2019, 03:30 Go to last post

  15. latches in timing (do latches get timed as destination or as combo logic)

    Started by stanford, 27th February 2019 20:27
    • Replies: 2
    • Views: 272
    swabhi812
    6th March 2019, 20:38 Go to last post

  16. AI Accelerators hardware for AI applications

    Started by stanford, 3rd March 2019 07:43
    • Replies: 4
    • Views: 475
    ThisIsNotSam
    4th March 2019, 14:25 Go to last post

  17. Export cadence schematic top view into hierarchy pdf

    Started by LostEagle, 27th February 2019 20:48
    2 Attachment(s)
    • Replies: 0
    • Views: 105
    LostEagle
    27th February 2019, 20:48 Go to last post

  18. Error in Cadence RTL Compiler when estimating Power using VCD

    Started by saunaksaha, 26th February 2019 22:52
    • Replies: 1
    • Views: 205
    ThisIsNotSam
    27th February 2019, 15:29 Go to last post

  19. How to debug pattern mismatch during simulation of SOC level patterns- DFT

    Started by finsiherfish, 26th February 2019 21:15
    • Replies: 0
    • Views: 118
    finsiherfish
    26th February 2019, 21:15 Go to last post

  20. [moved] What is the tool used to create .spf file through synopsys?

    Started by Sph, 26th February 2019 07:08
    • Replies: 2
    • Views: 230
    FvM
    26th February 2019, 13:13 Go to last post

  21. Using libraries in Leonardo Spectrum.

    Started by NehaJain1234, 26th February 2019 09:52
    • Replies: 0
    • Views: 132
    NehaJain1234
    26th February 2019, 09:52 Go to last post

  22. Up counter or down counter

    Started by stanford, 24th February 2019 11:20
    • Replies: 3
    • Views: 380
    dpaul
    25th February 2019, 11:12 Go to last post

  23. Logical and physical 0.13 or 0.18 um technology library

    Started by Abdo18, 20th February 2019 20:45
    • Replies: 1
    • Views: 225
    ThisIsNotSam
    22nd February 2019, 22:10 Go to last post

  24. how does insertion delay affect timing

    Started by stanford, 22nd February 2019 20:02
    • Replies: 1
    • Views: 152
    ThisIsNotSam
    22nd February 2019, 22:07 Go to last post

  25. Liberate - Custom Cell Characterization

    Started by manpmanp, 22nd February 2019 17:10
    • Replies: 1
    • Views: 134
    ThisIsNotSam
    22nd February 2019, 19:53 Go to last post

  26. [moved] Area and Gate Equivalent in Leonardo Spectrum Report

    Started by NehaJain1234, 20th February 2019 16:21
    3 Attachment(s)
    • Replies: 5
    • Views: 330
    ThisIsNotSam
    22nd February 2019, 16:08 Go to last post

  27. rtl code to find the smallest

    Started by stanford, 20th February 2019 08:47
    • Replies: 10
    • Views: 529
    ThisIsNotSam
    21st February 2019, 23:34 Go to last post

  28. LBIST architecture - Industry standards

    Started by Nanda_DFT, 20th February 2019 06:09
    • Replies: 1
    • Views: 141
    ArakelTheDragon
    21st February 2019, 11:54 Go to last post

  29. Test-per-scan v/s Test-per-clock

    Started by Nanda_DFT, 20th February 2019 06:11
    • Replies: 1
    • Views: 153
    ArakelTheDragon
    21st February 2019, 11:50 Go to last post

  30. [Moved]: Postlayout simulation of digital ASIC design with vhdl testbench

    Started by gauravsharma93, 21st February 2019 11:21
    • Replies: 0
    • Views: 184
    gauravsharma93
    21st February 2019, 11:21 Go to last post
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