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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,230
    25th March 2007, 08:41 Go to last post
  1. How to generate sine wave using Verilog?

    Started by h_upadhyay, 9th November 2019 06:59
    • Replies: 9
    • Views: 476
    Yesterday, 15:03 Go to last post
  2. DFT Visualizer Data View

    Started by Vignesh_J, 15th November 2019 13:24
    • Replies: 1
    • Views: 162
    15th November 2019, 18:09 Go to last post
  3. Using a BFM in system verification code.

    Started by dipk11, 15th November 2019 07:49
    • Replies: 2
    • Views: 122
    15th November 2019, 10:32 Go to last post
  4. max_transition Violation

    Started by vyella1, 13th November 2019 22:17
    • Replies: 1
    • Views: 143
    14th November 2019, 13:29 Go to last post
  5. Synopsys DC: Tracing clock path

    Started by vaibhava, 13th November 2019 08:36
    • Replies: 1
    • Views: 83
    14th November 2019, 13:27 Go to last post
  6. What are the meaings of the following Calibre warnings

    Started by aditya1579, 13th November 2019 03:44
    • Replies: 2
    • Views: 153
    14th November 2019, 13:25 Go to last post
  7. DFT parallel pattern simulation mismatch analysis

    Started by Vignesh_J, 13th November 2019 13:33
    • Replies: 1
    • Views: 113
    14th November 2019, 04:34 Go to last post
    • Replies: 4
    • Views: 451
    13th November 2019, 09:46 Go to last post
    • Replies: 2
    • Views: 340
    12th November 2019, 02:31 Go to last post
  8. What is meant by Split CODEC IN DFT ?

    Started by Varun124, 12th October 2019 10:18
    • Replies: 1
    • Views: 306
    11th November 2019, 10:15 Go to last post
  9. LBIST low test coverage

    Started by vijay82, 23rd October 2019 08:21
    • Replies: 5
    • Views: 450
    11th November 2019, 10:07 Go to last post
  10. MBIST DONE & GO failing conditions

    Started by vipul982, 6th November 2019 14:13
    • Replies: 1
    • Views: 256
    11th November 2019, 10:03 Go to last post
  11. [moved] What is Cadence genus synthesis, report power?

    Started by daskk62, 8th November 2019 18:50
    • Replies: 1
    • Views: 238
    9th November 2019, 09:02 Go to last post
  12. External C++ compilation and DPI question

    Started by ghertz, 1st November 2019 23:39
    • Replies: 14
    • Views: 574
    6th November 2019, 00:20 Go to last post
  13. What is Negative timing checks

    Started by Varun124, 5th November 2019 11:32
    • Replies: 1
    • Views: 125
    5th November 2019, 12:49 Go to last post
  14. SiliconSmart pin and lib file

    Started by xabosexi, 4th November 2019 08:04
    • Replies: 1
    • Views: 130
    4th November 2019, 12:22 Go to last post
  15. Mipi D-phy physical layer implementation

    Started by MaheshC, 4th November 2019 10:33
    • Replies: 0
    • Views: 107
    4th November 2019, 10:33 Go to last post
  16. How does aging is conducted exactly in Cadence?

    Started by antlhem, 31st October 2019 11:42
    • Replies: 3
    • Views: 395
    2nd November 2019, 14:25 Go to last post
    • Replies: 17
    • Views: 1,240
    31st October 2019, 17:22 Go to last post
  17. Moved: CMOS ring oscillator frequency degradation through years

    Started by antlhem, 2nd November 2019 15:00
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  18. Voltage drop of on die power gating cells

    Started by volsky, 29th October 2019 07:34
    • Replies: 4
    • Views: 303
    30th October 2019, 12:19 Go to last post
  19. [SOLVED] Preventing using a certain cell in cadence encounter

    Started by Abdo_Mgdy, 29th October 2019 12:39
    • Replies: 2
    • Views: 198
    29th October 2019, 14:22 Go to last post
  20. Solution for ICC mismatch in units

    Started by Vlsi24, 29th October 2019 08:06
    • Replies: 0
    • Views: 98
    29th October 2019, 08:06 Go to last post
  21. Getting exact values of VIL, VOL, VIH and VOH ?

    Started by Robotduck, 25th October 2019 15:35
    • Replies: 0
    • Views: 253
    25th October 2019, 15:35 Go to last post
  22. Transient Simulation in Cadence

    Started by KingDarius6288, 24th October 2019 02:33
    • Replies: 2
    • Views: 287
    24th October 2019, 08:00 Go to last post
  23. How to identify design in terms of track ?

    Started by kartikpujari, 4th October 2019 09:49
    • Replies: 2
    • Views: 382
    24th October 2019, 06:03 Go to last post
  24. is accellera UVM free?

    Started by liletian, 23rd October 2019 18:56
    • Replies: 1
    • Views: 195
    23rd October 2019, 21:33 Go to last post
  25. How to fix unclocked register?

    Started by kartikpujari, 20th October 2019 18:50
    • Replies: 1
    • Views: 435
    21st October 2019, 07:04 Go to last post