1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    124,164
Page 1 of 817 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24491

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,192
    25th March 2007, 08:41 Go to last post
    • Replies: 2
    • Views: 277
    Yesterday, 02:31 Go to last post
  1. What is meant by Split CODEC IN DFT ?

    Started by Varun124, 12th October 2019 10:18
    • Replies: 1
    • Views: 290
    11th November 2019, 10:15 Go to last post
  2. LBIST low test coverage

    Started by vijay82, 23rd October 2019 08:21
    • Replies: 5
    • Views: 430
    11th November 2019, 10:07 Go to last post
  3. MBIST DONE & GO failing conditions

    Started by vipul982, 6th November 2019 14:13
    • Replies: 1
    • Views: 239
    11th November 2019, 10:03 Go to last post
  4. How to generate sine wave using Verilog?

    Started by h_upadhyay, 9th November 2019 06:59
    • Replies: 5
    • Views: 331
    10th November 2019, 10:40 Go to last post
  5. [moved] What is Cadence genus synthesis, report power?

    Started by daskk62, 8th November 2019 18:50
    • Replies: 1
    • Views: 218
    9th November 2019, 09:02 Go to last post
  6. External C++ compilation and DPI question

    Started by ghertz, 1st November 2019 23:39
    • Replies: 14
    • Views: 558
    6th November 2019, 00:20 Go to last post
  7. What is Negative timing checks

    Started by Varun124, 5th November 2019 11:32
    • Replies: 1
    • Views: 107
    5th November 2019, 12:49 Go to last post
  8. SiliconSmart pin and lib file

    Started by xabosexi, 4th November 2019 08:04
    • Replies: 1
    • Views: 124
    4th November 2019, 12:22 Go to last post
  9. Mipi D-phy physical layer implementation

    Started by MaheshC, 4th November 2019 10:33
    • Replies: 0
    • Views: 101
    4th November 2019, 10:33 Go to last post
  10. How does aging is conducted exactly in Cadence?

    Started by antlhem, 31st October 2019 11:42
    • Replies: 3
    • Views: 383
    2nd November 2019, 14:25 Go to last post
    • Replies: 17
    • Views: 1,219
    31st October 2019, 17:22 Go to last post
  11. Moved: CMOS ring oscillator frequency degradation through years

    Started by antlhem, 2nd November 2019 15:00
    •  
    •  
  12. Voltage drop of on die power gating cells

    Started by volsky, 29th October 2019 07:34
    • Replies: 4
    • Views: 296
    30th October 2019, 12:19 Go to last post
  13. [SOLVED] Preventing using a certain cell in cadence encounter

    Started by Abdo_Mgdy, 29th October 2019 12:39
    • Replies: 2
    • Views: 192
    29th October 2019, 14:22 Go to last post
  14. Solution for ICC mismatch in units

    Started by Vlsi24, 29th October 2019 08:06
    • Replies: 0
    • Views: 94
    29th October 2019, 08:06 Go to last post
  15. Getting exact values of VIL, VOL, VIH and VOH ?

    Started by Robotduck, 25th October 2019 15:35
    • Replies: 0
    • Views: 241
    25th October 2019, 15:35 Go to last post
  16. Transient Simulation in Cadence

    Started by KingDarius6288, 24th October 2019 02:33
    • Replies: 2
    • Views: 281
    24th October 2019, 08:00 Go to last post
  17. How to identify design in terms of track ?

    Started by kartikpujari, 4th October 2019 09:49
    • Replies: 2
    • Views: 378
    24th October 2019, 06:03 Go to last post
  18. is accellera UVM free?

    Started by liletian, 23rd October 2019 18:56
    • Replies: 1
    • Views: 189
    23rd October 2019, 21:33 Go to last post
  19. How to fix unclocked register?

    Started by kartikpujari, 20th October 2019 18:50
    • Replies: 1
    • Views: 427
    21st October 2019, 07:04 Go to last post
  20. Usage of Synchronous and Asynchronuos FIFOs

    Started by Muthuraja.M, 20th October 2019 09:29
    • Replies: 2
    • Views: 347
    20th October 2019, 17:45 Go to last post
    • Replies: 6
    • Views: 860
    20th October 2019, 01:50 Go to last post
  21. What cells are placed around RAM? Why?

    Started by Dan_Yang, 8th October 2019 15:04
    • Replies: 2
    • Views: 645
    17th October 2019, 10:44 Go to last post
  22. How to create parallel TDL patters in tetramax

    Started by Varun124, 13th October 2019 21:26
    • Replies: 0
    • Views: 235
    13th October 2019, 21:26 Go to last post
    • Replies: 1
    • Views: 500
    11th October 2019, 09:19 Go to last post
    • Replies: 4
    • Views: 611
    10th October 2019, 10:45 Go to last post
    • Replies: 1
    • Views: 268
    9th October 2019, 01:46 Go to last post
  23. Formal verification of AHB bus, arbiter confusion

    Started by Haraldovs, 8th October 2019 07:57
    • Replies: 0
    • Views: 216
    8th October 2019, 07:57 Go to last post