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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,316
    25th March 2007, 08:41 Go to last post
  1. Synopsys VP Virtualizer installation

    Started by yuhiub90, Today 09:09
    • Replies: 0
    • Views: 1
    Today, 09:09 Go to last post
  2. async fifo - almost full/empty

    Started by stanford, 10th June 2018 08:24
    • Replies: 6
    • Views: 249
    Today, 00:53 Go to last post
  3. Non clock cells on clock path

    Started by stanford, Yesterday 23:01
    • Replies: 0
    • Views: 46
    Yesterday, 23:01 Go to last post
    • Replies: 2
    • Views: 64
    Yesterday, 22:42 Go to last post
  4. Memory/macro internal clock insertion delay

    Started by argha, 16th June 2018 20:12
    • Replies: 1
    • Views: 146
    Yesterday, 14:17 Go to last post
  5. Import a layout from Encounter to Virtuoso

    Started by Mahmoud_Dagher, 14th June 2018 14:53
    • Replies: 5
    • Views: 207
    Yesterday, 14:15 Go to last post
    • Replies: 1
    • Views: 88
    Yesterday, 10:16 Go to last post
    • Replies: 2
    • Views: 153
    15th June 2018, 15:36 Go to last post
  6. SPI Slave with strange behavior

    Started by rmachado, 9th June 2018 13:59
    2 Pages
    1 2
    • Replies: 25
    • Views: 597
    15th June 2018, 10:57 Go to last post
  7. SDC constraints for asynchronous reset

    Started by Alexxk, 14th June 2018 12:04
    • Replies: 2
    • Views: 102
    15th June 2018, 10:36 Go to last post
  8. Timing Sign off from Primetime

    Started by sreejinair, 11th June 2018 14:38
    • Replies: 4
    • Views: 274
    12th June 2018, 15:33 Go to last post
  9. UMC 65nm without TLU+ files

    Started by ua6bqg, 8th June 2018 16:30
    • Replies: 1
    • Views: 123
    8th June 2018, 18:00 Go to last post
  10. [moved] Physical design placement timing issue

    Started by prabhu14, 7th June 2018 19:05
    • Replies: 2
    • Views: 175
    8th June 2018, 14:54 Go to last post
  11. Cadence lint error: CLKDMN

    Started by Sam26, 7th June 2018 10:45
    • Replies: 3
    • Views: 171
    8th June 2018, 12:37 Go to last post
  12. [moved] 50Mz to 1 kHz clock generator

    Started by sanjaysharmaiitk, 8th June 2018 09:26
    • Replies: 1
    • Views: 134
    8th June 2018, 10:14 Go to last post
    • Replies: 10
    • Views: 526
    4th June 2018, 11:41 Go to last post
  13. bit width for addition

    Started by sky_above, 2nd June 2018 14:04
    • Replies: 3
    • Views: 220
    3rd June 2018, 22:22 Go to last post
    • Replies: 7
    • Views: 390
    2nd June 2018, 16:10 Go to last post
  14. Output combinational output and valid sequential

    Started by sky_above, 26th May 2018 16:22
    • Replies: 9
    • Views: 400
    2nd June 2018, 15:28 Go to last post
  15. Books or websites to learn digital system design

    Started by sky_above, 2nd June 2018 14:01
    • Replies: 0
    • Views: 130
    2nd June 2018, 14:01 Go to last post
  16. TrueNorth Evaluation Board

    Started by mwn1, 2nd June 2018 04:58
    • Replies: 0
    • Views: 92
    2nd June 2018, 04:58 Go to last post
  17. Force deposit through testbench

    Started by rmk423, 25th April 2018 06:50
    • Replies: 4
    • Views: 487
    31st May 2018, 16:27 Go to last post
    • Replies: 7
    • Views: 375
    30th May 2018, 13:29 Go to last post
    • Replies: 7
    • Views: 347
    29th May 2018, 18:28 Go to last post