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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,253
    klug
    25th March 2007, 08:41 Go to last post

  1. UPF: What is isolation sense in isolation strategy?

    Started by swabhi812, Yesterday 01:01
    • Replies: 1
    • Views: 114
    jbeniston
    Today, 10:13 Go to last post

  2. Digital VLSI verification engineer - required knowledge

    Started by NikosTS, 2nd May 2018 17:36
    • Replies: 7
    • Views: 324
    swabhi812
    18th May 2018, 19:38 Go to last post

  3. Capacitance of the ESD protection devices, the bond pad, the bond wire

    Started by littlerock, 17th May 2018 11:03
    5 Attachment(s)
    • Replies: 7
    • Views: 229
    ThisIsNotSam
    18th May 2018, 14:32 Go to last post

  4. Selecting CTS topology in ICC

    Started by Vamsi Srikanth S, 17th May 2018 12:57
    • Replies: 2
    • Views: 123
    Vamsi Srikanth S
    17th May 2018, 19:04 Go to last post

  5. multiple registers inside if-else of an always block

    Started by sky_above, 16th May 2018 13:44
    • Replies: 8
    • Views: 242
    ads-ee
    17th May 2018, 16:12 Go to last post

  6. Questions on DFT autofix

    Started by childs72, 17th May 2018 02:54
    • Replies: 1
    • Views: 88
    Tieny
    17th May 2018, 07:06 Go to last post

  7. DC-topo and ICC environment comparison

    Started by ua6bqg, 7th May 2018 17:19
    • Replies: 4
    • Views: 183
    slutarius
    17th May 2018, 05:40 Go to last post

  8. PTPX Switching power calculation

    Started by Mohammed Abrar, 16th May 2018 01:06
    • Replies: 1
    • Views: 98
    slutarius
    17th May 2018, 05:34 Go to last post

  9. RTL for linear search

    Started by sky_above, 14th May 2018 13:59
    • Replies: 19
    • Views: 488
    ThisIsNotSam
    16th May 2018, 15:11 Go to last post

  10. Why higherk frequency circuit may encounter hold time violation for low frequency?

    Started by Anklon, 13th May 2018 11:08
    • Replies: 7
    • Views: 720
    ThisIsNotSam
    16th May 2018, 15:10 Go to last post

  11. 4 bit multiplier from 2 bit multiplier

    Started by sky_above, 14th May 2018 13:56
    • Replies: 3
    • Views: 96
    FvM
    14th May 2018, 15:24 Go to last post

  12. Synopsys tools to find controllability and observability

    Started by Ziki, 10th May 2018 19:34
    • Replies: 1
    • Views: 215
    dpaul
    11th May 2018, 13:40 Go to last post

  13. Cadence encounter - Custom level shifters and power domains APR

    Started by NikosTS, 9th May 2018 14:55
    • Replies: 3
    • Views: 257
    NikosTS
    10th May 2018, 14:34 Go to last post

  14. Merging pin-tagged nets in Cadence

    Started by sci-fi_guy, 4th May 2018 11:42
    • Replies: 1
    • Views: 118
    jjx
    9th May 2018, 13:05 Go to last post

  15. Hspice Warning : device geometries will not be checked

    Started by V.Singh, 8th May 2018 08:36
    • Replies: 1
    • Views: 154
    ThisIsNotSam
    8th May 2018, 15:55 Go to last post

  16. Cadence Encounter place and route - Pins not covered by metal layer

    Started by NikosTS, 7th May 2018 10:01
    • Replies: 9
    • Views: 311
    ThisIsNotSam
    8th May 2018, 15:53 Go to last post

  17. How can you use Mentor Calibre to flatten a hierarchical DRC database?

    Started by majd229, 3rd May 2018 22:29
    • Replies: 4
    • Views: 308
    majd229
    8th May 2018, 14:33 Go to last post

  18. [SOLVED] How to define sdc file description for internally generated clock ?

    Started by Anklon, 6th May 2018 08:24
    1 Attachment(s)
    • Replies: 6
    • Views: 246
    Anklon
    7th May 2018, 20:24 Go to last post

  19. [SOLVED] Virtual Interface resolution cannot find a matching instance for virtual ......

    Started by yashnasa80, 5th May 2018 03:31
    • Replies: 0
    • Views: 158
    yashnasa80
    5th May 2018, 03:31 Go to last post

  20. Prime time tool of Synopsys

    Started by harshahari, 12th April 2018 09:38
    • Replies: 4
    • Views: 537
    Tieny
    4th May 2018, 03:08 Go to last post

  21. [SOLVED] Genus: How to instruct to synthesize multiple module into a single module ?

    Started by Anklon, 3rd May 2018 11:47
    • Replies: 1
    • Views: 126
    ThisIsNotSam
    3rd May 2018, 16:01 Go to last post

  22. SDF back annotation after synthesis fails: No timing checks annotated

    Started by razer6, 7th February 2018 16:50
    • Replies: 1
    • Views: 593
    Tieny
    3rd May 2018, 11:32 Go to last post

  23. How to stitch multi bit flip-flop into wrapper chains in tessent -shell

    Started by WarrenWang, 26th April 2018 07:17
    • Replies: 1
    • Views: 180
    Tieny
    3rd May 2018, 11:25 Go to last post

  24. Force in Synopsys DVE

    Started by rmk423, 25th April 2018 06:50
    • Replies: 1
    • Views: 253
    Tieny
    3rd May 2018, 10:15 Go to last post

  25. parallel chain and scan simulation

    Started by palanis29, 3rd January 2018 10:48
    • Replies: 9
    • Views: 1,720
    Tieny
    3rd May 2018, 10:08 Go to last post

  26. UVM predictor error: Pending reg items

    Started by jiminization, 3rd May 2018 03:10
    • Replies: 0
    • Views: 112
    jiminization
    3rd May 2018, 03:10 Go to last post

  27. Async reset to clk gate

    Started by stanford, 30th April 2018 22:27
    • Replies: 1
    • Views: 246
    jt_eaton
    2nd May 2018, 18:23 Go to last post

  28. Difference between -ntcnotchks and -notimingchecks

    Started by AaronYang, 2nd May 2018 04:59
    • Replies: 0
    • Views: 94
    AaronYang
    2nd May 2018, 04:59 Go to last post

  29. Innovus CTS for a range of clock

    Started by Anklon, 16th April 2018 06:34
    • Replies: 3
    • Views: 392
    Anklon
    30th April 2018, 15:48 Go to last post

  30. 4-phases dual-rail logic : always valid data

    Started by knoxknox, 30th April 2018 08:35
    • Replies: 0
    • Views: 143
    knoxknox
    30th April 2018, 08:35 Go to last post
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