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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,828
    25th March 2007, 08:41 Go to last post
  1. Extracting MOSRA LEVEL 3 Parameters and values

    Started by tanish, 20th September 2019 21:37
    • Replies: 0
    • Views: 162
    20th September 2019, 21:37 Go to last post
  2. scan chain inside memory

    Started by fragnen, 13th September 2019 09:19
    • Replies: 10
    • Views: 365
    20th September 2019, 08:33 Go to last post
  3. Gate Level Simulation

    Started by fragnen, 16th September 2019 10:13
    • Replies: 11
    • Views: 487
    19th September 2019, 15:02 Go to last post
    • Replies: 0
    • Views: 146
    19th September 2019, 02:02 Go to last post
    • Replies: 0
    • Views: 109
    18th September 2019, 14:15 Go to last post
  4. Lockup Latch for DFT purpose

    Started by Varun124, 3rd July 2019 19:34
    • Replies: 8
    • Views: 497
    18th September 2019, 11:46 Go to last post
    • Replies: 5
    • Views: 339
    17th September 2019, 18:33 Go to last post
  5. vcd file generation for netlist

    Started by maru2488, 4th September 2019 07:19
    • Replies: 2
    • Views: 214
    17th September 2019, 12:45 Go to last post
    • Replies: 1
    • Views: 317
    17th September 2019, 11:27 Go to last post
  6. I2C not working properly

    Started by rmachado, 2nd September 2019 14:39
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,037
    14th September 2019, 20:36 Go to last post
  7. Overwrite cell delay.

    Started by Yussef, 11th September 2019 13:46
    • Replies: 4
    • Views: 284
    12th September 2019, 14:04 Go to last post
  8. SAIF file generation in VCS tool

    Started by maru2488, 6th September 2019 10:23
    • Replies: 0
    • Views: 212
    6th September 2019, 10:23 Go to last post
    • Replies: 1
    • Views: 249
    6th September 2019, 06:55 Go to last post
  9. Inducing delays in WGL files

    Started by tahirsengine, 5th September 2019 14:17
    • Replies: 0
    • Views: 190
    5th September 2019, 14:17 Go to last post
  10. Warnings in nano route in innovus

    Started by Chinmaye, 5th September 2019 11:18
    • Replies: 1
    • Views: 173
    5th September 2019, 12:06 Go to last post
  11. DFT- Circuit Netlist

    Started by avinashkumar, 1st September 2019 15:57
    • Replies: 2
    • Views: 369
    5th September 2019, 03:53 Go to last post
  12. Using multilayer AHB-Lite

    Started by Haraldovs, 3rd September 2019 11:27
    • Replies: 3
    • Views: 293
    4th September 2019, 08:23 Go to last post
    • Replies: 3
    • Views: 443
    4th September 2019, 07:26 Go to last post
  13. Different ways of reading design in ICC

    Started by Dan_Yang, 2nd September 2019 16:14
    • Replies: 2
    • Views: 222
    3rd September 2019, 14:45 Go to last post
  14. Time Constraints in Placement

    Started by Dan_Yang, 2nd September 2019 16:19
    • Replies: 2
    • Views: 289
    3rd September 2019, 12:07 Go to last post
  15. SRAM1RW512x32 module for PULPino microprocessor

    Started by Abdo_Mgdy, 1st September 2019 10:05
    • Replies: 0
    • Views: 144
    1st September 2019, 10:05 Go to last post
  16. Difference between mebes & Job Deck

    Started by RohithRaj, 31st August 2019 17:02
    • Replies: 0
    • Views: 164
    31st August 2019, 17:02 Go to last post
    • Replies: 3
    • Views: 315
    31st August 2019, 08:19 Go to last post
  17. [SOLVED] [moved] Routing signal like clock tree in Cadence Encounter

    Started by Abdo_Mgdy, 27th August 2019 13:40
    • Replies: 3
    • Views: 313
    31st August 2019, 08:18 Go to last post
  18. power analysis using synopsys DC compiler

    Started by avishek_sinha_roy, 28th August 2019 19:03
    • Replies: 5
    • Views: 408
    30th August 2019, 11:54 Go to last post
  19. Beginning and end of a time step

    Started by stanford, 22nd August 2019 02:59
    • Replies: 11
    • Views: 802
    29th August 2019, 07:29 Go to last post
  20. Verifying Large ASIC

    Started by khtsoi, 26th August 2019 14:55
    • Replies: 6
    • Views: 621
    28th August 2019, 07:58 Go to last post