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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,399
    klug
    25th March 2007, 08:41 Go to last post

  1. Static timing analysis

    Started by gaurp, 17th March 2019 20:38
    • Replies: 4
    • Views: 320
    swabhi812
    Yesterday, 19:29 Go to last post

  2. Shadow path causing parallel simulation to fail. Serial is passing.

    Started by finsiherfish, Yesterday 16:36
    • Replies: 0
    • Views: 62
    finsiherfish
    Yesterday, 16:36 Go to last post

  3. Asap7 for free academic PDK and library access

    Started by saurabhr8here, 20th March 2019 15:07
    • Replies: 0
    • Views: 168
    saurabhr8here
    20th March 2019, 15:07 Go to last post

  4. Clock cells adding jitter to clock

    Started by stanford, 18th March 2019 09:31
    • Replies: 6
    • Views: 209
    ThisIsNotSam
    18th March 2019, 19:03 Go to last post

  5. minimum depth for data streaming through async fifo

    Started by stanford, 14th March 2019 19:46
    2 Pages •
    1 2
    • Replies: 24
    • Views: 506
    KlausST
    18th March 2019, 16:40 Go to last post

  6. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 4
    • Views: 650
    englishdogg
    18th March 2019, 08:22 Go to last post

  7. Question related to high latency

    Started by kirankumark0489, 19th February 2019 23:34
    • Replies: 4
    • Views: 351
    Vlsi29
    17th March 2019, 22:46 Go to last post

  8. didn't find inverter for specified operating conditions

    Started by vyella1, 15th March 2019 21:03
    • Replies: 1
    • Views: 169
    stanford
    16th March 2019, 04:59 Go to last post

  9. Export Spectre XPS-MS simulation into VCD

    Started by LostEagle, 15th March 2019 00:22
    • Replies: 0
    • Views: 91
    LostEagle
    15th March 2019, 00:22 Go to last post

  10. Clock domain crossing problem

    Started by biju4u90, 11th March 2019 19:39
    • Replies: 9
    • Views: 578
    swabhi812
    14th March 2019, 19:45 Go to last post

  11. Mentor DFT tool- supra ATPG- EDT patterns

    Started by finsiherfish, 12th March 2019 21:29
    • Replies: 0
    • Views: 134
    finsiherfish
    12th March 2019, 21:29 Go to last post

  12. Async FIFO full generation when read and write frequencies are different

    Started by biju4u90, 12th March 2019 14:43
    • Replies: 3
    • Views: 218
    KlausST
    12th March 2019, 15:17 Go to last post

  13. Looking for Hint: How to output failing vectors in Synopsys Formality?

    Started by kingishm, 10th March 2019 23:40
    2 Attachment(s)
    • Replies: 0
    • Views: 156
    kingishm
    10th March 2019, 23:40 Go to last post

  14. reliable low latency low complexity viterbi decoder

    Started by jisna, 8th March 2019 07:03
    • Replies: 1
    • Views: 269
    KlausST
    8th March 2019, 08:11 Go to last post

  15. Why are the most critical signals in Digital Circuitry are Active low ?

    Started by kaushikrvs, 28th February 2019 21:09
    • Replies: 15
    • Views: 768
    andre_teprom
    7th March 2019, 12:52 Go to last post

  16. Reverse case statement with multiple matches

    Started by stanford, 6th March 2019 00:52
    • Replies: 4
    • Views: 361
    ThisIsNotSam
    7th March 2019, 03:30 Go to last post

  17. latches in timing (do latches get timed as destination or as combo logic)

    Started by stanford, 27th February 2019 20:27
    • Replies: 2
    • Views: 281
    swabhi812
    6th March 2019, 20:38 Go to last post

  18. AI Accelerators hardware for AI applications

    Started by stanford, 3rd March 2019 07:43
    • Replies: 4
    • Views: 487
    ThisIsNotSam
    4th March 2019, 14:25 Go to last post

  19. Export cadence schematic top view into hierarchy pdf

    Started by LostEagle, 27th February 2019 20:48
    2 Attachment(s)
    • Replies: 0
    • Views: 110
    LostEagle
    27th February 2019, 20:48 Go to last post

  20. Error in Cadence RTL Compiler when estimating Power using VCD

    Started by saunaksaha, 26th February 2019 22:52
    • Replies: 1
    • Views: 216
    ThisIsNotSam
    27th February 2019, 15:29 Go to last post

  21. How to debug pattern mismatch during simulation of SOC level patterns- DFT

    Started by finsiherfish, 26th February 2019 21:15
    • Replies: 0
    • Views: 124
    finsiherfish
    26th February 2019, 21:15 Go to last post

  22. [moved] What is the tool used to create .spf file through synopsys?

    Started by Sph, 26th February 2019 07:08
    • Replies: 2
    • Views: 238
    FvM
    26th February 2019, 13:13 Go to last post

  23. Using libraries in Leonardo Spectrum.

    Started by NehaJain1234, 26th February 2019 09:52
    • Replies: 0
    • Views: 138
    NehaJain1234
    26th February 2019, 09:52 Go to last post

  24. Up counter or down counter

    Started by stanford, 24th February 2019 11:20
    • Replies: 3
    • Views: 394
    dpaul
    25th February 2019, 11:12 Go to last post

  25. Logical and physical 0.13 or 0.18 um technology library

    Started by Abdo18, 20th February 2019 20:45
    • Replies: 1
    • Views: 234
    ThisIsNotSam
    22nd February 2019, 22:10 Go to last post

  26. how does insertion delay affect timing

    Started by stanford, 22nd February 2019 20:02
    • Replies: 1
    • Views: 160
    ThisIsNotSam
    22nd February 2019, 22:07 Go to last post

  27. Liberate - Custom Cell Characterization

    Started by manpmanp, 22nd February 2019 17:10
    • Replies: 1
    • Views: 148
    ThisIsNotSam
    22nd February 2019, 19:53 Go to last post

  28. [moved] Area and Gate Equivalent in Leonardo Spectrum Report

    Started by NehaJain1234, 20th February 2019 16:21
    3 Attachment(s)
    • Replies: 5
    • Views: 344
    ThisIsNotSam
    22nd February 2019, 16:08 Go to last post

  29. rtl code to find the smallest

    Started by stanford, 20th February 2019 08:47
    • Replies: 10
    • Views: 550
    ThisIsNotSam
    21st February 2019, 23:34 Go to last post

  30. LBIST architecture - Industry standards

    Started by Nanda_DFT, 20th February 2019 06:09
    • Replies: 1
    • Views: 181
    ArakelTheDragon
    21st February 2019, 11:54 Go to last post
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