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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,622
    25th March 2007, 08:41 Go to last post
  1. [Synopsys VCS] Recommended Materials

    Started by ivlsi, 16th October 2018 17:26
    • Replies: 0
    • Views: 69
    16th October 2018, 17:26 Go to last post
    • Replies: 1
    • Views: 78
    16th October 2018, 13:25 Go to last post
  2. [SOLVED] Hold time violations in post layout simulation (Although STA is fine)

    Started by ranaya, 12th October 2018 10:00
    • Replies: 5
    • Views: 194
    16th October 2018, 12:35 Go to last post
    • Replies: 1
    • Views: 89
    16th October 2018, 08:28 Go to last post
  3. Multi-vth design not performed

    Started by onta00, 15th October 2018 14:28
    • Replies: 4
    • Views: 150
    16th October 2018, 07:10 Go to last post
    • Replies: 3
    • Views: 143
    15th October 2018, 19:19 Go to last post
  4. CMOS inverter output ?

    Started by IngleA, 1st October 2018 18:49
    • Replies: 8
    • Views: 359
    15th October 2018, 18:24 Go to last post
  5. [LEC] Why needed in ASIC flow?

    Started by ivlsi, 23rd August 2018 19:16
    • Replies: 12
    • Views: 886
    15th October 2018, 12:52 Go to last post
  6. Critical Path in a design

    Started by onta00, 11th October 2018 12:06
    • Replies: 4
    • Views: 213
    15th October 2018, 08:07 Go to last post
  7. SYNOPSIS - Clock creation and delivery to submodules

    Started by kls213, 11th October 2018 17:08
    • Replies: 3
    • Views: 218
    15th October 2018, 08:05 Go to last post
  8. [SOLVED] Fatal error while running top module || UVM

    Started by ranayehya, 13th October 2018 18:33
    • Replies: 4
    • Views: 160
    14th October 2018, 19:36 Go to last post
  9. Max capacitance violation on macro clk pin

    Started by shragh, 14th October 2018 08:00
    • Replies: 2
    • Views: 104
    14th October 2018, 19:10 Go to last post
  10. What is going on with my D flip-flop in Hspice?

    Started by Amamiya_Ren, 12th October 2018 14:35
    • Replies: 3
    • Views: 138
    12th October 2018, 14:55 Go to last post
  11. One clock cycle delay for the input data

    Started by riz1679, 12th October 2018 09:54
    • Replies: 1
    • Views: 83
    12th October 2018, 10:04 Go to last post
    • Replies: 3
    • Views: 176
    11th October 2018, 15:11 Go to last post
    • Replies: 0
    • Views: 65
    11th October 2018, 11:41 Go to last post
  12. Closed: Input reference library in synopsys ic compiler tool

    Started by harshahari, 20th April 2018 12:12
    • Replies: 1
    • Views: 375
    11th October 2018, 11:31 Go to last post
    • Replies: 0
    • Views: 45
    11th October 2018, 11:09 Go to last post
  13. Memory BIST insertion Synopsys flow

    Started by shmd19, 10th October 2018 17:05
    • Replies: 0
    • Views: 85
    10th October 2018, 17:05 Go to last post
  14. Cadence ATPG TCL script

    Started by Nitin1245, 5th October 2018 09:39
    • Replies: 4
    • Views: 238
    8th October 2018, 13:30 Go to last post
    • Replies: 1
    • Views: 76
    8th October 2018, 13:28 Go to last post
    • Replies: 1
    • Views: 201
    6th October 2018, 19:01 Go to last post
  15. [SOLVED] QuestaSim / ModelSim fatal error during simulation

    Started by riz1679, 5th October 2018 10:44
    • Replies: 3
    • Views: 130
    5th October 2018, 15:01 Go to last post
    • Replies: 5
    • Views: 423
    4th October 2018, 08:36 Go to last post
  16. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 4
    • Views: 314
    4th October 2018, 08:34 Go to last post
  17. Power Gating Cells in SAED32/29 EDK

    Started by mumichang, 4th October 2018 06:37
    • Replies: 0
    • Views: 84
    4th October 2018, 06:37 Go to last post
  18. Power Measurement Error with Design Compiler?

    Started by mumichang, 4th October 2018 03:37
    • Replies: 0
    • Views: 95
    4th October 2018, 03:37 Go to last post
  19. NC verilog schematic to verilog

    Started by jiminization, 27th September 2018 09:02
    • Replies: 1
    • Views: 169
    28th September 2018, 15:13 Go to last post