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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,287
    klug
    25th March 2007, 08:41 Go to last post

  1. Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    Started by daskk62, Yesterday 19:13
    • Replies: 5
    • Views: 168
    dpaul
    Today, 10:18 Go to last post

  2. [moved] How to detect the faulty flop in scan chain

    Started by Sunilverma03, Yesterday 05:33
    • Replies: 0
    • Views: 135
    Sunilverma03
    Yesterday, 05:33 Go to last post

  3. SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

    Started by Puppet123, 20th November 2019 21:35
    • Replies: 2
    • Views: 162
    Puppet123
    Yesterday, 03:36 Go to last post

  4. Tool inserted DFT lockup latch is not transparent in functional mode (no test port)

    Started by Ashish Agrawal, 14th November 2019 18:32
    • Replies: 2
    • Views: 221
    Sunilverma03
    20th November 2019, 13:08 Go to last post

  5. Using a BFM in system verification code.

    Started by dipk11, 15th November 2019 07:49
    • Replies: 6
    • Views: 348
    dipk11
    19th November 2019, 09:27 Go to last post

  6. SystemVerilog Interface signal assignment

    Started by ghertz, 18th November 2019 17:30
    • Replies: 2
    • Views: 183
    ghertz
    18th November 2019, 23:46 Go to last post

  7. asynchronous D Flip flop with negative edge triggered clk,set and reset

    Started by Knowledge.seeker, 18th November 2019 11:11
    • Replies: 2
    • Views: 184
    dick_freebird
    18th November 2019, 23:09 Go to last post

  8. DFT Visualizer Data View

    Started by Vignesh_J, 15th November 2019 13:24
    • Replies: 2
    • Views: 258
    Vignesh_J
    18th November 2019, 08:03 Go to last post

  9. How to find the operating frequency for an ASIC?

    Started by daskk62, 17th November 2019 19:18
    • Replies: 2
    • Views: 152
    Tieny
    17th November 2019, 22:51 Go to last post

  10. How to generate sine wave using Verilog?

    Started by h_upadhyay, 9th November 2019 06:59
    • Replies: 9
    • Views: 617
    wwfeldman
    16th November 2019, 15:03 Go to last post

  11. max_transition Violation

    Started by vyella1, 13th November 2019 22:17
    • Replies: 1
    • Views: 185
    ThisIsNotSam
    14th November 2019, 13:29 Go to last post

  12. Synopsys DC: Tracing clock path

    Started by vaibhava, 13th November 2019 08:36
    • Replies: 1
    • Views: 107
    ThisIsNotSam
    14th November 2019, 13:27 Go to last post

  13. What are the meaings of the following Calibre warnings

    Started by aditya1579, 13th November 2019 03:44
    • Replies: 2
    • Views: 189
    ThisIsNotSam
    14th November 2019, 13:25 Go to last post

  14. DFT parallel pattern simulation mismatch analysis

    Started by Vignesh_J, 13th November 2019 13:33
    • Replies: 1
    • Views: 136
    Tieny
    14th November 2019, 04:34 Go to last post

  15. For DFT perspective ,what happens when there are no capture clock

    Started by Varun124, 28th September 2019 08:31
    • Replies: 4
    • Views: 476
    Tieny
    13th November 2019, 09:46 Go to last post

  16. [moved] Value of lateral electric field(E0) in UMC 65 technology

    Started by abhishek260, 11th November 2019 12:41
    • Replies: 2
    • Views: 374
    timof
    12th November 2019, 02:31 Go to last post

  17. What is meant by Split CODEC IN DFT ?

    Started by Varun124, 12th October 2019 10:18
    • Replies: 1
    • Views: 323
    Tieny
    11th November 2019, 10:15 Go to last post

  18. LBIST low test coverage

    Started by vijay82, 23rd October 2019 08:21
    • Replies: 5
    • Views: 485
    Tieny
    11th November 2019, 10:07 Go to last post

  19. MBIST DONE & GO failing conditions

    Started by vipul982, 6th November 2019 14:13
    • Replies: 1
    • Views: 280
    Tieny
    11th November 2019, 10:03 Go to last post

  20. [SOLVED] [moved] What is Cadence genus synthesis, report power?

    Started by daskk62, 8th November 2019 18:50
    • Replies: 1
    • Views: 282
    ThisIsNotSam
    9th November 2019, 09:02 Go to last post

  21. External C++ compilation and DPI question

    Started by ghertz, 1st November 2019 23:39
    • Replies: 14
    • Views: 638
    ghertz
    6th November 2019, 00:20 Go to last post

  22. In PrimeTime, is there a similar command for setting output load cell to all outputs?

    Started by majd229, 5th November 2019 18:27
    • Replies: 0
    • Views: 206
    majd229
    5th November 2019, 18:27 Go to last post

  23. What is Negative timing checks

    Started by Varun124, 5th November 2019 11:32
    • Replies: 1
    • Views: 146
    ThisIsNotSam
    5th November 2019, 12:49 Go to last post

  24. SiliconSmart pin and lib file

    Started by xabosexi, 4th November 2019 08:04
    • Replies: 1
    • Views: 143
    ThisIsNotSam
    4th November 2019, 12:22 Go to last post

  25. Mipi D-phy physical layer implementation

    Started by MaheshC, 4th November 2019 10:33
    • Replies: 0
    • Views: 122
    MaheshC
    4th November 2019, 10:33 Go to last post

  26. How does aging is conducted exactly in Cadence?

    Started by antlhem, 31st October 2019 11:42
    3 Attachment(s)
    • Replies: 3
    • Views: 435
    antlhem
    2nd November 2019, 14:25 Go to last post

  27. How to measure the C parasitic (internal capacitance) of an inverter using Spectre ?

    Started by Puppet123, 26th October 2019 14:35
    2 Attachment(s)
    • Replies: 17
    • Views: 1,330
    timof
    31st October 2019, 17:22 Go to last post

  28. Moved: CMOS ring oscillator frequency degradation through years

    Started by antlhem, 2nd November 2019 15:00
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  29. Voltage drop of on die power gating cells

    Started by volsky, 29th October 2019 07:34
    • Replies: 4
    • Views: 330
    ThisIsNotSam
    30th October 2019, 12:19 Go to last post

  30. [SOLVED] Preventing using a certain cell in cadence encounter

    Started by Abdo_Mgdy, 29th October 2019 12:39
    • Replies: 2
    • Views: 219
    Abdo_Mgdy
    29th October 2019, 14:22 Go to last post
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