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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,262
    klug
    25th March 2007, 08:41 Go to last post

  1. Difference in Delays of the same cells in best run and worst run

    Started by Stichi_1985, Today 06:44
    • Replies: 1
    • Views: 12
    KlausST
    Today, 10:01 Go to last post

  2. Async set deassertion

    Started by stanford, Today 07:03
    • Replies: 0
    • Views: 30
    stanford
    Today, 07:03 Go to last post

  3. How to figure out whether it is setup or hold issue on real silicon

    Started by stanford, Yesterday 00:58
    • Replies: 2
    • Views: 126
    jbeniston
    Yesterday, 20:46 Go to last post

  4. D flip flop RTL without Qbar

    Started by sky_above, Yesterday 14:37
    • Replies: 7
    • Views: 91
    FvM
    Yesterday, 19:15 Go to last post

  5. [SOLVED] Synthesize an RTL from two technology .db files (of same node)

    Started by ranaya, 22nd May 2018 20:17
    • Replies: 6
    • Views: 126
    rca
    Yesterday, 15:09 Go to last post

  6. Clock gating and cdc on clock_req

    Started by stanford, 22nd May 2018 23:15
    • Replies: 3
    • Views: 162
    FvM
    Yesterday, 10:49 Go to last post

  7. Cell Characterization Determining Slew vs Capacitive Values for Templates

    Started by ranaya, 23rd May 2018 19:20
    • Replies: 1
    • Views: 75
    ThisIsNotSam
    23rd May 2018, 22:04 Go to last post

  8. UPF: What is isolation sense in isolation strategy?

    Started by swabhi812, 20th May 2018 01:01
    • Replies: 3
    • Views: 218
    stanford
    22nd May 2018, 06:47 Go to last post

  9. Timing through the d pin

    Started by stanford, 22nd May 2018 06:23
    • Replies: 0
    • Views: 53
    stanford
    22nd May 2018, 06:23 Go to last post

  10. DC-topo and ICC environment comparison

    Started by ua6bqg, 7th May 2018 17:19
    • Replies: 6
    • Views: 242
    slutarius
    22nd May 2018, 01:38 Go to last post

  11. multiple registers inside if-else of an always block

    Started by sky_above, 16th May 2018 13:44
    2 Attachment(s)
    • Replies: 15
    • Views: 323
    ads-ee
    21st May 2018, 17:15 Go to last post

  12. Digital VLSI verification engineer - required knowledge

    Started by NikosTS, 2nd May 2018 17:36
    • Replies: 7
    • Views: 340
    swabhi812
    18th May 2018, 19:38 Go to last post

  13. Capacitance of the ESD protection devices, the bond pad, the bond wire

    Started by littlerock, 17th May 2018 11:03
    5 Attachment(s)
    • Replies: 7
    • Views: 253
    ThisIsNotSam
    18th May 2018, 14:32 Go to last post

  14. Selecting CTS topology in ICC

    Started by Vamsi Srikanth S, 17th May 2018 12:57
    • Replies: 2
    • Views: 131
    Vamsi Srikanth S
    17th May 2018, 19:04 Go to last post

  15. Questions on DFT autofix

    Started by childs72, 17th May 2018 02:54
    • Replies: 1
    • Views: 94
    Tieny
    17th May 2018, 07:06 Go to last post

  16. PTPX Switching power calculation

    Started by Mohammed Abrar, 16th May 2018 01:06
    • Replies: 1
    • Views: 119
    slutarius
    17th May 2018, 05:34 Go to last post

  17. RTL for linear search

    Started by sky_above, 14th May 2018 13:59
    • Replies: 19
    • Views: 508
    ThisIsNotSam
    16th May 2018, 15:11 Go to last post

  18. Why higherk frequency circuit may encounter hold time violation for low frequency?

    Started by Anklon, 13th May 2018 11:08
    • Replies: 7
    • Views: 737
    ThisIsNotSam
    16th May 2018, 15:10 Go to last post

  19. 4 bit multiplier from 2 bit multiplier

    Started by sky_above, 14th May 2018 13:56
    • Replies: 3
    • Views: 103
    FvM
    14th May 2018, 15:24 Go to last post

  20. Synopsys tools to find controllability and observability

    Started by Ziki, 10th May 2018 19:34
    • Replies: 1
    • Views: 224
    dpaul
    11th May 2018, 13:40 Go to last post

  21. Cadence encounter - Custom level shifters and power domains APR

    Started by NikosTS, 9th May 2018 14:55
    • Replies: 3
    • Views: 269
    NikosTS
    10th May 2018, 14:34 Go to last post

  22. Merging pin-tagged nets in Cadence

    Started by sci-fi_guy, 4th May 2018 11:42
    • Replies: 1
    • Views: 125
    jjx
    9th May 2018, 13:05 Go to last post

  23. Hspice Warning : device geometries will not be checked

    Started by V.Singh, 8th May 2018 08:36
    • Replies: 1
    • Views: 169
    ThisIsNotSam
    8th May 2018, 15:55 Go to last post

  24. Cadence Encounter place and route - Pins not covered by metal layer

    Started by NikosTS, 7th May 2018 10:01
    • Replies: 9
    • Views: 328
    ThisIsNotSam
    8th May 2018, 15:53 Go to last post

  25. How can you use Mentor Calibre to flatten a hierarchical DRC database?

    Started by majd229, 3rd May 2018 22:29
    • Replies: 4
    • Views: 327
    majd229
    8th May 2018, 14:33 Go to last post

  26. [SOLVED] How to define sdc file description for internally generated clock ?

    Started by Anklon, 6th May 2018 08:24
    1 Attachment(s)
    • Replies: 6
    • Views: 258
    Anklon
    7th May 2018, 20:24 Go to last post

  27. [SOLVED] Virtual Interface resolution cannot find a matching instance for virtual ......

    Started by yashnasa80, 5th May 2018 03:31
    • Replies: 0
    • Views: 161
    yashnasa80
    5th May 2018, 03:31 Go to last post

  28. Prime time tool of Synopsys

    Started by harshahari, 12th April 2018 09:38
    • Replies: 4
    • Views: 552
    Tieny
    4th May 2018, 03:08 Go to last post

  29. [SOLVED] Genus: How to instruct to synthesize multiple module into a single module ?

    Started by Anklon, 3rd May 2018 11:47
    • Replies: 1
    • Views: 131
    ThisIsNotSam
    3rd May 2018, 16:01 Go to last post

  30. SDF back annotation after synthesis fails: No timing checks annotated

    Started by razer6, 7th February 2018 16:50
    • Replies: 1
    • Views: 611
    Tieny
    3rd May 2018, 11:32 Go to last post
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