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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,997
    klug
    25th March 2007, 08:41 Go to last post

  1. How to generate the vcd file in modelsim for power estimation using PrimeTime Px

    Started by javierh.santiago, Yesterday 07:20
    • Replies: 2
    • Views: 151
    javierh.santiago
    Yesterday, 22:11 Go to last post

  2. Using a CDL file in LTSpice

    Started by youngguns21, 16th January 2019 17:13
    • Replies: 3
    • Views: 206
    Akanimo
    16th January 2019, 21:51 Go to last post

  3. Clock gate set up and hold checks

    Started by mailsrikanth007, 15th January 2019 07:18
    • Replies: 1
    • Views: 146
    ThisIsNotSam
    15th January 2019, 15:56 Go to last post

  4. FIFO implementation using RAM

    Started by biju4u90, 8th January 2019 19:16
    • Replies: 3
    • Views: 572
    Alexxk
    9th January 2019, 11:47 Go to last post

  5. TSMC 65nm GP operating voltage

    Started by oAwad, 6th January 2019 21:10
    • Replies: 1
    • Views: 204
    ThisIsNotSam
    7th January 2019, 14:25 Go to last post

  6. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 8
    • Views: 1,059
    Tieny
    6th January 2019, 22:34 Go to last post

  7. fifo with ram or flops

    Started by stanford, 13th December 2018 01:40
    1 Attachment(s)
    • Replies: 7
    • Views: 506
    Tieny
    6th January 2019, 22:31 Go to last post

  8. DFT interview questions

    Started by Nitin1245, 29th November 2018 05:36
    • Replies: 3
    • Views: 736
    Tieny
    6th January 2019, 22:04 Go to last post

  9. How do you reduce Atpg Abort faults?

    Started by g_eashwar, 23rd November 2018 14:53
    • Replies: 1
    • Views: 345
    Tieny
    6th January 2019, 21:54 Go to last post

  10. High-Level Synthesis (HLS) vs RTL for ASIC flow

    Started by oAwad, 31st December 2018 22:51
    • Replies: 2
    • Views: 464
    weetabixharry
    5th January 2019, 17:53 Go to last post

  11. ModelSim - How to force a struct type written in SystemVerilog?

    Started by oho, 30th December 2018 18:21
    • Replies: 0
    • Views: 154
    oho
    30th December 2018, 18:21 Go to last post

  12. Difference between NETLIST and GOLDEN NETLIST?

    Started by Alishetty, 23rd November 2018 07:25
    • Replies: 6
    • Views: 724
    arvinraj
    27th December 2018, 09:06 Go to last post

  13. Timing during Synthesis: Max clock frequency

    Started by Alexxk, 13th December 2018 14:34
    • Replies: 3
    • Views: 793
    dick_freebird
    14th December 2018, 18:44 Go to last post

  14. Why NMOS body is connected to ground not to source in n-well process

    Started by ICdesignerbeginner, 12th December 2018 10:07
    1 Attachment(s)
    • Replies: 1
    • Views: 232
    rmanalo
    12th December 2018, 11:05 Go to last post

  15. Sanity check of NETLIST

    Started by Alishetty, 8th December 2018 17:26
    • Replies: 3
    • Views: 463
    ThisIsNotSam
    9th December 2018, 17:53 Go to last post

  16. Where can I find an IFC Verilog implementation?

    Started by oho, 21st November 2018 12:00
    • Replies: 1
    • Views: 315
    ads-ee
    21st November 2018, 17:13 Go to last post

  17. Repeated setting default values in case statement in Verilog?

    Started by stanford, 21st November 2018 01:03
    • Replies: 1
    • Views: 283
    dave_59
    21st November 2018, 05:54 Go to last post

  18. Pico second precision up counter

    Started by npsnpsnps, 14th November 2018 12:21
    • Replies: 9
    • Views: 927
    BradtheRad
    20th November 2018, 05:47 Go to last post

  19. I have a Micro Code design assignment, how to proceed?

    Started by kaushikrvs, 17th November 2018 20:51
    • Replies: 1
    • Views: 430
    ThisIsNotSam
    18th November 2018, 15:51 Go to last post

  20. What are the normal tricks to closing time in rc and encounter?

    Started by liletian, 13th November 2018 18:56
    • Replies: 1
    • Views: 360
    ThisIsNotSam
    15th November 2018, 03:17 Go to last post

  21. How does variable bit shift operation get synthesize in hw?

    Started by stanford, 14th November 2018 04:37
    • Replies: 1
    • Views: 334
    FvM
    14th November 2018, 09:05 Go to last post

  22. Ringing between pads and digital inputs?

    Started by Alexxk, 13th November 2018 08:28
    • Replies: 4
    • Views: 399
    dick_freebird
    13th November 2018, 18:50 Go to last post

  23. What does this mean in standard cell library?

    Started by liletian, 13th November 2018 07:14
    • Replies: 1
    • Views: 273
    oratie
    13th November 2018, 08:32 Go to last post

  24. Prime Time power estimation whith .spef file

    Started by jmaileh.b, 12th November 2018 08:00
    • Replies: 0
    • Views: 290
    jmaileh.b
    12th November 2018, 08:00 Go to last post

  25. How do I synthesize an inout port using DC?

    Started by kos8108, 27th August 2018 14:55
    • Replies: 1
    • Views: 352
    TonyLS
    9th November 2018, 21:41 Go to last post

  26. Logic Path Activation Probability Depending on Input Data Pattern

    Started by ranaya, 9th November 2018 12:12
    • Replies: 1
    • Views: 328
    ThisIsNotSam
    9th November 2018, 15:22 Go to last post

  27. what is the usage of the port in the fpga?

    Started by liletian, 28th August 2018 19:12
    • Replies: 4
    • Views: 540
    dpaul
    9th November 2018, 10:26 Go to last post

  28. CUVMUR error for VHDL code and Verilog testbench

    Started by shreyakishore, 6th November 2018 21:22
    5 Attachment(s)
    • Replies: 3
    • Views: 381
    FvM
    8th November 2018, 08:35 Go to last post

  29. SiliconSmart set_config_opt for individual bus pins

    Started by jiminization, 8th November 2018 07:21
    • Replies: 0
    • Views: 182
    jiminization
    8th November 2018, 07:21 Go to last post

  30. What does this mean in RC?

    Started by liletian, 6th November 2018 01:17
    • Replies: 6
    • Views: 640
    liletian
    7th November 2018, 23:46 Go to last post
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