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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,788
    klug
    25th March 2007, 08:41 Go to last post

  1. ADS1115 issue for taking values of 4th digit after decimal point

    Started by RenesasT, 25th April 2019 09:36
    • Replies: 6
    • Views: 321
    KlausST
    Today, 01:30 Go to last post

  2. TSMC LVS errors after sealring

    Started by AllenD, Yesterday 08:50
    • Replies: 0
    • Views: 89
    AllenD
    Yesterday, 08:50 Go to last post

  3. last step of tapeoout---sealring and dummy fill density

    Started by AllenD, 18th May 2019 15:36
    • Replies: 0
    • Views: 126
    AllenD
    18th May 2019, 15:36 Go to last post

  4. [moved] Saving data from reliability simulation Virtuoso Cadence

    Started by antlhem, 17th May 2019 17:23
    1 Attachment(s)
    • Replies: 0
    • Views: 105
    antlhem
    17th May 2019, 17:23 Go to last post

  5. [SOLVED] Hz vs number of bits

    Started by tahirsengine, 3rd May 2019 11:47
    • Replies: 6
    • Views: 398
    KlausST
    17th May 2019, 06:42 Go to last post

  6. LEC at top level of a SOC

    Started by fragnen, 7th May 2019 14:22
    • Replies: 1
    • Views: 127
    vipul982
    17th May 2019, 06:28 Go to last post

  7. How does Foundry provide different Process Models?

    Started by Wyre, 13th May 2019 09:22
    • Replies: 1
    • Views: 200
    ThisIsNotSam
    13th May 2019, 16:35 Go to last post

  8. recovery time of sync reset vs. async reset

    Started by stanford, 9th May 2019 02:29
    • Replies: 5
    • Views: 1,994
    stanford
    9th May 2019, 18:36 Go to last post

  9. TSMC 65nm Calibre dummy insertion tool

    Started by AllenD, 5th May 2019 11:36
    • Replies: 8
    • Views: 2,788
    AllenD
    9th May 2019, 09:26 Go to last post

  10. synthesizing memory as latches

    Started by vyella1, 8th May 2019 17:19
    • Replies: 1
    • Views: 651
    ThisIsNotSam
    8th May 2019, 18:23 Go to last post

  11. Design to state position of first one from lsb every clock for parallel data coming

    Started by fragnen, 12th April 2019 14:18
    1 Attachment(s)
    • Replies: 11
    • Views: 2,618
    Akanimo
    8th May 2019, 00:17 Go to last post

  12. [Questa] How to colorize the Transcript window (files, directories, etc)?

    Started by ldm.eth, 5th May 2019 16:51
    • Replies: 2
    • Views: 158
    ldm.eth
    5th May 2019, 18:14 Go to last post

  13. How to create *.mpf in the "middle of work"?

    Started by ldm.eth, 5th May 2019 14:59
    • Replies: 0
    • Views: 80
    ldm.eth
    5th May 2019, 14:59 Go to last post

  14. How PA/PTPX handle analog macro

    Started by tarkyss, 5th May 2019 10:11
    • Replies: 0
    • Views: 99
    tarkyss
    5th May 2019, 10:11 Go to last post

  15. How to reduce the ringing that occur in the PI analysis using the package.

    Started by savithad, 4th May 2019 09:29
    • Replies: 0
    • Views: 122
    savithad
    4th May 2019, 09:29 Go to last post

  16. Always @ flop holding value when else is not specified

    Started by stanford, 3rd May 2019 04:55
    • Replies: 2
    • Views: 221
    asdf44
    3rd May 2019, 17:13 Go to last post

  17. How to use the verilog obfuscator?

    Started by nagulapatigirireddy, 2nd May 2019 14:54
    1 Attachment(s)
    • Replies: 3
    • Views: 268
    ads-ee
    3rd May 2019, 16:41 Go to last post

  18. DC Optimize Registers message

    Started by mwb, 1st May 2019 17:22
    • Replies: 0
    • Views: 225
    mwb
    1st May 2019, 17:22 Go to last post

  19. Design Compiler Register Retiming and CDC

    Started by mwb, 24th April 2019 10:48
    • Replies: 2
    • Views: 1,171
    mwb
    1st May 2019, 17:13 Go to last post

  20. How to synchronize two LFSR between PRBS generator and checker

    Started by stanford, 29th April 2019 19:16
    • Replies: 7
    • Views: 3,793
    FvM
    1st May 2019, 10:41 Go to last post

  21. Writing ModelSim do files

    Started by tahirsengine, 18th April 2019 07:54
    • Replies: 3
    • Views: 635
    dave_59
    26th April 2019, 15:02 Go to last post

  22. [moved] Learning DFT as an intern and need help with .dft.v files

    Started by linaxus, 12th April 2019 01:08
    • Replies: 1
    • Views: 243
    vipul982
    25th April 2019, 06:20 Go to last post

  23. 32x32 Single Cycle Fast Multiplier

    Started by Mr.PAP, 18th April 2019 12:56
    • Replies: 10
    • Views: 6,519
    Mr.PAP
    24th April 2019, 06:25 Go to last post

  24. Synth. area reduced when adding a pipeline register

    Started by oAwad, 22nd April 2019 22:02
    • Replies: 4
    • Views: 1,491
    ThisIsNotSam
    23rd April 2019, 14:56 Go to last post

  25. priority on two asynch triggered events

    Started by stanford, 18th April 2019 23:50
    2 Attachment(s)
    • Replies: 13
    • Views: 1,989
    ads-ee
    22nd April 2019, 18:14 Go to last post

  26. what $finish will be sythesis to in verilog?

    Started by liletian, 21st April 2019 19:05
    • Replies: 5
    • Views: 309
    dave_59
    22nd April 2019, 15:54 Go to last post

  27. Generated clocks in design compiler

    Started by xdaanx, 20th April 2019 12:52
    1 Attachment(s)
    • Replies: 0
    • Views: 205
    xdaanx
    20th April 2019, 12:52 Go to last post

  28. 6T SRAM read/write current

    Started by Windywast, 18th April 2019 20:30
    • Replies: 2
    • Views: 194
    dick_freebird
    18th April 2019, 22:03 Go to last post

  29. Trouble inserting level shifters with upf and design compiler

    Started by beeflobill, 8th April 2019 19:20
    • Replies: 3
    • Views: 2,219
    ThisIsNotSam
    16th April 2019, 18:10 Go to last post

  30. [Verilog] Asynchronous Reset

    Started by EEPuppyPuppy, 15th April 2019 21:13
    • Replies: 5
    • Views: 368
    FvM
    16th April 2019, 07:58 Go to last post
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