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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 35,831
    25th March 2007, 08:41 Go to last post
  1. Boundary Cell in Core Chip

    Started by akhil_psm, 9th December 2019 17:50
    • Replies: 3
    • Views: 801
    Yesterday, 08:31 Go to last post
  2. Preferred shell for scripting, csh or bash?

    Started by tpungi, 23rd February 2020 12:15
    • Replies: 2
    • Views: 162
    Yesterday, 08:27 Go to last post
  3. Timing Closure on metal filled GDS

    Started by aditya1579, 23rd February 2020 13:29
    • Replies: 3
    • Views: 215
    Yesterday, 08:25 Go to last post
  4. Using generate and for loop to index signal name

    Started by stanford, 12th February 2020 22:47
    • Replies: 4
    • Views: 379
    24th February 2020, 18:02 Go to last post
  5. Why set_max_fanout constraint in design compiler ?

    Started by willvegapunk, 23rd February 2020 09:32
    • Replies: 5
    • Views: 389
    24th February 2020, 08:21 Go to last post
  6. What is the use of base fill

    Started by aditya1579, 23rd February 2020 12:57
    • Replies: 0
    • Views: 129
    23rd February 2020, 12:57 Go to last post
  7. Set prefix for inserted cell in innovus

    Started by Dan_Yang, 20th February 2020 08:25
    • Replies: 1
    • Views: 203
    21st February 2020, 07:21 Go to last post
  8. Reading SV assertion values using fsdb reader library

    Started by newuser11, 19th February 2020 08:07
    • Replies: 0
    • Views: 150
    19th February 2020, 08:07 Go to last post
  9. ISCAS 89-s38417 testbench required

    Started by tanish, 17th February 2020 04:00
    • Replies: 2
    • Views: 329
    18th February 2020, 13:42 Go to last post
  10. Question about scan pattern simulation

    Started by tpoleped08, 13th February 2020 20:04
    • Replies: 1
    • Views: 300
    14th February 2020, 04:59 Go to last post
  11. Clock Tree Synthesis

    Started by seahwan95, 11th February 2020 03:26
    • Replies: 1
    • Views: 264
    11th February 2020, 09:36 Go to last post
  12. How to write a 'req' before 'ack' systemverilog assertion?

    Started by ash72, 10th February 2020 21:41
    • Replies: 0
    • Views: 181
    10th February 2020, 21:41 Go to last post
    • Replies: 1
    • Views: 450
    8th February 2020, 01:46 Go to last post
  13. DFT - unused faults in atpg

    Started by avinashkumar, 5th February 2020 18:34
    • Replies: 0
    • Views: 242
    5th February 2020, 18:34 Go to last post
  14. [SOLVED] CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 2
    • Views: 516
    5th February 2020, 15:46 Go to last post
  15. [SOLVED] DFT Compiler: Clock pin not active when scan clock is on

    Started by kungchuking, 31st January 2020 06:06
    • Replies: 4
    • Views: 527
    5th February 2020, 15:41 Go to last post
  16. [SOLVED] Design not simulating for different technology node

    Started by vyella1, 3rd February 2020 17:19
    • Replies: 3
    • Views: 1,651
    4th February 2020, 23:34 Go to last post
  17. Input/Inout Pin Capacitance Attributes

    Started by janthonym, 4th February 2020 17:49
    • Replies: 1
    • Views: 203
    4th February 2020, 18:37 Go to last post
    • Replies: 2
    • Views: 337
    30th January 2020, 08:04 Go to last post
    • Replies: 0
    • Views: 287
    29th January 2020, 03:57 Go to last post
  18. Interface Logic Model in Synosys is obsolete

    Started by ldhung, 22nd January 2020 13:35
    • Replies: 2
    • Views: 549
    26th January 2020, 10:56 Go to last post
  19. [ Describing PG Pins at RTL Level UPF ]

    Started by whizkid123, 23rd January 2020 07:49
    • Replies: 1
    • Views: 325
    23rd January 2020, 08:31 Go to last post
  20. DFT Reset Constraints Handling in Spyglass DFT SGDC

    Started by whizkid123, 14th January 2020 08:58
    • Replies: 2
    • Views: 768
    17th January 2020, 06:47 Go to last post
  21. Verdi: Assertion debug mode question

    Started by swabhi812, 15th January 2020 00:02
    • Replies: 0
    • Views: 375
    15th January 2020, 00:02 Go to last post
  22. Why not simulate ATPG pattern in ATPG TetraMAX tool

    Started by abgohil013, 17th December 2019 11:05
    • Replies: 4
    • Views: 836
    14th January 2020, 09:53 Go to last post
  23. Why we insert Mbist before scan ?

    Started by alp507, 3rd January 2020 05:52
    • Replies: 4
    • Views: 659
    14th January 2020, 09:02 Go to last post
  24. Innovus CTS .tcl Script Qustions

    Started by EEPuppyPuppy, 16th December 2019 22:12
    • Replies: 5
    • Views: 1,133
    14th January 2020, 08:20 Go to last post
  25. Innovus Command Questions

    Started by EEPuppyPuppy, 13th January 2020 23:22
    • Replies: 1
    • Views: 373
    14th January 2020, 08:19 Go to last post
  26. Synopsys TetraMax ATPG B16-1 and B12-1 Error

    Started by ibtesam90, 13th January 2020 16:57
    • Replies: 0
    • Views: 293
    13th January 2020, 16:57 Go to last post