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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 35,553
    klug
    25th March 2007, 08:41 Go to last post

  1. Interface Logic Model in Synosys is obsolete

    Started by ldhung, Today 13:35
    • Replies: 0
    • Views: 43
    ldhung
    Today, 13:35 Go to last post

  2. DFT Reset Constraints Handling in Spyglass DFT SGDC

    Started by whizkid123, 14th January 2020 08:58
    • Replies: 2
    • Views: 440
    whizkid123
    17th January 2020, 06:47 Go to last post

  3. Verdi: Assertion debug mode question

    Started by swabhi812, 15th January 2020 00:02
    • Replies: 0
    • Views: 216
    swabhi812
    15th January 2020, 00:02 Go to last post

  4. Why not simulate ATPG pattern in ATPG TetraMAX tool

    Started by abgohil013, 17th December 2019 11:05
    • Replies: 4
    • Views: 610
    wizard
    14th January 2020, 09:53 Go to last post

  5. Why we insert Mbist before scan ?

    Started by alp507, 3rd January 2020 05:52
    • Replies: 4
    • Views: 413
    wizard
    14th January 2020, 09:02 Go to last post

  6. Innovus CTS .tcl Script Qustions

    Started by EEPuppyPuppy, 16th December 2019 22:12
    • Replies: 5
    • Views: 795
    ThisIsNotSam
    14th January 2020, 08:20 Go to last post

  7. Innovus Command Questions

    Started by EEPuppyPuppy, 13th January 2020 23:22
    • Replies: 1
    • Views: 175
    ThisIsNotSam
    14th January 2020, 08:19 Go to last post

  8. Synopsys TetraMax ATPG B16-1 and B12-1 Error

    Started by ibtesam90, 13th January 2020 16:57
    1 Attachment(s)
    • Replies: 0
    • Views: 140
    ibtesam90
    13th January 2020, 16:57 Go to last post

  9. Understanding LVS results (hierarchical)

    Started by aditya1579, 12th January 2020 08:31
    • Replies: 2
    • Views: 294
    timof
    13th January 2020, 04:27 Go to last post

  10. Smaller die size by tighter SPICE corners?

    Started by Macduff, 8th January 2020 11:05
    1 Attachment(s)
    • Replies: 4
    • Views: 356
    dick_freebird
    10th January 2020, 19:24 Go to last post

  11. [SOLVED] Short violations in Innovus (due to special route)

    Started by Fati_hv, 9th January 2020 11:19
    • Replies: 4
    • Views: 372
    Fati_hv
    10th January 2020, 17:30 Go to last post

  12. Does Opentimer tool for STA support VHDL netlist

    Started by garvind25, 6th January 2020 19:37
    • Replies: 2
    • Views: 369
    ThisIsNotSam
    8th January 2020, 08:19 Go to last post

  13. DIE Size calculations in TSMC22ULL GF""FDX

    Started by Elec Singh, 8th January 2020 01:13
    • Replies: 1
    • Views: 205
    ThisIsNotSam
    8th January 2020, 08:17 Go to last post

  14. Regarding synthesis of HDLs

    Started by garvind25, 26th December 2019 10:33
    • Replies: 4
    • Views: 500
    asdf44
    5th January 2020, 17:21 Go to last post

  15. CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    Started by RBTKraisee, 28th December 2019 23:52
    • Replies: 3
    • Views: 532
    RBTKraisee
    3rd January 2020, 18:20 Go to last post

  16. Are parallel universes source of high fault coverage of sequential ATPG

    Started by firewireblue, 30th December 2019 01:22
    • Replies: 2
    • Views: 343
    betwixt
    3rd January 2020, 10:09 Go to last post

  17. CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 1
    • Views: 277
    ThisIsNotSam
    3rd January 2020, 08:59 Go to last post

  18. [SOLVED] Derate Factor while calculating delay

    Started by akhil_psm, 1st January 2020 06:14
    • Replies: 1
    • Views: 262
    ThisIsNotSam
    3rd January 2020, 08:56 Go to last post

  19. Why coverage low in transition fault model as compared to stuck at fault model?

    Started by alp507, 1st January 2020 12:30
    • Replies: 0
    • Views: 270
    alp507
    1st January 2020, 12:30 Go to last post

  20. How we decide compression terminology in Scan insertion?

    Started by alp507, 1st January 2020 07:20
    • Replies: 0
    • Views: 239
    alp507
    1st January 2020, 07:20 Go to last post

  21. How test data reduce in compression ?

    Started by alp507, 30th December 2019 13:31
    • Replies: 2
    • Views: 256
    alp507
    31st December 2019, 05:41 Go to last post

  22. when neg. edge flop followed by pose. edge flop both have different clock then locku

    Started by alp507, 30th December 2019 14:11
    • Replies: 1
    • Views: 278
    dick_freebird
    31st December 2019, 04:35 Go to last post

  23. In terms of timing in ICC, What requirement should be met to say the design is valid?

    Started by 2channelkrt, 31st December 2019 04:21
    • Replies: 0
    • Views: 412
    2channelkrt
    31st December 2019, 04:21 Go to last post

  24. Verilog modulus % operator

    Started by TonyLS, 27th December 2019 05:10
    • Replies: 5
    • Views: 503
    FvM
    27th December 2019, 19:10 Go to last post

  25. Phase Detect Circuitry

    Started by promach, 18th December 2019 03:16
    • Replies: 3
    • Views: 696
    BradtheRad
    24th December 2019, 08:02 Go to last post

  26. .sdc file into Innovus WARN and ERROR

    Started by EEPuppyPuppy, 17th December 2019 23:01
    • Replies: 3
    • Views: 482
    ThisIsNotSam
    19th December 2019, 11:46 Go to last post

  27. How hold violation caused by below mentioned Scenceio

    Started by Varun124, 6th December 2019 14:06
    • Replies: 2
    • Views: 474
    Nanda_DFT
    17th December 2019, 18:51 Go to last post

  28. Can not run simv after compile Verilog project by VCS

    Started by nmphus, 7th December 2019 11:44
    • Replies: 1
    • Views: 540
    dpaul
    16th December 2019, 09:46 Go to last post

  29. Tracing clock net in Tetramax

    Started by dft1978, 16th December 2019 09:16
    • Replies: 0
    • Views: 276
    dft1978
    16th December 2019, 09:16 Go to last post

  30. How to let multiple OCC created clocks driving registers become single scan chain ?

    Started by ronald66, 14th December 2019 05:42
    1 Attachment(s)
    • Replies: 0
    • Views: 357
    ronald66
    14th December 2019, 05:42 Go to last post
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