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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,567
    klug
    25th March 2007, 08:41 Go to last post

  1. Query about Logical Efoort

    Started by kaushikrvs, Today 06:23
    • Replies: 0
    • Views: 18
    kaushikrvs
    Today, 06:23 Go to last post

  2. Static & Dynamic IR analysis operating conditions

    Started by sdbot, Yesterday 23:55
    • Replies: 0
    • Views: 59
    sdbot
    Yesterday, 23:55 Go to last post

  3. [LEC] Why needed in ASIC flow?

    Started by ivlsi, 23rd August 2018 19:16
    • Replies: 11
    • Views: 650
    gstekboy
    Yesterday, 08:39 Go to last post

  4. Endcap and Decap Usage in P&R

    Started by ranaya, 12th September 2018 14:53
    • Replies: 5
    • Views: 191
    gstekboy
    Yesterday, 04:28 Go to last post

  5. How to use Synopsys saed 28/32 technology file

    Started by jcll, 10th September 2018 19:33
    • Replies: 3
    • Views: 124
    gstekboy
    Yesterday, 04:16 Go to last post

  6. Timing Checks in primetime

    Started by kishoresai1996, 27th August 2018 10:39
    • Replies: 5
    • Views: 257
    gstekboy
    Yesterday, 04:14 Go to last post

  7. Design has 600 macros, How will you start the macro placement?

    Started by Bahubalisd, 13th April 2018 11:46
    • Replies: 4
    • Views: 680
    gstekboy
    Yesterday, 04:10 Go to last post

  8. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 3
    • Views: 182
    gstekboy
    Yesterday, 04:06 Go to last post

  9. How to comment out part of a DEF file?

    Started by ttxs, 6th March 2018 06:20
    • Replies: 3
    • Views: 594
    kumar_eee
    22nd September 2018, 17:26 Go to last post

  10. Query regarding Physical design flow

    Started by ajayg0880, 8th September 2018 07:28
    • Replies: 2
    • Views: 130
    kumar_eee
    22nd September 2018, 17:17 Go to last post

  11. Where can I get a decent technology library (.db, .sdb) for Synopsys Design Compiler

    Started by jcll, 10th September 2018 19:10
    • Replies: 2
    • Views: 392
    kumar_eee
    22nd September 2018, 17:07 Go to last post

  12. Timing Budgeting between Blocks

    Started by GDesign, 19th September 2018 12:08
    • Replies: 8
    • Views: 253
    kumar_eee
    22nd September 2018, 16:37 Go to last post

  13. Asynchronous assertion and synchronous deassertion of reset

    Started by elegz, 21st September 2018 12:04
    • Replies: 2
    • Views: 131
    FvM
    22nd September 2018, 09:21 Go to last post

  14. Using Synopsys Astro tdf file in IC Compiler

    Started by ryu_hayabusa, 26th August 2018 08:48
    • Replies: 1
    • Views: 225
    ryu_hayabusa
    21st September 2018, 01:46 Go to last post

  15. Compile Nangate45 library with Synopsys' Library Compiler

    Started by thomas.whatsoever, 19th September 2018 14:59
    • Replies: 1
    • Views: 102
    ThisIsNotSam
    19th September 2018, 15:44 Go to last post

  16. Different operating conditions in the MV and design libraries

    Started by ua6bqg, 18th September 2018 15:17
    • Replies: 2
    • Views: 144
    ua6bqg
    18th September 2018, 17:54 Go to last post

  17. Need a answer for below problem in static timing analysis

    Started by bevaratripurari8, 13th September 2018 07:43
    1 Attachment(s)
    • Replies: 6
    • Views: 242
    ua6bqg
    18th September 2018, 13:05 Go to last post

  18. How crosstalk is reduced by shield net ??

    Started by tejthammic, 17th September 2018 15:26
    • Replies: 1
    • Views: 150
    dick_freebird
    17th September 2018, 18:10 Go to last post

  19. Regarding MTech thesis topic in Verilog in frontend

    Started by edeepak93, 16th September 2018 12:54
    • Replies: 1
    • Views: 152
    ThisIsNotSam
    16th September 2018, 14:22 Go to last post

  20. Characterizing cells with verilog-A models for components

    Started by frasheed, 15th September 2018 15:00
    • Replies: 1
    • Views: 156
    ThisIsNotSam
    15th September 2018, 17:41 Go to last post

  21. Innovus (SoC Encounter) Post Layout Power Estimation

    Started by ranaya, 13th September 2018 10:47
    • Replies: 5
    • Views: 238
    ThisIsNotSam
    14th September 2018, 16:07 Go to last post

  22. Tools for DFT (SCAN insertion and ATPG)

    Started by kimthanhvu178, 13th September 2018 09:06
    • Replies: 0
    • Views: 80
    kimthanhvu178
    13th September 2018, 09:06 Go to last post

  23. .lib internal_power question

    Started by hznichol, 13th September 2018 02:20
    • Replies: 1
    • Views: 131
    oratie
    13th September 2018, 06:59 Go to last post

  24. What principles do High Level Synthesis languages use to synthesize hardware?

    Started by matrixofdynamism, 31st August 2018 12:52
    • Replies: 7
    • Views: 463
    jcll
    10th September 2018, 21:34 Go to last post

  25. why does power no longer scale with technology?

    Started by kaushikrvs, 9th September 2018 23:14
    • Replies: 3
    • Views: 244
    swabhi812
    10th September 2018, 17:44 Go to last post

  26. How can I make unmapped netlist for verilog simulation model within GTECH library?

    Started by coshy, 8th September 2018 13:18
    • Replies: 1
    • Views: 147
    ThisIsNotSam
    8th September 2018, 16:00 Go to last post

  27. Different types of pads in VLSI?

    Started by maniroop, 6th September 2018 06:17
    • Replies: 1
    • Views: 248
    ThisIsNotSam
    6th September 2018, 13:29 Go to last post

  28. What does this assignment mean?

    Started by rmk423, 3rd September 2018 08:34
    • Replies: 3
    • Views: 326
    fouwad
    5th September 2018, 06:34 Go to last post

  29. Jitter Margin in CPU Timing Closure, up to 80ps, too much? Unrealistic? Unecessary wa

    Started by Mister_hass, 31st August 2018 06:42
    • Replies: 3
    • Views: 331
    Mister_hass
    31st August 2018, 17:27 Go to last post

  30. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 2
    • Views: 210
    kishoresai1996
    31st August 2018, 07:37 Go to last post
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