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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,183
    25th March 2007, 08:41 Go to last post
    • Replies: 2
    • Views: 240
    Yesterday, 22:31 Go to last post
  1. Force in Synopsys DVE

    Started by rmk423, 25th April 2018 06:50
    • Replies: 0
    • Views: 124
    25th April 2018, 06:50 Go to last post
  2. communication port redundancy!

    Started by elecfan, 20th April 2018 20:48
    • Replies: 3
    • Views: 256
    24th April 2018, 20:26 Go to last post
  3. Innovus violates antena rules

    Started by Anklon, 22nd April 2018 15:27
    • Replies: 1
    • Views: 235
    22nd April 2018, 22:03 Go to last post
  4. [SOLVED] Area overhead pertaining to VLSI

    Started by nagulapatigirireddy, 20th April 2018 07:38
    • Replies: 1
    • Views: 179
    20th April 2018, 14:33 Go to last post
    • Replies: 0
    • Views: 127
    20th April 2018, 12:12 Go to last post
  5. Simulating Netlist in Modelsim

    Started by javierh.santiago, 14th April 2018 00:56
    • Replies: 2
    • Views: 341
    19th April 2018, 13:48 Go to last post
  6. Partial scan chain using DFT compiler

    Started by farzaneh_2561, 19th July 2014 12:02
    • Replies: 1
    • Views: 857
    18th April 2018, 08:53 Go to last post
  7. Why is casez preferred than others?

    Started by stanford, 17th April 2018 01:13
    • Replies: 6
    • Views: 304
    18th April 2018, 06:05 Go to last post
  8. [SOLVED] Partial scan chain using DFT compiler

    Started by leorezende93, 17th April 2018 20:21
    • Replies: 0
    • Views: 181
    17th April 2018, 20:21 Go to last post
  9. Migrating from encounter CTS to innovus CCOPT

    Started by rmachado, 14th April 2018 13:22
    • Replies: 11
    • Views: 536
    17th April 2018, 13:56 Go to last post
  10. Innovus CTS for a range of clock

    Started by Anklon, 16th April 2018 06:34
    • Replies: 2
    • Views: 225
    16th April 2018, 23:02 Go to last post
  11. [SOLVED] [Cadence Encounter] Connecting Macro Block pgpins

    Started by cheesyfeet, 15th April 2018 17:15
    • Replies: 3
    • Views: 260
    16th April 2018, 10:27 Go to last post
    • Replies: 4
    • Views: 283
    16th April 2018, 06:28 Go to last post
  12. Working in synthesis

    Started by ranayehya, 13th April 2018 21:57
    • Replies: 1
    • Views: 260
    16th April 2018, 02:27 Go to last post
  13. Gate delay in CMOS various technologies

    Started by Zerox100, 15th April 2018 10:54
    • Replies: 0
    • Views: 190
    15th April 2018, 10:54 Go to last post
  14. UVM Register Model with unknown register address

    Started by jiminization, 13th April 2018 10:58
    • Replies: 1
    • Views: 211
    13th April 2018, 21:58 Go to last post
  15. Prime time tool of Synopsys

    Started by harshahari, 12th April 2018 09:38
    • Replies: 3
    • Views: 345
    13th April 2018, 19:28 Go to last post
  16. How to understand an eVCD file?

    Started by rmk423, 12th April 2018 06:51
    • Replies: 1
    • Views: 234
    13th April 2018, 18:27 Go to last post
  17. Macro placement in ICC Tool

    Started by jagannathsharma, 12th April 2018 07:57
    • Replies: 6
    • Views: 290
    13th April 2018, 14:17 Go to last post
    • Replies: 1
    • Views: 233
    13th April 2018, 14:16 Go to last post
  18. [SOLVED] WHAT is STIL DPV and how it is diffrent from verilog testbench

    Started by artik.patel, 27th October 2017 08:18
    • Replies: 3
    • Views: 1,125
    13th April 2018, 13:45 Go to last post
  19. Prime time tool input files

    Started by harshahari, 13th April 2018 10:33
    • Replies: 0
    • Views: 178
    13th April 2018, 10:33 Go to last post
  20. When can we avoid using reset synchronizer?

    Started by stanford, 11th April 2018 19:36
    • Replies: 10
    • Views: 417
    12th April 2018, 21:13 Go to last post
  21. Synchronous Reset and Load STA and SR feedback

    Started by mwb, 11th April 2018 19:10
    • Replies: 1
    • Views: 236
    12th April 2018, 15:53 Go to last post
  22. Static timing analysis

    Started by harshahari, 11th April 2018 07:09
    • Replies: 5
    • Views: 385
    12th April 2018, 14:24 Go to last post