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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 35,744
    klug
    25th March 2007, 08:41 Go to last post

  1. Question about scan pattern simulation

    Started by tpoleped08, 13th February 2020 20:04
    • Replies: 1
    • Views: 208
    tpoleped08
    14th February 2020, 04:59 Go to last post

  2. Using generate and for loop to index signal name

    Started by stanford, 12th February 2020 22:47
    • Replies: 1
    • Views: 180
    dave_59
    13th February 2020, 01:07 Go to last post

  3. Clock Tree Synthesis

    Started by seahwan95, 11th February 2020 03:26
    • Replies: 1
    • Views: 194
    ThisIsNotSam
    11th February 2020, 09:36 Go to last post

  4. How to write a 'req' before 'ack' systemverilog assertion?

    Started by ash72, 10th February 2020 21:41
    • Replies: 0
    • Views: 136
    ash72
    10th February 2020, 21:41 Go to last post

  5. Boundary Cell in Core Chip

    Started by akhil_psm, 9th December 2019 17:50
    • Replies: 2
    • Views: 673
    kungchuking
    8th February 2020, 02:05 Go to last post

  6. Why coverage low in transition fault model as compared to stuck at fault model?

    Started by alp507, 1st January 2020 12:30
    • Replies: 1
    • Views: 397
    kungchuking
    8th February 2020, 01:46 Go to last post

  7. DFT - unused faults in atpg

    Started by avinashkumar, 5th February 2020 18:34
    • Replies: 0
    • Views: 192
    avinashkumar
    5th February 2020, 18:34 Go to last post

  8. [SOLVED] CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 2
    • Views: 457
    kungchuking
    5th February 2020, 15:46 Go to last post

  9. [SOLVED] DFT Compiler: Clock pin not active when scan clock is on

    Started by kungchuking, 31st January 2020 06:06
    3 Attachment(s)
    • Replies: 4
    • Views: 438
    kungchuking
    5th February 2020, 15:41 Go to last post

  10. How D flip flop can hold output until next clock cycle when it is level firered.

    Started by miso156, 4th February 2020 16:28
    3 Attachment(s)
    • Replies: 5
    • Views: 356
    dick_freebird
    5th February 2020, 01:23 Go to last post

  11. [SOLVED] Design not simulating for different technology node

    Started by vyella1, 3rd February 2020 17:19
    • Replies: 3
    • Views: 1,206
    ads-ee
    4th February 2020, 23:34 Go to last post

  12. Input/Inout Pin Capacitance Attributes

    Started by janthonym, 4th February 2020 17:49
    • Replies: 1
    • Views: 154
    janthonym
    4th February 2020, 18:37 Go to last post

  13. why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

    Started by kaushikrvs, 29th January 2020 22:00
    • Replies: 2
    • Views: 276
    ThisIsNotSam
    30th January 2020, 08:04 Go to last post

  14. What is retianing_rise and retianing_fall in SRAM_lib ?

    Started by kinglongzh, 29th January 2020 03:57
    • Replies: 0
    • Views: 245
    kinglongzh
    29th January 2020, 03:57 Go to last post

  15. Interface Logic Model in Synosys is obsolete

    Started by ldhung, 22nd January 2020 13:35
    • Replies: 2
    • Views: 499
    ldhung
    26th January 2020, 10:56 Go to last post

  16. [ Describing PG Pins at RTL Level UPF ]

    Started by whizkid123, 23rd January 2020 07:49
    • Replies: 1
    • Views: 281
    ThisIsNotSam
    23rd January 2020, 08:31 Go to last post

  17. DFT Reset Constraints Handling in Spyglass DFT SGDC

    Started by whizkid123, 14th January 2020 08:58
    • Replies: 2
    • Views: 696
    whizkid123
    17th January 2020, 06:47 Go to last post

  18. Verdi: Assertion debug mode question

    Started by swabhi812, 15th January 2020 00:02
    • Replies: 0
    • Views: 331
    swabhi812
    15th January 2020, 00:02 Go to last post

  19. Why not simulate ATPG pattern in ATPG TetraMAX tool

    Started by abgohil013, 17th December 2019 11:05
    • Replies: 4
    • Views: 768
    wizard
    14th January 2020, 09:53 Go to last post

  20. Why we insert Mbist before scan ?

    Started by alp507, 3rd January 2020 05:52
    • Replies: 4
    • Views: 594
    wizard
    14th January 2020, 09:02 Go to last post

  21. Innovus CTS .tcl Script Qustions

    Started by EEPuppyPuppy, 16th December 2019 22:12
    • Replies: 5
    • Views: 1,039
    ThisIsNotSam
    14th January 2020, 08:20 Go to last post

  22. Innovus Command Questions

    Started by EEPuppyPuppy, 13th January 2020 23:22
    • Replies: 1
    • Views: 321
    ThisIsNotSam
    14th January 2020, 08:19 Go to last post

  23. Synopsys TetraMax ATPG B16-1 and B12-1 Error

    Started by ibtesam90, 13th January 2020 16:57
    1 Attachment(s)
    • Replies: 0
    • Views: 255
    ibtesam90
    13th January 2020, 16:57 Go to last post

  24. Understanding LVS results (hierarchical)

    Started by aditya1579, 12th January 2020 08:31
    • Replies: 2
    • Views: 446
    timof
    13th January 2020, 04:27 Go to last post

  25. Smaller die size by tighter SPICE corners?

    Started by Macduff, 8th January 2020 11:05
    1 Attachment(s)
    • Replies: 4
    • Views: 486
    dick_freebird
    10th January 2020, 19:24 Go to last post

  26. [SOLVED] Short violations in Innovus (due to special route)

    Started by Fati_hv, 9th January 2020 11:19
    • Replies: 4
    • Views: 557
    Fati_hv
    10th January 2020, 17:30 Go to last post

  27. Does Opentimer tool for STA support VHDL netlist

    Started by garvind25, 6th January 2020 19:37
    • Replies: 2
    • Views: 475
    ThisIsNotSam
    8th January 2020, 08:19 Go to last post

  28. DIE Size calculations in TSMC22ULL GF""FDX

    Started by Elec Singh, 8th January 2020 01:13
    • Replies: 1
    • Views: 285
    ThisIsNotSam
    8th January 2020, 08:17 Go to last post

  29. Regarding synthesis of HDLs

    Started by garvind25, 26th December 2019 10:33
    • Replies: 4
    • Views: 641
    asdf44
    5th January 2020, 17:21 Go to last post

  30. CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    Started by RBTKraisee, 28th December 2019 23:52
    • Replies: 3
    • Views: 664
    RBTKraisee
    3rd January 2020, 18:20 Go to last post
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