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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,086
    25th March 2007, 08:41 Go to last post
  1. LBIST low test coverage

    Started by vijay82, Today 08:21
    • Replies: 1
    • Views: 51
    Today, 15:06 Go to last post
  2. How to fix unclocked register?

    Started by kartikpujari, 20th October 2019 18:50
    • Replies: 1
    • Views: 331
    21st October 2019, 07:04 Go to last post
  3. Usage of Synchronous and Asynchronuos FIFOs

    Started by Muthuraja.M, 20th October 2019 09:29
    • Replies: 2
    • Views: 244
    20th October 2019, 17:45 Go to last post
    • Replies: 6
    • Views: 697
    20th October 2019, 01:50 Go to last post
  4. What cells are placed around RAM? Why?

    Started by Dan_Yang, 8th October 2019 15:04
    • Replies: 2
    • Views: 538
    17th October 2019, 10:44 Go to last post
  5. How to create parallel TDL patters in tetramax

    Started by Varun124, 13th October 2019 21:26
    • Replies: 0
    • Views: 179
    13th October 2019, 21:26 Go to last post
  6. What is meant by Split CODEC IN DFT ?

    Started by Varun124, 12th October 2019 10:18
    • Replies: 0
    • Views: 182
    12th October 2019, 10:18 Go to last post
    • Replies: 1
    • Views: 411
    11th October 2019, 09:19 Go to last post
    • Replies: 4
    • Views: 508
    10th October 2019, 10:45 Go to last post
    • Replies: 1
    • Views: 212
    9th October 2019, 01:46 Go to last post
  7. Formal verification of AHB bus, arbiter confusion

    Started by Haraldovs, 8th October 2019 07:57
    • Replies: 0
    • Views: 173
    8th October 2019, 07:57 Go to last post
  8. default statement in case

    Started by stanford, 5th October 2019 23:15
    • Replies: 6
    • Views: 588
    7th October 2019, 23:54 Go to last post
  9. Generating chain patterns in tetramax tool

    Started by Varun124, 7th October 2019 16:19
    • Replies: 0
    • Views: 171
    7th October 2019, 16:19 Go to last post
  10. Site row overlapping

    Started by kartikpujari, 2nd October 2019 17:00
    • Replies: 5
    • Views: 656
    5th October 2019, 09:02 Go to last post
  11. How to identify design in terms of track ?

    Started by kartikpujari, 4th October 2019 09:49
    • Replies: 1
    • Views: 231
    4th October 2019, 11:43 Go to last post
  12. [SOLVED] Post place & route netlist simulation is failing although STA is ok

    Started by mifio, 25th September 2019 14:04
    • Replies: 8
    • Views: 656
    2nd October 2019, 06:52 Go to last post
    • Replies: 3
    • Views: 332
    30th September 2019, 20:06 Go to last post
  13. Multiple scan clocks

    Started by Varun124, 28th September 2019 09:06
    • Replies: 1
    • Views: 238
    30th September 2019, 13:57 Go to last post
  14. scan chain inside memory

    Started by fragnen, 13th September 2019 09:19
    • Replies: 12
    • Views: 801
    30th September 2019, 13:52 Go to last post
  15. FAN OUT /FAN IN for Logic Families

    Started by Robotduck, 25th September 2019 20:54
    • Replies: 2
    • Views: 240
    25th September 2019, 23:08 Go to last post
  16. output and input impedance impedance

    Started by zuirgham, 24th September 2019 13:13
    • Replies: 1
    • Views: 256
    25th September 2019, 04:13 Go to last post
    • Replies: 0
    • Views: 213
    23rd September 2019, 13:36 Go to last post
  17. Extracting MOSRA LEVEL 3 Parameters and values

    Started by tanish, 20th September 2019 21:37
    • Replies: 0
    • Views: 281
    20th September 2019, 21:37 Go to last post
  18. Gate Level Simulation

    Started by fragnen, 16th September 2019 10:13
    • Replies: 11
    • Views: 883
    19th September 2019, 15:02 Go to last post
    • Replies: 0
    • Views: 246
    19th September 2019, 02:02 Go to last post
    • Replies: 0
    • Views: 203
    18th September 2019, 14:15 Go to last post
  19. Lockup Latch for DFT purpose

    Started by Varun124, 3rd July 2019 19:34
    • Replies: 8
    • Views: 748
    18th September 2019, 11:46 Go to last post
    • Replies: 5
    • Views: 535
    17th September 2019, 18:33 Go to last post
  20. vcd file generation for netlist

    Started by maru2488, 4th September 2019 07:19
    • Replies: 2
    • Views: 346
    17th September 2019, 12:45 Go to last post
    • Replies: 1
    • Views: 444
    17th September 2019, 11:27 Go to last post