1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    106,122
Page 1 of 799 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 23956

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,183
    klug
    25th March 2007, 08:41 Go to last post

  1. [Cadence Encounter] Macro Block Signal Pin Connections

    Started by cheesyfeet, 21st April 2018 08:58
    2 Attachment(s)
    • Replies: 2
    • Views: 240
    cheesyfeet
    Yesterday, 22:31 Go to last post

  2. How to stitch multi bit flip-flop into wrapper chains in tessent -shell

    Started by WarrenWang, Yesterday 07:17
    • Replies: 0
    • Views: 71
    WarrenWang
    Yesterday, 07:17 Go to last post

  3. What do I need to set up in order to generate abstract view in Virtuoso?

    Started by javierh.santiago, 24th April 2018 19:59
    • Replies: 3
    • Views: 266
    ThisIsNotSam
    25th April 2018, 21:07 Go to last post

  4. Force in Synopsys DVE

    Started by rmk423, 25th April 2018 06:50
    • Replies: 0
    • Views: 124
    rmk423
    25th April 2018, 06:50 Go to last post

  5. communication port redundancy!

    Started by elecfan, 20th April 2018 20:48
    1 Attachment(s)
    • Replies: 3
    • Views: 256
    elecfan
    24th April 2018, 20:26 Go to last post

  6. Innovus violates antena rules

    Started by Anklon, 22nd April 2018 15:27
    • Replies: 1
    • Views: 235
    ThisIsNotSam
    22nd April 2018, 22:03 Go to last post

  7. [SOLVED] Area overhead pertaining to VLSI

    Started by nagulapatigirireddy, 20th April 2018 07:38
    • Replies: 1
    • Views: 179
    ThisIsNotSam
    20th April 2018, 14:33 Go to last post

  8. Input reference library in synopsys ic compiler tool

    Started by harshahari, 20th April 2018 12:12
    • Replies: 0
    • Views: 127
    harshahari
    20th April 2018, 12:12 Go to last post

  9. What is the purpose of using Memory Models from EDA vendor? What are its advantages ?

    Started by rshrig, 19th April 2018 10:52
    • Replies: 5
    • Views: 284
    ThisIsNotSam
    20th April 2018, 01:13 Go to last post

  10. Simulating Netlist in Modelsim

    Started by javierh.santiago, 14th April 2018 00:56
    • Replies: 2
    • Views: 341
    wesleytaylor
    19th April 2018, 13:48 Go to last post

  11. Why we are doing static IR drop analysis eventhough dynamic IR drop results accurate?

    Started by DineshCalc, 19th April 2018 05:36
    • Replies: 0
    • Views: 171
    DineshCalc
    19th April 2018, 05:36 Go to last post

  12. Partial scan chain using DFT compiler

    Started by farzaneh_2561, 19th July 2014 12:02
    • Replies: 1
    • Views: 857
    bassa
    18th April 2018, 08:53 Go to last post

  13. Why is casez preferred than others?

    Started by stanford, 17th April 2018 01:13
    • Replies: 6
    • Views: 304
    Ashish Agrawal
    18th April 2018, 06:05 Go to last post

  14. [SOLVED] Partial scan chain using DFT compiler

    Started by leorezende93, 17th April 2018 20:21
    • Replies: 0
    • Views: 181
    leorezende93
    17th April 2018, 20:21 Go to last post

  15. Migrating from encounter CTS to innovus CCOPT

    Started by rmachado, 14th April 2018 13:22
    2 Attachment(s)
    • Replies: 11
    • Views: 536
    ThisIsNotSam
    17th April 2018, 13:56 Go to last post

  16. Innovus CTS for a range of clock

    Started by Anklon, 16th April 2018 06:34
    • Replies: 2
    • Views: 225
    ThisIsNotSam
    16th April 2018, 23:02 Go to last post

  17. [SOLVED] [Cadence Encounter] Connecting Macro Block pgpins

    Started by cheesyfeet, 15th April 2018 17:15
    6 Attachment(s)
    • Replies: 3
    • Views: 260
    cheesyfeet
    16th April 2018, 10:27 Go to last post

  18. [Cadence Genus Synthesis] How to add more than one library file for synthesis?

    Started by kurax, 13th April 2018 13:10
    • Replies: 4
    • Views: 283
    kurax
    16th April 2018, 06:28 Go to last post

  19. Working in synthesis

    Started by ranayehya, 13th April 2018 21:57
    • Replies: 1
    • Views: 260
    slutarius
    16th April 2018, 02:27 Go to last post

  20. Gate delay in CMOS various technologies

    Started by Zerox100, 15th April 2018 10:54
    • Replies: 0
    • Views: 190
    Zerox100
    15th April 2018, 10:54 Go to last post

  21. UVM Register Model with unknown register address

    Started by jiminization, 13th April 2018 10:58
    • Replies: 1
    • Views: 211
    dave_59
    13th April 2018, 21:58 Go to last post

  22. Prime time tool of Synopsys

    Started by harshahari, 12th April 2018 09:38
    • Replies: 3
    • Views: 345
    ads-ee
    13th April 2018, 19:28 Go to last post

  23. How to understand an eVCD file?

    Started by rmk423, 12th April 2018 06:51
    • Replies: 1
    • Views: 234
    dave_59
    13th April 2018, 18:27 Go to last post

  24. Macro placement in ICC Tool

    Started by jagannathsharma, 12th April 2018 07:57
    • Replies: 6
    • Views: 290
    ThisIsNotSam
    13th April 2018, 14:17 Go to last post

  25. Design has 600 macros, How will you start the macro placement?

    Started by Bahubalisd, 13th April 2018 11:46
    • Replies: 1
    • Views: 233
    ThisIsNotSam
    13th April 2018, 14:16 Go to last post

  26. [SOLVED] WHAT is STIL DPV and how it is diffrent from verilog testbench

    Started by artik.patel, 27th October 2017 08:18
    • Replies: 3
    • Views: 1,125
    artik.patel
    13th April 2018, 13:45 Go to last post

  27. Prime time tool input files

    Started by harshahari, 13th April 2018 10:33
    • Replies: 0
    • Views: 178
    harshahari
    13th April 2018, 10:33 Go to last post

  28. When can we avoid using reset synchronizer?

    Started by stanford, 11th April 2018 19:36
    • Replies: 10
    • Views: 417
    morris_mano
    12th April 2018, 21:13 Go to last post

  29. Synchronous Reset and Load STA and SR feedback

    Started by mwb, 11th April 2018 19:10
    1 Attachment(s)
    • Replies: 1
    • Views: 236
    mwb
    12th April 2018, 15:53 Go to last post

  30. Static timing analysis

    Started by harshahari, 11th April 2018 07:09
    • Replies: 5
    • Views: 385
    ThisIsNotSam
    12th April 2018, 14:24 Go to last post
Powered by vBulletin
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.