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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,297
    klug
    25th March 2007, 08:41 Go to last post

  1. FERROCORE FR3 more information?

    Started by Coper, Yesterday 10:42
    • Replies: 2
    • Views: 129
    FvM
    Yesterday, 14:47 Go to last post

  2. In PrimeTime, how can I view setup/hold times per endpoint in easy format for parsing

    Started by majd229, 19th July 2019 16:35
    • Replies: 1
    • Views: 185
    ThisIsNotSam
    19th July 2019, 19:26 Go to last post

  3. CRC Error insertion and detection

    Started by rrucha, 17th July 2019 21:01
    • Replies: 4
    • Views: 281
    rrucha
    19th July 2019, 19:19 Go to last post

  4. dft-how to use .bench format

    Started by avinashkumar, 18th July 2019 09:18
    • Replies: 1
    • Views: 142
    dpaul
    19th July 2019, 12:16 Go to last post

  5. Dft - tetramax for pattern generation and test coverage

    Started by avinashkumar, 17th July 2019 19:12
    • Replies: 0
    • Views: 86
    avinashkumar
    17th July 2019, 19:12 Go to last post

  6. In PrimeTime, whats are -start_end_pair and -cover_design in report_timing cmd?

    Started by majd229, 17th July 2019 16:19
    • Replies: 0
    • Views: 94
    majd229
    17th July 2019, 16:19 Go to last post

  7. Input & output delay in mixed signal chip - RTL Signal Integrity

    Started by The_Dutchman, 14th July 2019 09:46
    1 Attachment(s)
    • Replies: 3
    • Views: 249
    ThisIsNotSam
    16th July 2019, 18:55 Go to last post

  8. Tech library problem

    Started by abdoboua, 16th July 2019 12:15
    4 Attachment(s)
    • Replies: 3
    • Views: 170
    ThisIsNotSam
    16th July 2019, 18:49 Go to last post

  9. [SOLVED] What is the difference of power estimation between Design Compiler and PrimeTIme PX

    Started by kkpark, 16th July 2019 06:34
    • Replies: 4
    • Views: 229
    ThisIsNotSam
    16th July 2019, 17:30 Go to last post

  10. [m]What is the difference between "Damascene copper" interconnect and normal copper ?

    Started by RohithRaj, 16th July 2019 13:22
    • Replies: 1
    • Views: 156
    ThisIsNotSam
    16th July 2019, 17:24 Go to last post

  11. Help needed for spice conversion from mdl syntax

    Started by smurtuzah, 16th July 2019 13:29
    • Replies: 0
    • Views: 101
    smurtuzah
    16th July 2019, 13:29 Go to last post

  12. DRC problem with layout in cadence 617

    Started by abdoboua, 8th July 2019 19:05
    • Replies: 1
    • Views: 155
    jbeniston
    16th July 2019, 11:35 Go to last post

  13. How do I know inbetween which pins do arcs exist in PrimeTime for timing libs?

    Started by majd229, 15th July 2019 20:40
    • Replies: 1
    • Views: 118
    oratie
    16th July 2019, 06:14 Go to last post

  14. Problem when installing Calibre

    Started by abdoboua, 10th July 2019 20:35
    • Replies: 1
    • Views: 151
    slizak
    15th July 2019, 16:22 Go to last post

  15. ModelSim simulation error

    Started by garvind25, 11th July 2019 10:42
    3 Attachment(s)
    • Replies: 11
    • Views: 458
    ads-ee
    15th July 2019, 15:59 Go to last post

  16. Cannot find vdd in the design

    Started by kartikpujari, 14th July 2019 05:25
    • Replies: 2
    • Views: 205
    dick_freebird
    14th July 2019, 19:44 Go to last post

  17. Shadow path causing parallel simulation to fail. Serial is passing.

    Started by finsiherfish, 22nd March 2019 16:36
    • Replies: 1
    • Views: 317
    CHIRU777
    14th July 2019, 18:48 Go to last post

  18. Is it possible to assign a value to a signal in a systemverilog assertion?

    Started by iammedjay, 18th June 2019 08:53
    • Replies: 3
    • Views: 249
    andre_teprom
    14th July 2019, 01:44 Go to last post

  19. Systemverilog type cast or integer division

    Started by parafux, 10th July 2019 13:51
    • Replies: 2
    • Views: 205
    kripacharya
    13th July 2019, 18:53 Go to last post

  20. Global Buffer Access Normalized Energy Cost

    Started by moa375, 12th July 2019 21:51
    • Replies: 0
    • Views: 155
    moa375
    12th July 2019, 21:51 Go to last post

  21. What do you mean by Predictive FIFO?

    Started by rameshbabur, 11th July 2019 08:01
    • Replies: 2
    • Views: 238
    kripacharya
    12th July 2019, 19:01 Go to last post

  22. 32 bit left shift of a longint variable does not work

    Started by parafux, 11th July 2019 06:23
    • Replies: 2
    • Views: 218
    kripacharya
    12th July 2019, 18:46 Go to last post

  23. Facing issue of long runtime to find a legal location for cell , in clock opt stage

    Started by reddvoid, 12th July 2019 07:03
    • Replies: 1
    • Views: 168
    ThisIsNotSam
    12th July 2019, 16:48 Go to last post

  24. Digital design of a GPU

    Started by adwnis123, 11th July 2019 14:06
    • Replies: 3
    • Views: 296
    asdf44
    12th July 2019, 14:00 Go to last post

  25. Saving the layout in innovus

    Started by Chinmaye, 10th July 2019 11:45
    4 Attachment(s)
    • Replies: 7
    • Views: 339
    ThisIsNotSam
    11th July 2019, 17:44 Go to last post

  26. How do I decide clock period constrain for Synthesis in DC?

    Started by asic_architect, 10th July 2019 03:20
    • Replies: 3
    • Views: 250
    ThisIsNotSam
    10th July 2019, 21:41 Go to last post

  27. [SOLVED] Error during clock tree synthesis in innovus

    Started by Chinmaye, 10th July 2019 10:51
    • Replies: 1
    • Views: 125
    Chinmaye
    10th July 2019, 17:34 Go to last post

  28. pins of symbol and layout do not match

    Started by abdoboua, 9th July 2019 12:01
    8 Attachment(s)
    • Replies: 4
    • Views: 221
    abdoboua
    9th July 2019, 21:59 Go to last post

  29. Help in understanding innovus

    Started by Chinmaye, 5th July 2019 06:56
    1 Attachment(s)
    • Replies: 5
    • Views: 468
    ThisIsNotSam
    9th July 2019, 14:30 Go to last post

  30. Effect of adding an BUF/INV in physical Design on LEC

    Started by gauravgautam, 8th July 2019 10:03
    • Replies: 2
    • Views: 156
    ThisIsNotSam
    8th July 2019, 15:51 Go to last post
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