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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,316
    klug
    25th March 2007, 08:41 Go to last post

  1. Synopsys VP Virtualizer installation

    Started by yuhiub90, Today 09:09
    • Replies: 0
    • Views: 1
    yuhiub90
    Today, 09:09 Go to last post

  2. Script for adding wires in Encounter

    Started by Mahmoud_Dagher, Today 03:10
    • Replies: 0
    • Views: 19
    Mahmoud_Dagher
    Today, 03:10 Go to last post

  3. async fifo - almost full/empty

    Started by stanford, 10th June 2018 08:24
    • Replies: 6
    • Views: 249
    KlausST
    Today, 00:53 Go to last post

  4. I need a driver (ANSI C99) or design manual for the NCR53c94...

    Started by e-music, Today 00:33
    • Replies: 0
    • Views: 29
    e-music
    Today, 00:33 Go to last post

  5. Non clock cells on clock path

    Started by stanford, Yesterday 23:01
    • Replies: 0
    • Views: 46
    stanford
    Yesterday, 23:01 Go to last post

  6. Undefined Packets when importing a gds from Encounter to Cadence Virtuoso

    Started by Mahmoud_Dagher, Yesterday 22:55
    • Replies: 0
    • Views: 33
    Mahmoud_Dagher
    Yesterday, 22:55 Go to last post

  7. How to use ICC2 to merge 2 LEFs into 1 monolithic LEF?

    Started by majd229, Yesterday 17:44
    • Replies: 2
    • Views: 64
    majd229
    Yesterday, 22:42 Go to last post

  8. Memory/macro internal clock insertion delay

    Started by argha, 16th June 2018 20:12
    • Replies: 1
    • Views: 146
    ThisIsNotSam
    Yesterday, 14:17 Go to last post

  9. Import a layout from Encounter to Virtuoso

    Started by Mahmoud_Dagher, 14th June 2018 14:53
    • Replies: 5
    • Views: 207
    ThisIsNotSam
    Yesterday, 14:15 Go to last post

  10. Plotting the transient noise distribution in virtuoso

    Started by romanb, 17th June 2018 19:27
    • Replies: 1
    • Views: 88
    jjx
    Yesterday, 10:16 Go to last post

  11. When is data captured and data launched in SPI transmission?

    Started by kaushikrvs, 15th June 2018 13:04
    • Replies: 2
    • Views: 153
    ads-ee
    15th June 2018, 15:36 Go to last post

  12. SPI Slave with strange behavior

    Started by rmachado, 9th June 2018 13:59
    2 Pages •
    1 2
    9 Attachment(s)
    • Replies: 25
    • Views: 597
    rmachado
    15th June 2018, 10:57 Go to last post

  13. SDC constraints for asynchronous reset

    Started by Alexxk, 14th June 2018 12:04
    • Replies: 2
    • Views: 102
    slutarius
    15th June 2018, 10:36 Go to last post

  14. Timing Sign off from Primetime

    Started by sreejinair, 11th June 2018 14:38
    • Replies: 4
    • Views: 274
    sreejinair
    12th June 2018, 15:33 Go to last post

  15. What happens when the width is too large for the length of the MOSFET?

    Started by littlerock, 5th June 2018 09:41
    • Replies: 4
    • Views: 325
    frankrose
    9th June 2018, 17:56 Go to last post

  16. UMC 65nm without TLU+ files

    Started by ua6bqg, 8th June 2018 16:30
    • Replies: 1
    • Views: 123
    ThisIsNotSam
    8th June 2018, 18:00 Go to last post

  17. [moved] Physical design placement timing issue

    Started by prabhu14, 7th June 2018 19:05
    • Replies: 2
    • Views: 175
    ThisIsNotSam
    8th June 2018, 14:54 Go to last post

  18. Cadence lint error: CLKDMN

    Started by Sam26, 7th June 2018 10:45
    • Replies: 3
    • Views: 171
    Sam26
    8th June 2018, 12:37 Go to last post

  19. [moved] 50Mz to 1 kHz clock generator

    Started by sanjaysharmaiitk, 8th June 2018 09:26
    3 Attachment(s)
    • Replies: 1
    • Views: 134
    KlausST
    8th June 2018, 10:14 Go to last post

  20. Cell Characterization Determining Slew vs Capacitive Values for Templates

    Started by ranaya, 23rd May 2018 19:20
    • Replies: 6
    • Views: 349
    ThisIsNotSam
    7th June 2018, 14:35 Go to last post

  21. Cadence Encounter place and route - Pins not covered by metal layer

    Started by NikosTS, 7th May 2018 10:01
    • Replies: 10
    • Views: 526
    jackoup
    4th June 2018, 11:41 Go to last post

  22. Program Error:unhandled pattern type while reading external VCDE pattern in TetraMax

    Started by edab_johnhsu, 4th June 2018 07:56
    • Replies: 0
    • Views: 266
    edab_johnhsu
    4th June 2018, 07:56 Go to last post

  23. bit width for addition

    Started by sky_above, 2nd June 2018 14:04
    • Replies: 3
    • Views: 220
    vGoodtimes
    3rd June 2018, 22:22 Go to last post

  24. Realization of D flip flop by basic gates from library while synthesizing

    Started by sky_above, 26th May 2018 16:47
    • Replies: 7
    • Views: 390
    FvM
    2nd June 2018, 16:10 Go to last post

  25. Output combinational output and valid sequential

    Started by sky_above, 26th May 2018 16:22
    • Replies: 9
    • Views: 400
    barry
    2nd June 2018, 15:28 Go to last post

  26. Books or websites to learn digital system design

    Started by sky_above, 2nd June 2018 14:01
    • Replies: 0
    • Views: 130
    sky_above
    2nd June 2018, 14:01 Go to last post

  27. TrueNorth Evaluation Board

    Started by mwn1, 2nd June 2018 04:58
    • Replies: 0
    • Views: 92
    mwn1
    2nd June 2018, 04:58 Go to last post

  28. Force deposit through testbench

    Started by rmk423, 25th April 2018 06:50
    • Replies: 4
    • Views: 487
    ads-ee
    31st May 2018, 16:27 Go to last post

  29. HSPICE 2013 SP2 28T Full Adder Simulation Problem

    Started by Mohammad Amin Nili, 29th May 2018 21:59
    2 Attachment(s)
    • Replies: 7
    • Views: 375
    FvM
    30th May 2018, 13:29 Go to last post

  30. generic parameter while instantiating design at top level if allowed

    Started by sky_above, 27th May 2018 10:05
    • Replies: 7
    • Views: 347
    ads-ee
    29th May 2018, 18:28 Go to last post
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