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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,550
    klug
    25th March 2007, 08:41 Go to last post

  1. Timing Budgeting between Blocks

    Started by GDesign, Today 12:08
    • Replies: 5
    • Views: 98
    ThisIsNotSam
    Today, 17:10 Go to last post

  2. Compile Nangate45 library with Synopsys' Library Compiler

    Started by thomas.whatsoever, Today 14:59
    • Replies: 1
    • Views: 47
    ThisIsNotSam
    Today, 15:44 Go to last post

  3. Different operating conditions in the MV and design libraries

    Started by ua6bqg, Yesterday 15:17
    • Replies: 2
    • Views: 107
    ua6bqg
    Yesterday, 17:54 Go to last post

  4. Need a answer for below problem in static timing analysis

    Started by bevaratripurari8, 13th September 2018 07:43
    1 Attachment(s)
    • Replies: 6
    • Views: 209
    ua6bqg
    Yesterday, 13:05 Go to last post

  5. How crosstalk is reduced by shield net ??

    Started by tejthammic, 17th September 2018 15:26
    • Replies: 1
    • Views: 118
    dick_freebird
    17th September 2018, 18:10 Go to last post

  6. Regarding MTech thesis topic in Verilog in frontend

    Started by edeepak93, 16th September 2018 12:54
    • Replies: 1
    • Views: 134
    ThisIsNotSam
    16th September 2018, 14:22 Go to last post

  7. Characterizing cells with verilog-A models for components

    Started by frasheed, 15th September 2018 15:00
    • Replies: 1
    • Views: 142
    ThisIsNotSam
    15th September 2018, 17:41 Go to last post

  8. Innovus (SoC Encounter) Post Layout Power Estimation

    Started by ranaya, 13th September 2018 10:47
    • Replies: 5
    • Views: 219
    ThisIsNotSam
    14th September 2018, 16:07 Go to last post

  9. Tools for DFT (SCAN insertion and ATPG)

    Started by kimthanhvu178, 13th September 2018 09:06
    • Replies: 0
    • Views: 70
    kimthanhvu178
    13th September 2018, 09:06 Go to last post

  10. .lib internal_power question

    Started by hznichol, 13th September 2018 02:20
    • Replies: 1
    • Views: 117
    oratie
    13th September 2018, 06:59 Go to last post

  11. Endcap and Decap Usage in P&R

    Started by ranaya, 12th September 2018 14:53
    • Replies: 3
    • Views: 145
    ThisIsNotSam
    12th September 2018, 17:55 Go to last post

  12. Where can I get a decent technology library (.db, .sdb) for Synopsys Design Compiler

    Started by jcll, 10th September 2018 19:10
    • Replies: 1
    • Views: 369
    ThisIsNotSam
    11th September 2018, 00:42 Go to last post

  13. How to use Synopsys saed 28/32 technology file

    Started by jcll, 10th September 2018 19:33
    • Replies: 1
    • Views: 99
    ThisIsNotSam
    11th September 2018, 00:41 Go to last post

  14. What principles do High Level Synthesis languages use to synthesize hardware?

    Started by matrixofdynamism, 31st August 2018 12:52
    • Replies: 7
    • Views: 443
    jcll
    10th September 2018, 21:34 Go to last post

  15. why does power no longer scale with technology?

    Started by kaushikrvs, 9th September 2018 23:14
    • Replies: 3
    • Views: 230
    swabhi812
    10th September 2018, 17:44 Go to last post

  16. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 1
    • Views: 156
    ThisIsNotSam
    8th September 2018, 16:02 Go to last post

  17. Query regarding Physical design flow

    Started by ajayg0880, 8th September 2018 07:28
    • Replies: 1
    • Views: 106
    ThisIsNotSam
    8th September 2018, 16:01 Go to last post

  18. How can I make unmapped netlist for verilog simulation model within GTECH library?

    Started by coshy, 8th September 2018 13:18
    • Replies: 1
    • Views: 138
    ThisIsNotSam
    8th September 2018, 16:00 Go to last post

  19. Different types of pads in VLSI?

    Started by maniroop, 6th September 2018 06:17
    • Replies: 1
    • Views: 230
    ThisIsNotSam
    6th September 2018, 13:29 Go to last post

  20. What does this assignment mean?

    Started by rmk423, 3rd September 2018 08:34
    • Replies: 3
    • Views: 314
    fouwad
    5th September 2018, 06:34 Go to last post

  21. [LEC] Why needed in ASIC flow?

    Started by ivlsi, 23rd August 2018 19:16
    • Replies: 10
    • Views: 589
    jt_eaton
    4th September 2018, 01:52 Go to last post

  22. Jitter Margin in CPU Timing Closure, up to 80ps, too much? Unrealistic? Unecessary wa

    Started by Mister_hass, 31st August 2018 06:42
    • Replies: 3
    • Views: 311
    Mister_hass
    31st August 2018, 17:27 Go to last post

  23. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 2
    • Views: 196
    kishoresai1996
    31st August 2018, 07:37 Go to last post

  24. Tweaking Vsb to make the transistors to pass weak logics ?

    Started by kaushikrvs, 29th August 2018 21:44
    • Replies: 3
    • Views: 219
    dick_freebird
    30th August 2018, 04:49 Go to last post

  25. Synopsys Design Compiler: Get Path Through Sequential Cells

    Started by thomas.whatsoever, 28th August 2018 19:42
    • Replies: 0
    • Views: 160
    thomas.whatsoever
    28th August 2018, 19:42 Go to last post

  26. what is the usage of the port in the fpga?

    Started by liletian, 28th August 2018 19:12
    • Replies: 1
    • Views: 119
    KlausST
    28th August 2018, 19:20 Go to last post

  27. Timing Checks in primetime

    Started by kishoresai1996, 27th August 2018 10:39
    • Replies: 3
    • Views: 219
    ThisIsNotSam
    28th August 2018, 14:20 Go to last post

  28. How does lowering the voltage makes transitor more leaky?

    Started by kaushikrvs, 25th August 2018 22:32
    • Replies: 4
    • Views: 318
    ThisIsNotSam
    28th August 2018, 14:19 Go to last post

  29. How to find min setup time from DB

    Started by ckdrv, 27th August 2018 18:12
    • Replies: 0
    • Views: 130
    ckdrv
    27th August 2018, 18:12 Go to last post

  30. How do I synthesize an inout port using DC?

    Started by kos8108, 27th August 2018 14:55
    • Replies: 0
    • Views: 82
    kos8108
    27th August 2018, 14:55 Go to last post
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