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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,085
    klug
    25th March 2007, 08:41 Go to last post

  1. In PrimeTime, how can I report_delay_calculation from all input pins to all out pins?

    Started by majd229, Yesterday 22:35
    • Replies: 0
    • Views: 74
    majd229
    Yesterday, 22:35 Go to last post

  2. Output <= registers(to_integer(address)) and intentional meta values

    Started by adrianf0, 18th June 2019 13:55
    • Replies: 11
    • Views: 392
    vyella1
    Yesterday, 18:54 Go to last post

  3. Design compiler synthesis

    Started by vyella1, Yesterday 04:15
    • Replies: 2
    • Views: 75
    vyella1
    Yesterday, 18:49 Go to last post

  4. How to load an already compiled design in Design Compiler?

    Started by asic_architect, 23rd June 2019 08:26
    • Replies: 1
    • Views: 109
    ThisIsNotSam
    23rd June 2019, 15:07 Go to last post

  5. [SOLVED] Synposys Tcyc not observed

    Started by blindscience, 19th June 2019 18:29
    • Replies: 1
    • Views: 138
    blindscience
    21st June 2019, 18:24 Go to last post

  6. Ripple-borrow binary subtraction circuit

    Started by promach, 20th June 2019 08:52
    • Replies: 2
    • Views: 156
    promach
    20th June 2019, 15:55 Go to last post

  7. [Synopsys] ICC1 Multi-thread problem. plz help me.

    Started by sebas.lee, 20th June 2019 04:53
    • Replies: 0
    • Views: 100
    sebas.lee
    20th June 2019, 04:53 Go to last post

  8. How to clock gate in hierarchy?

    Started by DimitrisStathis, 17th June 2019 17:29
    • Replies: 5
    • Views: 219
    ThisIsNotSam
    18th June 2019, 18:06 Go to last post

  9. Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 4
    • Views: 300
    fragnen
    18th June 2019, 09:29 Go to last post

  10. How to get the Number of components before a specific net using Design Compiler?

    Started by qaziarbab, 17th June 2019 10:58
    • Replies: 2
    • Views: 273
    qaziarbab
    18th June 2019, 09:18 Go to last post

  11. Is it possible to assign a value to a signal in a systemverilog assertion?

    Started by iammedjay, 18th June 2019 08:53
    • Replies: 0
    • Views: 77
    iammedjay
    18th June 2019, 08:53 Go to last post

  12. Coverage improvement from AU.TC faults

    Started by aakashaspires, 17th June 2019 08:59
    • Replies: 1
    • Views: 104
    ThisIsNotSam
    17th June 2019, 16:17 Go to last post

  13. meaning of placeable cells

    Started by sharanbr123, 14th June 2019 12:52
    • Replies: 2
    • Views: 181
    sharanbr123
    14th June 2019, 17:23 Go to last post

  14. How to ensure the accuracy of static timing analysis (STA) by using .lib

    Started by fatocean, 13th June 2019 13:13
    • Replies: 1
    • Views: 162
    ThisIsNotSam
    13th June 2019, 14:50 Go to last post

  15. TimeDesign in innovus with value 0 of Shift Phase

    Started by chineselboy, 12th June 2019 03:37
    1 Attachment(s)
    • Replies: 1
    • Views: 177
    ThisIsNotSam
    12th June 2019, 14:16 Go to last post

  16. Fault simulation of leon3mp mismatched with commercial diagnosis tool

    Started by LeoYou, 12th June 2019 09:00
    • Replies: 0
    • Views: 113
    LeoYou
    12th June 2019, 09:00 Go to last post

  17. ATPG Test Coverage for stuck@ and @speed

    Started by sandy2811, 25th March 2019 15:08
    • Replies: 3
    • Views: 334
    xodus_fr
    11th June 2019, 07:16 Go to last post

  18. What is Tranisition Delay and Path Delay Fault models in DFT ATPG?

    Started by Nanda_DFT, 19th February 2019 07:03
    • Replies: 1
    • Views: 218
    xodus_fr
    11th June 2019, 07:07 Go to last post

  19. [moved] Digital Transition Capture

    Started by minhchau, 8th June 2019 16:40
    3 Attachment(s)
    • Replies: 11
    • Views: 581
    summitville
    10th June 2019, 19:40 Go to last post

  20. Delay a signal in a system verilog testbench using jaspergold

    Started by haammzzaa, 10th June 2019 13:29
    • Replies: 4
    • Views: 190
    ThisIsNotSam
    10th June 2019, 16:01 Go to last post

  21. [SOLVED] How to re-synthesize a circuit with ABC synthesizer?

    Started by amin-ea, 25th May 2019 12:06
    • Replies: 5
    • Views: 370
    amin-ea
    10th June 2019, 08:40 Go to last post

  22. [SOLVED] Methodology to calculate the Clock Uncertainity values.

    Started by Wyre, 9th June 2019 10:35
    • Replies: 1
    • Views: 139
    ThisIsNotSam
    9th June 2019, 16:13 Go to last post

  23. Post-layout Simulation Errors in Virtuoso with av_extracted view

    Started by minmin_J, 6th June 2019 18:31
    • Replies: 1
    • Views: 236
    Dominik Przyborowski
    6th June 2019, 19:18 Go to last post

  24. System verilog, fork join_any

    Started by surerdra, 4th June 2019 08:49
    • Replies: 3
    • Views: 317
    surerdra
    5th June 2019, 07:05 Go to last post

  25. Add output signal to reliability analysis virtuoso-cadence

    Started by antlhem, 31st May 2019 12:11
    1 Attachment(s)
    • Replies: 2
    • Views: 258
    antlhem
    3rd June 2019, 15:19 Go to last post

  26. Post synthesis simulation shows setup and hold time violations while DC doesn't

    Started by dormant_bci, 30th May 2019 00:32
    • Replies: 8
    • Views: 777
    ThisIsNotSam
    2nd June 2019, 22:43 Go to last post

  27. [SOLVED] Can you use StarRC to extract a certain subcell and all its connections to topcell?

    Started by majd229, 2nd June 2019 17:14
    • Replies: 1
    • Views: 197
    timof
    2nd June 2019, 21:31 Go to last post

  28. Optimizing case statement with large input

    Started by stanford, 30th May 2019 03:01
    • Replies: 8
    • Views: 732
    asdf44
    1st June 2019, 02:42 Go to last post

  29. if/else vs. if/if in combo logic

    Started by stanford, 30th May 2019 02:09
    • Replies: 10
    • Views: 536
    asdf44
    1st June 2019, 02:39 Go to last post

  30. Overloading Arithmethic operators in Design Compiler

    Started by javierh.santiago, 31st May 2019 17:57
    • Replies: 2
    • Views: 400
    javierh.santiago
    1st June 2019, 01:46 Go to last post
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