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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 36,745
    klug
    25th March 2007, 08:41 Go to last post

  1. Looking for synopsys documentation on their outputs formats used in PrimeTimePX

    Started by tchad, Yesterday 23:25
    • Replies: 0
    • Views: 50
    tchad
    Yesterday, 23:25 Go to last post

  2. DFT 1500 ip module testing

    Started by Varun124, Yesterday 20:32
    • Replies: 0
    • Views: 30
    Varun124
    Yesterday, 20:32 Go to last post

  3. How to trace the original of netlist gates back to the original RTL description

    Started by noureddine-as, 2nd April 2020 16:42
    • Replies: 3
    • Views: 222
    ThisIsNotSam
    Yesterday, 20:30 Go to last post

  4. INTEST, EXTEST and BYPASS modes without wrapper in DFT

    Started by mona_patel, 2nd April 2020 05:54
    • Replies: 4
    • Views: 186
    mona_patel
    2nd April 2020, 10:33 Go to last post

  5. How to estimate power consumption at the IP design level?

    Started by luoyanghero, 27th March 2020 03:38
    • Replies: 4
    • Views: 377
    luoyanghero
    2nd April 2020, 07:35 Go to last post

  6. [SOLVED] DFT DRC - Clock connected to primary output (Design Compiler C17)

    Started by tchisholmuk, 31st March 2020 11:04
    • Replies: 4
    • Views: 253
    tchisholmuk
    1st April 2020, 11:04 Go to last post

  7. SDF file backannotation problem: "Instance X does not have a generic named Y"

    Started by noureddine-as, 31st March 2020 18:52
    • Replies: 0
    • Views: 160
    noureddine-as
    31st March 2020, 18:52 Go to last post

  8. Conflict between two axi masters.

    Started by hcu, 30th March 2020 06:04
    • Replies: 5
    • Views: 321
    hcu
    31st March 2020, 11:21 Go to last post

  9. How to parallel process foreach_in_collection in ICC?

    Started by pradeep5344, 29th March 2020 08:57
    • Replies: 2
    • Views: 226
    pradeep5344
    30th March 2020, 04:08 Go to last post

  10. How to write patterns to multiple files - Cadence ATPG

    Started by srirao, 30th March 2020 01:54
    • Replies: 0
    • Views: 202
    srirao
    30th March 2020, 01:54 Go to last post

  11. How to write a top-level DEF file/hierarchical DEF files

    Started by rhilai, 29th March 2020 11:23
    • Replies: 1
    • Views: 184
    ThisIsNotSam
    29th March 2020, 15:44 Go to last post

  12. UPF for low power design in DC/ICC2

    Started by riti, 24th March 2020 17:55
    • Replies: 3
    • Views: 587
    riti
    27th March 2020, 12:51 Go to last post

  13. [SOLVED] How to evaluate the energy of an arithmetic operation

    Started by noureddine-as, 20th March 2020 14:46
    • Replies: 3
    • Views: 377
    noureddine-as
    26th March 2020, 16:04 Go to last post

  14. Latency and skew of clock tree

    Started by riti, 19th March 2020 17:34
    • Replies: 5
    • Views: 493
    ThisIsNotSam
    21st March 2020, 10:12 Go to last post

  15. [SOLVED] Low power optimization problem in competitive vendor economics ?

    Started by BeckettColt, 19th March 2020 10:31
    • Replies: 2
    • Views: 312
    BeckettColt
    21st March 2020, 06:16 Go to last post

  16. [SOLVED] How to automate the maximum frequency estimation

    Started by noureddine-as, 20th March 2020 03:07
    • Replies: 4
    • Views: 347
    noureddine-as
    20th March 2020, 14:29 Go to last post

  17. Max Overdrive Supply Voltage in SoC 5nmFinFet

    Started by Mister_hass, 19th March 2020 20:53
    • Replies: 3
    • Views: 273
    ThisIsNotSam
    20th March 2020, 08:30 Go to last post

  18. LTspice and Electric – (VLSI) - Simulation error

    Started by lufer17, 14th March 2020 13:54
    2 Attachment(s)
    • Replies: 2
    • Views: 281
    lufer17
    18th March 2020, 12:39 Go to last post

  19. Troubles with TetraMAX test patterns

    Started by TelpDmtr, 11th March 2020 10:59
    7 Attachment(s)
    • Replies: 7
    • Views: 646
    kungchuking
    17th March 2020, 04:47 Go to last post

  20. [SOLVED] How to check un-clocked flops and how to trace the source point for the problem ?

    Started by purushotham.vlsi, 12th March 2020 10:51
    • Replies: 12
    • Views: 808
    FvM
    15th March 2020, 12:33 Go to last post

  21. PrimeTime provides different Power analysis results for FSDB vs. VCD files

    Started by noureddine-as, 13th March 2020 17:10
    • Replies: 0
    • Views: 238
    noureddine-as
    13th March 2020, 17:10 Go to last post

  22. two test case clock gating check circuit & clock divide generation circiut

    Started by kumarprakash1980, 13th March 2020 14:21
    • Replies: 1
    • Views: 170
    dpaul
    13th March 2020, 14:47 Go to last post

  23. Regarding synthesis of HDLs

    Started by garvind25, 26th December 2019 10:33
    • Replies: 5
    • Views: 911
    uditkumar1983
    12th March 2020, 10:40 Go to last post

  24. [SOLVED] CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 3
    • Views: 742
    uditkumar1983
    12th March 2020, 10:33 Go to last post

  25. Best Books for Learning Synopsys ASIC Tools and Cadence ASIC Tools

    Started by Puppet123, 12th March 2020 07:07
    • Replies: 1
    • Views: 259
    dpaul
    12th March 2020, 10:11 Go to last post

  26. Finding an IP Power Analysis Tool

    Started by luoyanghero, 3rd March 2020 03:02
    • Replies: 3
    • Views: 344
    uditkumar1983
    12th March 2020, 10:05 Go to last post

  27. Electric VLSI Design System - SEQUENTIAL COMMAND

    Started by lufer17, 12th March 2020 02:01
    • Replies: 0
    • Views: 324
    lufer17
    12th March 2020, 02:01 Go to last post

  28. Verdi GUI addsignal command line option

    Started by sandeepj, 7th March 2020 16:51
    3 Attachment(s)
    • Replies: 1
    • Views: 275
    kungchuking
    10th March 2020, 14:01 Go to last post

  29. RTL design (system/Verilog) for Linked list with buffer/SRAM storage

    Started by sandeepj, 7th March 2020 17:01
    • Replies: 0
    • Views: 487
    sandeepj
    7th March 2020, 17:01 Go to last post

  30. Results for hierarchical LVS

    Started by aditya1579, 4th March 2020 12:54
    • Replies: 1
    • Views: 306
    Prashanthanilm
    7th March 2020, 11:16 Go to last post
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