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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 36,713
    25th March 2007, 08:41 Go to last post
    • Replies: 3
    • Views: 293
    Yesterday, 14:08 Go to last post
  1. Conflict between two axi masters.

    Started by hcu, 30th March 2020 06:04
    • Replies: 5
    • Views: 263
    Yesterday, 11:21 Go to last post
    • Replies: 2
    • Views: 198
    30th March 2020, 04:08 Go to last post
  2. How to write patterns to multiple files - Cadence ATPG

    Started by srirao, 30th March 2020 01:54
    • Replies: 0
    • Views: 175
    30th March 2020, 01:54 Go to last post
    • Replies: 1
    • Views: 154
    29th March 2020, 15:44 Go to last post
  3. UPF for low power design in DC/ICC2

    Started by riti, 24th March 2020 17:55
    • Replies: 3
    • Views: 569
    27th March 2020, 12:51 Go to last post
  4. [SOLVED] How to evaluate the energy of an arithmetic operation

    Started by noureddine-as, 20th March 2020 14:46
    • Replies: 3
    • Views: 363
    26th March 2020, 16:04 Go to last post
  5. Latency and skew of clock tree

    Started by riti, 19th March 2020 17:34
    • Replies: 5
    • Views: 482
    21st March 2020, 10:12 Go to last post
    • Replies: 2
    • Views: 301
    21st March 2020, 06:16 Go to last post
  6. [SOLVED] How to automate the maximum frequency estimation

    Started by noureddine-as, 20th March 2020 03:07
    • Replies: 4
    • Views: 337
    20th March 2020, 14:29 Go to last post
  7. Max Overdrive Supply Voltage in SoC 5nmFinFet

    Started by Mister_hass, 19th March 2020 20:53
    • Replies: 3
    • Views: 265
    20th March 2020, 08:30 Go to last post
  8. LTspice and Electric – (VLSI) - Simulation error

    Started by lufer17, 14th March 2020 13:54
    • Replies: 2
    • Views: 275
    18th March 2020, 12:39 Go to last post
  9. Troubles with TetraMAX test patterns

    Started by TelpDmtr, 11th March 2020 10:59
    • Replies: 7
    • Views: 629
    17th March 2020, 04:47 Go to last post
    • Replies: 12
    • Views: 785
    15th March 2020, 12:33 Go to last post
  10. Regarding synthesis of HDLs

    Started by garvind25, 26th December 2019 10:33
    • Replies: 5
    • Views: 904
    12th March 2020, 10:40 Go to last post
  11. [SOLVED] CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 3
    • Views: 740
    12th March 2020, 10:33 Go to last post
    • Replies: 1
    • Views: 255
    12th March 2020, 10:11 Go to last post
  12. Finding an IP Power Analysis Tool

    Started by luoyanghero, 3rd March 2020 03:02
    • Replies: 3
    • Views: 340
    12th March 2020, 10:05 Go to last post
  13. Electric VLSI Design System - SEQUENTIAL COMMAND

    Started by lufer17, 12th March 2020 02:01
    • Replies: 0
    • Views: 307
    12th March 2020, 02:01 Go to last post
  14. Verdi GUI addsignal command line option

    Started by sandeepj, 7th March 2020 16:51
    • Replies: 1
    • Views: 271
    10th March 2020, 14:01 Go to last post
    • Replies: 0
    • Views: 482
    7th March 2020, 17:01 Go to last post
  15. Results for hierarchical LVS

    Started by aditya1579, 4th March 2020 12:54
    • Replies: 1
    • Views: 301
    7th March 2020, 11:16 Go to last post
    • Replies: 2
    • Views: 345
    6th March 2020, 09:17 Go to last post
  16. Capacitacne tables in UMC 130nm

    Started by shlooky, 3rd March 2020 18:18
    • Replies: 3
    • Views: 365
    4th March 2020, 09:07 Go to last post
    • Replies: 4
    • Views: 549
    29th February 2020, 15:53 Go to last post