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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,329
    klug
    25th March 2007, 08:41 Go to last post

  1. [SOLVED] FSM output function of the encoded states

    Started by carmeloA, Yesterday 12:03
    • Replies: 2
    • Views: 162
    carmeloA
    Today, 09:22 Go to last post

  2. modelsim simulation after syntesis

    Started by carmeloA, Today 09:15
    • Replies: 0
    • Views: 18
    carmeloA
    Today, 09:15 Go to last post

  3. Variable in Design Compiler for clock gating

    Started by aditya1579, 22nd June 2018 10:57
    • Replies: 4
    • Views: 193
    oratie
    23rd June 2018, 18:24 Go to last post

  4. is it correct to have filler cells being overlapped in floorplan b/w core and die

    Started by Pravesh_Rathee, 19th June 2018 20:59
    3 Attachment(s)
    • Replies: 7
    • Views: 412
    Pravesh_Rathee
    22nd June 2018, 12:23 Go to last post

  5. Clock slew and data slew

    Started by sjt1003, 22nd June 2018 05:52
    • Replies: 0
    • Views: 71
    sjt1003
    22nd June 2018, 05:52 Go to last post

  6. Vcd to saif conversion

    Started by Swethav, 21st June 2018 12:14
    • Replies: 3
    • Views: 126
    ThisIsNotSam
    21st June 2018, 14:48 Go to last post

  7. [SOLVED] Common POLY layer in the digital standard cells

    Started by ua6bqg, 19th June 2018 18:23
    1 Attachment(s)
    • Replies: 7
    • Views: 132
    ThisIsNotSam
    20th June 2018, 15:03 Go to last post

  8. Script for adding wires in Encounter

    Started by Mahmoud_Dagher, 19th June 2018 03:10
    • Replies: 4
    • Views: 109
    ThisIsNotSam
    20th June 2018, 14:50 Go to last post

  9. Non clock cells on clock path

    Started by stanford, 18th June 2018 23:01
    • Replies: 4
    • Views: 141
    ThisIsNotSam
    20th June 2018, 14:42 Go to last post

  10. Undefined Packets when importing a gds from Encounter to Cadence Virtuoso

    Started by Mahmoud_Dagher, 18th June 2018 22:55
    • Replies: 1
    • Views: 76
    ThisIsNotSam
    19th June 2018, 19:08 Go to last post

  11. Synopsys VP Virtualizer installation

    Started by yuhiub90, 19th June 2018 09:09
    • Replies: 0
    • Views: 61
    yuhiub90
    19th June 2018, 09:09 Go to last post

  12. async fifo - almost full/empty

    Started by stanford, 10th June 2018 08:24
    • Replies: 6
    • Views: 281
    KlausST
    19th June 2018, 00:53 Go to last post

  13. I need a driver (ANSI C99) or design manual for the NCR53c94...

    Started by e-music, 19th June 2018 00:33
    • Replies: 0
    • Views: 61
    e-music
    19th June 2018, 00:33 Go to last post

  14. How to use ICC2 to merge 2 LEFs into 1 monolithic LEF?

    Started by majd229, 18th June 2018 17:44
    • Replies: 2
    • Views: 88
    majd229
    18th June 2018, 22:42 Go to last post

  15. Memory/macro internal clock insertion delay

    Started by argha, 16th June 2018 20:12
    • Replies: 1
    • Views: 169
    ThisIsNotSam
    18th June 2018, 14:17 Go to last post

  16. Import a layout from Encounter to Virtuoso

    Started by Mahmoud_Dagher, 14th June 2018 14:53
    • Replies: 5
    • Views: 238
    ThisIsNotSam
    18th June 2018, 14:15 Go to last post

  17. Plotting the transient noise distribution in virtuoso

    Started by romanb, 17th June 2018 19:27
    • Replies: 1
    • Views: 103
    jjx
    18th June 2018, 10:16 Go to last post

  18. When is data captured and data launched in SPI transmission?

    Started by kaushikrvs, 15th June 2018 13:04
    • Replies: 2
    • Views: 172
    ads-ee
    15th June 2018, 15:36 Go to last post

  19. SPI Slave with strange behavior

    Started by rmachado, 9th June 2018 13:59
    2 Pages •
    1 2
    9 Attachment(s)
    • Replies: 25
    • Views: 618
    rmachado
    15th June 2018, 10:57 Go to last post

  20. SDC constraints for asynchronous reset

    Started by Alexxk, 14th June 2018 12:04
    • Replies: 2
    • Views: 130
    slutarius
    15th June 2018, 10:36 Go to last post

  21. Timing Sign off from Primetime

    Started by sreejinair, 11th June 2018 14:38
    • Replies: 4
    • Views: 299
    sreejinair
    12th June 2018, 15:33 Go to last post

  22. What happens when the width is too large for the length of the MOSFET?

    Started by littlerock, 5th June 2018 09:41
    • Replies: 4
    • Views: 344
    frankrose
    9th June 2018, 17:56 Go to last post

  23. UMC 65nm without TLU+ files

    Started by ua6bqg, 8th June 2018 16:30
    • Replies: 1
    • Views: 144
    ThisIsNotSam
    8th June 2018, 18:00 Go to last post

  24. [moved] Physical design placement timing issue

    Started by prabhu14, 7th June 2018 19:05
    • Replies: 2
    • Views: 193
    ThisIsNotSam
    8th June 2018, 14:54 Go to last post

  25. Cadence lint error: CLKDMN

    Started by Sam26, 7th June 2018 10:45
    • Replies: 3
    • Views: 209
    Sam26
    8th June 2018, 12:37 Go to last post

  26. [moved] 50Mz to 1 kHz clock generator

    Started by sanjaysharmaiitk, 8th June 2018 09:26
    3 Attachment(s)
    • Replies: 1
    • Views: 149
    KlausST
    8th June 2018, 10:14 Go to last post

  27. Cell Characterization Determining Slew vs Capacitive Values for Templates

    Started by ranaya, 23rd May 2018 19:20
    • Replies: 6
    • Views: 380
    ThisIsNotSam
    7th June 2018, 14:35 Go to last post

  28. Cadence Encounter place and route - Pins not covered by metal layer

    Started by NikosTS, 7th May 2018 10:01
    • Replies: 10
    • Views: 554
    jackoup
    4th June 2018, 11:41 Go to last post

  29. Program Error:unhandled pattern type while reading external VCDE pattern in TetraMax

    Started by edab_johnhsu, 4th June 2018 07:56
    • Replies: 0
    • Views: 278
    edab_johnhsu
    4th June 2018, 07:56 Go to last post

  30. bit width for addition

    Started by sky_above, 2nd June 2018 14:04
    • Replies: 3
    • Views: 243
    vGoodtimes
    3rd June 2018, 22:22 Go to last post
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