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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,263
    klug
    25th March 2007, 08:41 Go to last post

  1. licensing calibre problem

    Started by abdoboua, Yesterday 21:45
    • Replies: 0
    • Views: 31
    abdoboua
    Yesterday, 21:45 Go to last post

  2. Input & output delay in mixed signal chip - RTL Signal Integrity

    Started by The_Dutchman, 14th July 2019 09:46
    1 Attachment(s)
    • Replies: 3
    • Views: 154
    ThisIsNotSam
    Yesterday, 18:55 Go to last post

  3. Tech library problem

    Started by abdoboua, Yesterday 12:15
    4 Attachment(s)
    • Replies: 3
    • Views: 86
    ThisIsNotSam
    Yesterday, 18:49 Go to last post

  4. What is the difference of power estimation between Design Compiler and PrimeTIme PX

    Started by kkpark, Yesterday 06:34
    • Replies: 4
    • Views: 120
    ThisIsNotSam
    Yesterday, 17:30 Go to last post

  5. [m]What is the difference between "Damascene copper" interconnect and normal copper ?

    Started by RohithRaj, Yesterday 13:22
    • Replies: 1
    • Views: 78
    ThisIsNotSam
    Yesterday, 17:24 Go to last post

  6. Help needed for spice conversion from mdl syntax

    Started by smurtuzah, Yesterday 13:29
    • Replies: 0
    • Views: 53
    smurtuzah
    Yesterday, 13:29 Go to last post

  7. DRC problem with layout in cadence 617

    Started by abdoboua, 8th July 2019 19:05
    • Replies: 1
    • Views: 128
    jbeniston
    Yesterday, 11:35 Go to last post

  8. How do I know inbetween which pins do arcs exist in PrimeTime for timing libs?

    Started by majd229, 15th July 2019 20:40
    • Replies: 1
    • Views: 81
    oratie
    Yesterday, 06:14 Go to last post

  9. Problem when installing Calibre

    Started by abdoboua, 10th July 2019 20:35
    • Replies: 1
    • Views: 114
    slizak
    15th July 2019, 16:22 Go to last post

  10. ModelSim simulation error

    Started by garvind25, 11th July 2019 10:42
    3 Attachment(s)
    • Replies: 11
    • Views: 372
    ads-ee
    15th July 2019, 15:59 Go to last post

  11. Cannot find vdd in the design

    Started by kartikpujari, 14th July 2019 05:25
    • Replies: 2
    • Views: 163
    dick_freebird
    14th July 2019, 19:44 Go to last post

  12. Shadow path causing parallel simulation to fail. Serial is passing.

    Started by finsiherfish, 22nd March 2019 16:36
    • Replies: 1
    • Views: 287
    CHIRU777
    14th July 2019, 18:48 Go to last post

  13. Is it possible to assign a value to a signal in a systemverilog assertion?

    Started by iammedjay, 18th June 2019 08:53
    • Replies: 3
    • Views: 207
    andre_teprom
    14th July 2019, 01:44 Go to last post

  14. Systemverilog type cast or integer division

    Started by parafux, 10th July 2019 13:51
    • Replies: 2
    • Views: 174
    kripacharya
    13th July 2019, 18:53 Go to last post

  15. Global Buffer Access Normalized Energy Cost

    Started by moa375, 12th July 2019 21:51
    • Replies: 0
    • Views: 133
    moa375
    12th July 2019, 21:51 Go to last post

  16. What do you mean by Predictive FIFO?

    Started by rameshbabur, 11th July 2019 08:01
    • Replies: 2
    • Views: 208
    kripacharya
    12th July 2019, 19:01 Go to last post

  17. 32 bit left shift of a longint variable does not work

    Started by parafux, 11th July 2019 06:23
    • Replies: 2
    • Views: 182
    kripacharya
    12th July 2019, 18:46 Go to last post

  18. Facing issue of long runtime to find a legal location for cell , in clock opt stage

    Started by reddvoid, 12th July 2019 07:03
    • Replies: 1
    • Views: 140
    ThisIsNotSam
    12th July 2019, 16:48 Go to last post

  19. Digital design of a GPU

    Started by adwnis123, 11th July 2019 14:06
    • Replies: 3
    • Views: 262
    asdf44
    12th July 2019, 14:00 Go to last post

  20. Saving the layout in innovus

    Started by Chinmaye, 10th July 2019 11:45
    4 Attachment(s)
    • Replies: 7
    • Views: 293
    ThisIsNotSam
    11th July 2019, 17:44 Go to last post

  21. How do I decide clock period constrain for Synthesis in DC?

    Started by asic_architect, 10th July 2019 03:20
    • Replies: 3
    • Views: 217
    ThisIsNotSam
    10th July 2019, 21:41 Go to last post

  22. [SOLVED] Error during clock tree synthesis in innovus

    Started by Chinmaye, 10th July 2019 10:51
    • Replies: 1
    • Views: 109
    Chinmaye
    10th July 2019, 17:34 Go to last post

  23. pins of symbol and layout do not match

    Started by abdoboua, 9th July 2019 12:01
    8 Attachment(s)
    • Replies: 4
    • Views: 178
    abdoboua
    9th July 2019, 21:59 Go to last post

  24. Help in understanding innovus

    Started by Chinmaye, 5th July 2019 06:56
    1 Attachment(s)
    • Replies: 5
    • Views: 412
    ThisIsNotSam
    9th July 2019, 14:30 Go to last post

  25. Effect of adding an BUF/INV in physical Design on LEC

    Started by gauravgautam, 8th July 2019 10:03
    • Replies: 2
    • Views: 133
    ThisIsNotSam
    8th July 2019, 15:51 Go to last post

  26. Clock Buffer Questions

    Started by promach, 8th July 2019 15:26
    3 Attachment(s)
    • Replies: 0
    • Views: 127
    promach
    8th July 2019, 15:26 Go to last post

  27. problem when zooming to see layers

    Started by abdoboua, 5th July 2019 11:23
    15 Attachment(s)
    • Replies: 7
    • Views: 376
    abdoboua
    8th July 2019, 14:11 Go to last post

  28. Obtaining D flip-flop mosfet-level schematics from CMOS layout

    Started by promach, 5th July 2019 17:01
    1 Attachment(s)
    • Replies: 6
    • Views: 441
    promach
    7th July 2019, 14:35 Go to last post

  29. Getting an error in icc2_shell. Need help

    Started by nitheeshm, 6th July 2019 21:57
    • Replies: 0
    • Views: 182
    nitheeshm
    6th July 2019, 21:57 Go to last post

  30. [SOLVED] Timing slack showing Unconstrained after synthesis in genus

    Started by Chinmaye, 4th July 2019 08:37
    2 Attachment(s)
    • Replies: 5
    • Views: 285
    ThisIsNotSam
    5th July 2019, 14:08 Go to last post
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