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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,405
    25th March 2007, 08:41 Go to last post
  1. Create Block in innovus to use on other designs

    Started by rmachado, 4th July 2018 17:43
    • Replies: 3
    • Views: 132
    Today, 09:53 Go to last post
    • Replies: 4
    • Views: 149
    Yesterday, 19:05 Go to last post
  2. Explain tech file name rule

    Started by faunusest, Yesterday 04:02
    • Replies: 1
    • Views: 77
    Yesterday, 14:12 Go to last post
  3. latency of the dsync output

    Started by stanford, 11th July 2018 19:58
    • Replies: 9
    • Views: 289
    17th July 2018, 19:30 Go to last post
  4. X propagation on input when else is not there

    Started by stanford, 12th July 2018 23:00
    • Replies: 8
    • Views: 291
    17th July 2018, 19:24 Go to last post
  5. lw, sw in a processor

    Started by stanford, 16th July 2018 06:14
    • Replies: 3
    • Views: 181
    17th July 2018, 19:17 Go to last post
  6. TCL Script for adding wires on SoC Encounter

    Started by Mahmoud_Dagher, 17th July 2018 14:49
    • Replies: 0
    • Views: 59
    17th July 2018, 14:49 Go to last post
  7. Comparing two numbers

    Started by Pravesh_Rathee, 11th July 2018 17:54
    • Replies: 12
    • Views: 308
    13th July 2018, 20:29 Go to last post
  8. [SOLVED] Regarding placement legalization in cadence

    Started by pavan muvvala, 12th July 2018 07:45
    • Replies: 3
    • Views: 131
    13th July 2018, 19:47 Go to last post
  9. Parallel Pattern Simulation

    Started by sandy2811, 3rd July 2018 18:28
    • Replies: 4
    • Views: 211
    13th July 2018, 11:39 Go to last post
    • Replies: 0
    • Views: 63
    13th July 2018, 08:43 Go to last post
    • Replies: 2
    • Views: 126
    12th July 2018, 09:27 Go to last post
  10. fifo memory initialization

    Started by stanford, 6th July 2018 23:28
    • Replies: 3
    • Views: 306
    7th July 2018, 20:59 Go to last post
    • Replies: 2
    • Views: 162
    6th July 2018, 01:34 Go to last post
  11. Manual Intentional Routing

    Started by Mahmoud_Dagher, 3rd July 2018 20:01
    • Replies: 5
    • Views: 234
    5th July 2018, 14:12 Go to last post
    • Replies: 1
    • Views: 106
    4th July 2018, 16:51 Go to last post
    • Replies: 4
    • Views: 237
    3rd July 2018, 17:05 Go to last post
  12. Recovery and removal time of async reset

    Started by stanford, 29th June 2018 09:32
    • Replies: 3
    • Views: 231
    2nd July 2018, 22:26 Go to last post
  13. Variable in Design Compiler for clock gating

    Started by aditya1579, 22nd June 2018 10:57
    • Replies: 9
    • Views: 566
    29th June 2018, 15:58 Go to last post
    • Replies: 0
    • Views: 148
    28th June 2018, 21:52 Go to last post
  14. [SOLVED] Layout filemerge problem

    Started by Mahmoud_Dagher, 28th June 2018 14:18
    • Replies: 1
    • Views: 153
    28th June 2018, 16:10 Go to last post
  15. Script for adding wires in Encounter

    Started by Mahmoud_Dagher, 19th June 2018 03:10
    • Replies: 5
    • Views: 279
    28th June 2018, 12:11 Go to last post
  16. TSMC and spice model of library cells

    Started by nka, 27th June 2018 01:27
    • Replies: 5
    • Views: 310
    27th June 2018, 20:18 Go to last post