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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 36,787
    25th March 2007, 08:41 Go to last post
    • Replies: 0
    • Views: 41
    Yesterday, 21:59 Go to last post
  1. How to add PTM libraries in Tanner EDA

    Started by iamshahidrana, 4th April 2020 12:07
    • Replies: 1
    • Views: 192
    6th April 2020, 20:41 Go to last post
  2. Reset Value using a parameter

    Started by stanford, 4th April 2020 06:57
    • Replies: 6
    • Views: 278
    5th April 2020, 15:58 Go to last post
    • Replies: 5
    • Views: 317
    4th April 2020, 08:35 Go to last post
  3. Formality script (RTL vs netlist)

    Started by hcu, 4th April 2020 08:04
    • Replies: 0
    • Views: 111
    4th April 2020, 08:04 Go to last post
  4. DFT 1500 IP module testing

    Started by Varun124, 3rd April 2020 20:32
    • Replies: 0
    • Views: 111
    3rd April 2020, 20:32 Go to last post
    • Replies: 4
    • Views: 433
    2nd April 2020, 07:35 Go to last post
    • Replies: 4
    • Views: 299
    1st April 2020, 11:04 Go to last post
  5. Conflict between two axi masters.

    Started by hcu, 30th March 2020 06:04
    • Replies: 5
    • Views: 379
    31st March 2020, 11:21 Go to last post
    • Replies: 2
    • Views: 258
    30th March 2020, 04:08 Go to last post
  6. How to write patterns to multiple files - Cadence ATPG

    Started by srirao, 30th March 2020 01:54
    • Replies: 0
    • Views: 219
    30th March 2020, 01:54 Go to last post
    • Replies: 1
    • Views: 202
    29th March 2020, 15:44 Go to last post
  7. UPF for low power design in DC/ICC2

    Started by riti, 24th March 2020 17:55
    • Replies: 3
    • Views: 616
    27th March 2020, 12:51 Go to last post
  8. [SOLVED] How to evaluate the energy of an arithmetic operation

    Started by noureddine-as, 20th March 2020 14:46
    • Replies: 3
    • Views: 401
    26th March 2020, 16:04 Go to last post
  9. Latency and skew of clock tree

    Started by riti, 19th March 2020 17:34
    • Replies: 5
    • Views: 524
    21st March 2020, 10:12 Go to last post
    • Replies: 2
    • Views: 335
    21st March 2020, 06:16 Go to last post
  10. [SOLVED] How to automate the maximum frequency estimation

    Started by noureddine-as, 20th March 2020 03:07
    • Replies: 4
    • Views: 367
    20th March 2020, 14:29 Go to last post
  11. Max Overdrive Supply Voltage in SoC 5nmFinFet

    Started by Mister_hass, 19th March 2020 20:53
    • Replies: 3
    • Views: 290
    20th March 2020, 08:30 Go to last post
  12. LTspice and Electric – (VLSI) - Simulation error

    Started by lufer17, 14th March 2020 13:54
    • Replies: 2
    • Views: 293
    18th March 2020, 12:39 Go to last post
  13. Troubles with TetraMAX test patterns

    Started by TelpDmtr, 11th March 2020 10:59
    • Replies: 7
    • Views: 677
    17th March 2020, 04:47 Go to last post
    • Replies: 12
    • Views: 855
    15th March 2020, 12:33 Go to last post
  14. Regarding synthesis of HDLs

    Started by garvind25, 26th December 2019 10:33
    • Replies: 5
    • Views: 933
    12th March 2020, 10:40 Go to last post
  15. [SOLVED] CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 3
    • Views: 761
    12th March 2020, 10:33 Go to last post
    • Replies: 1
    • Views: 272
    12th March 2020, 10:11 Go to last post
  16. Finding an IP Power Analysis Tool

    Started by luoyanghero, 3rd March 2020 03:02
    • Replies: 3
    • Views: 361
    12th March 2020, 10:05 Go to last post