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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,500
    klug
    25th March 2007, 08:41 Go to last post

  1. How to let multiple OCC created clocks driving registers become single scan chain ?

    Started by ronald66, 14th December 2019 05:42
    1 Attachment(s)
    • Replies: 0
    • Views: 135
    ronald66
    14th December 2019, 05:42 Go to last post

  2. Synopsys cell Library "lec25dscc25_TT" required.

    Started by qaziarbab, 12th December 2019 12:01
    • Replies: 2
    • Views: 240
    qaziarbab
    13th December 2019, 12:04 Go to last post

  3. How to view assertion pass/fail/vacuous pass status in Questa?

    Started by atanuxplore, 13th December 2019 10:01
    • Replies: 0
    • Views: 86
    atanuxplore
    13th December 2019, 10:01 Go to last post

  4. Boundary Cell in Core Chip

    Started by akhil_psm, 9th December 2019 17:50
    • Replies: 1
    • Views: 248
    ThisIsNotSam
    10th December 2019, 08:24 Go to last post

  5. [SOLVED] Metastabilty and data loss

    Started by sherline123, 5th December 2019 15:58
    • Replies: 12
    • Views: 621
    sherline123
    9th December 2019, 15:12 Go to last post

  6. Can not run simv after compile Verilog project by VCS

    Started by nmphus, 7th December 2019 11:44
    • Replies: 0
    • Views: 225
    nmphus
    7th December 2019, 11:44 Go to last post

  7. How hold violation caused by below mentioned Scenceio

    Started by Varun124, 6th December 2019 14:06
    • Replies: 1
    • Views: 190
    barry
    6th December 2019, 20:21 Go to last post

  8. Sequential ATPG errors that dont go away because of hardware metal faults

    Started by firewireblue, 6th December 2019 14:40
    • Replies: 1
    • Views: 224
    ThisIsNotSam
    6th December 2019, 16:13 Go to last post

  9. Timing ARC for Asynchronous Signal

    Started by Varun124, 4th December 2019 21:09
    • Replies: 3
    • Views: 315
    ThisIsNotSam
    6th December 2019, 09:26 Go to last post

  10. Getting connectivity information from fsdb file

    Started by tomer, 5th December 2019 09:26
    • Replies: 1
    • Views: 202
    ThisIsNotSam
    5th December 2019, 12:39 Go to last post

  11. [SOLVED] Why remove scan chain before the placement?

    Started by akhil_psm, 2nd December 2019 17:42
    • Replies: 3
    • Views: 307
    ThisIsNotSam
    4th December 2019, 08:11 Go to last post

  12. Creating Power ring around macros

    Started by blue1, 3rd December 2019 09:05
    • Replies: 1
    • Views: 140
    ThisIsNotSam
    3rd December 2019, 10:58 Go to last post

  13. MBIST DONE & GO failing conditions

    Started by vipul982, 6th November 2019 14:13
    • Replies: 2
    • Views: 395
    shopping90
    3rd December 2019, 09:29 Go to last post

  14. Leakge current in low Vt cells

    Started by riti, 2nd December 2019 21:06
    • Replies: 2
    • Views: 244
    ThisIsNotSam
    3rd December 2019, 08:06 Go to last post

  15. ATPG stuff, tell me what you think

    Started by firewireblue, 30th November 2019 00:04
    • Replies: 3
    • Views: 320
    ThisIsNotSam
    2nd December 2019, 10:19 Go to last post

  16. Low power optimization problem in competitive vendor economics

    Started by firewireblue, 30th November 2019 12:49
    • Replies: 2
    • Views: 300
    ThisIsNotSam
    2nd December 2019, 10:17 Go to last post

  17. is there any relation between IR drop and Noise Margin ?

    Started by akhil_psm, 1st December 2019 10:38
    • Replies: 2
    • Views: 556
    ThisIsNotSam
    2nd December 2019, 10:15 Go to last post

  18. DDR4 SDRAM test signal is abnormal

    Started by williamli186, 27th November 2019 12:03
    2 Attachment(s)
    • Replies: 0
    • Views: 270
    williamli186
    27th November 2019, 12:03 Go to last post

  19. Use of Cascaded Dividers in the Design

    Started by Varun124, 27th November 2019 06:57
    • Replies: 0
    • Views: 370
    Varun124
    27th November 2019, 06:57 Go to last post

  20. Using a BFM in system verification code.

    Started by dipk11, 15th November 2019 07:49
    • Replies: 7
    • Views: 655
    dipk11
    26th November 2019, 07:34 Go to last post

  21. Clock divider circuit

    Started by promach, 24th November 2019 05:39
    • Replies: 2
    • Views: 416
    ThisIsNotSam
    25th November 2019, 12:04 Go to last post

  22. How power switches are connected to standard cells in design?

    Started by riti, 23rd November 2019 18:29
    • Replies: 1
    • Views: 292
    ThisIsNotSam
    25th November 2019, 08:44 Go to last post

  23. Why CTS in physical design?

    Started by Dan_Yang, 24th November 2019 16:09
    • Replies: 1
    • Views: 301
    ThisIsNotSam
    25th November 2019, 08:43 Go to last post

  24. Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    Started by daskk62, 21st November 2019 19:13
    • Replies: 5
    • Views: 542
    dpaul
    22nd November 2019, 10:18 Go to last post

  25. [moved] How to detect the faulty flop in scan chain

    Started by Sunilverma03, 21st November 2019 05:33
    • Replies: 0
    • Views: 240
    Sunilverma03
    21st November 2019, 05:33 Go to last post

  26. SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre

    Started by Puppet123, 20th November 2019 21:35
    • Replies: 2
    • Views: 315
    Puppet123
    21st November 2019, 03:36 Go to last post

  27. Tool inserted DFT lockup latch is not transparent in functional mode (no test port)

    Started by Ashish Agrawal, 14th November 2019 18:32
    • Replies: 2
    • Views: 319
    Sunilverma03
    20th November 2019, 13:08 Go to last post

  28. SystemVerilog Interface signal assignment

    Started by ghertz, 18th November 2019 17:30
    • Replies: 2
    • Views: 276
    ghertz
    18th November 2019, 23:46 Go to last post

  29. asynchronous D Flip flop with negative edge triggered clk,set and reset

    Started by Knowledge.seeker, 18th November 2019 11:11
    • Replies: 2
    • Views: 290
    dick_freebird
    18th November 2019, 23:09 Go to last post

  30. DFT Visualizer Data View

    Started by Vignesh_J, 15th November 2019 13:24
    • Replies: 2
    • Views: 361
    Vignesh_J
    18th November 2019, 08:03 Go to last post
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