1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    115,989
Page 1 of 809 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24243

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,112
    klug
    25th March 2007, 08:41 Go to last post

  1. Post layout delay in cadence

    Started by umaizameh, 14th February 2019 06:53
    • Replies: 5
    • Views: 220
    oratie
    Yesterday, 07:34 Go to last post

  2. How to Dump e-vcd File in Verilog HDL ?

    Started by sreejeesh_sreedharan, 14th February 2019 08:28
    • Replies: 2
    • Views: 104
    ThisIsNotSam
    14th February 2019, 16:39 Go to last post

  3. Sample files needed for working with Automatic PnR

    Started by LostEagle, 14th February 2019 00:17
    • Replies: 1
    • Views: 87
    ThisIsNotSam
    14th February 2019, 02:05 Go to last post

  4. Timing issues in netlist simualtion - SDF simulation of IP block

    Started by manpmanp, 11th February 2019 16:27
    1 Attachment(s)
    • Replies: 4
    • Views: 161
    manpmanp
    13th February 2019, 09:34 Go to last post

  5. Using SPEF files for STA in INNOVUS

    Started by Windywast, 12th February 2019 01:37
    • Replies: 3
    • Views: 158
    ThisIsNotSam
    12th February 2019, 17:49 Go to last post

  6. Help to synthesize floating point MAC in Design Compiler using DesignWare library.

    Started by DreamCaCao, 7th February 2019 06:25
    • Replies: 4
    • Views: 282
    ckqee
    11th February 2019, 19:41 Go to last post

  7. What does it mean to have a sequential encoding scheme to enumerate states?

    Started by MightyFunkster, 11th February 2019 17:03
    • Replies: 1
    • Views: 81
    ads-ee
    11th February 2019, 17:19 Go to last post

  8. synthesized netlists simulation issue

    Started by manpmanp, 7th February 2019 17:42
    1 Attachment(s)
    • Replies: 6
    • Views: 208
    ThisIsNotSam
    11th February 2019, 16:19 Go to last post

  9. DFT issues on scan clock input as "x"

    Started by skyworld_cy, 9th February 2019 10:08
    1 Attachment(s)
    • Replies: 5
    • Views: 273
    ThisIsNotSam
    10th February 2019, 03:47 Go to last post

  10. How do you simulate a mixed-signal system?

    Started by blacki, 8th February 2019 17:22
    1 Attachment(s)
    • Replies: 2
    • Views: 119
    BradtheRad
    9th February 2019, 05:40 Go to last post

  11. What's the difference between creating ndm using oas and lef

    Started by Studentofknowledge, 8th February 2019 17:37
    • Replies: 1
    • Views: 75
    ThisIsNotSam
    8th February 2019, 18:46 Go to last post

  12. MCR - Metal Cap Reduction

    Started by Studentofknowledge, 8th February 2019 17:44
    • Replies: 1
    • Views: 73
    KlausST
    8th February 2019, 18:11 Go to last post

  13. Have you ever done timing simulation with ARM standard cell library ?

    Started by Yongchan, 8th February 2019 02:15
    • Replies: 0
    • Views: 111
    Yongchan
    8th February 2019, 02:15 Go to last post

  14. Automatize simulations in Modelsim

    Started by javierh.santiago, 5th February 2019 22:44
    • Replies: 2
    • Views: 265
    dave_59
    8th February 2019, 00:12 Go to last post

  15. what are the inputs and outputs for floorplanning?

    Started by lh-, 3rd February 2019 18:28
    1 Attachment(s)
    • Replies: 8
    • Views: 369
    lh-
    7th February 2019, 19:42 Go to last post

  16. Digital filter projects

    Started by blacki, 6th February 2019 04:53
    • Replies: 7
    • Views: 272
    dpaul
    7th February 2019, 14:16 Go to last post

  17. finFET's behavior with Temperature

    Started by Wyre, 6th February 2019 10:28
    • Replies: 1
    • Views: 202
    ThisIsNotSam
    7th February 2019, 02:58 Go to last post

  18. Clarification about how to create the VCD files with Modelsim

    Started by javierh.santiago, 5th February 2019 23:12
    • Replies: 4
    • Views: 194
    ThisIsNotSam
    6th February 2019, 04:38 Go to last post

  19. Report detailed area in Design Compiler/ Cadence Innovus

    Started by oAwad, 6th February 2019 02:24
    • Replies: 1
    • Views: 119
    ThisIsNotSam
    6th February 2019, 04:36 Go to last post

  20. Optimize shifter synthesis in Design Compiler

    Started by oAwad, 2nd February 2019 22:19
    • Replies: 3
    • Views: 275
    asdf44
    3rd February 2019, 02:21 Go to last post

  21. what are the tests to be performed to verify the robustness of a standard cell ?

    Started by kaushikrvs, 25th January 2019 19:56
    • Replies: 2
    • Views: 543
    ThisIsNotSam
    25th January 2019, 21:04 Go to last post

  22. High-Level Synthesis (HLS) vs RTL for ASIC flow

    Started by oAwad, 31st December 2018 22:51
    • Replies: 3
    • Views: 835
    javierh.santiago
    21st January 2019, 18:08 Go to last post

  23. ADE9078 Energy Meter & Rogowski Coil Clarification

    Started by eebhoi01, 21st January 2019 08:19
    • Replies: 1
    • Views: 170
    FvM
    21st January 2019, 09:08 Go to last post

  24. How to generate the vcd file in modelsim for power estimation using PrimeTime Px

    Started by javierh.santiago, 19th January 2019 07:20
    • Replies: 4
    • Views: 494
    ThisIsNotSam
    20th January 2019, 15:52 Go to last post

  25. Using a CDL file in LTSpice

    Started by youngguns21, 16th January 2019 17:13
    • Replies: 3
    • Views: 343
    Akanimo
    16th January 2019, 21:51 Go to last post

  26. Clock gate set up and hold checks

    Started by mailsrikanth007, 15th January 2019 07:18
    • Replies: 1
    • Views: 242
    ThisIsNotSam
    15th January 2019, 15:56 Go to last post

  27. FIFO implementation using RAM

    Started by biju4u90, 8th January 2019 19:16
    • Replies: 3
    • Views: 691
    Alexxk
    9th January 2019, 11:47 Go to last post

  28. TSMC 65nm GP operating voltage

    Started by oAwad, 6th January 2019 21:10
    • Replies: 1
    • Views: 278
    ThisIsNotSam
    7th January 2019, 14:25 Go to last post

  29. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 8
    • Views: 1,236
    Tieny
    6th January 2019, 22:34 Go to last post

  30. fifo with ram or flops

    Started by stanford, 13th December 2018 01:40
    1 Attachment(s)
    • Replies: 7
    • Views: 672
    Tieny
    6th January 2019, 22:31 Go to last post
Powered by vBulletin™
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.