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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,019
    klug
    25th March 2007, 08:41 Go to last post

  1. How to clock gate in hierarchy?

    Started by DimitrisStathis, Yesterday 17:29
    • Replies: 2
    • Views: 52
    DimitrisStathis
    Today, 10:02 Go to last post

  2. Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 4
    • Views: 230
    fragnen
    Today, 09:29 Go to last post

  3. How to get the Number of components before a specific net using Design Compiler?

    Started by qaziarbab, Yesterday 10:58
    • Replies: 2
    • Views: 189
    qaziarbab
    Today, 09:18 Go to last post

  4. Is it possible to assign a value to a signal in a systemverilog assertion?

    Started by iammedjay, Today 08:53
    • Replies: 0
    • Views: 11
    iammedjay
    Today, 08:53 Go to last post

  5. Coverage improvement from AU.TC faults

    Started by aakashaspires, Yesterday 08:59
    • Replies: 1
    • Views: 63
    ThisIsNotSam
    Yesterday, 16:17 Go to last post

  6. meaning of placeable cells

    Started by sharanbr123, 14th June 2019 12:52
    • Replies: 2
    • Views: 144
    sharanbr123
    14th June 2019, 17:23 Go to last post

  7. How to ensure the accuracy of static timing analysis (STA) by using .lib

    Started by fatocean, 13th June 2019 13:13
    • Replies: 1
    • Views: 117
    ThisIsNotSam
    13th June 2019, 14:50 Go to last post

  8. TimeDesign in innovus with value 0 of Shift Phase

    Started by chineselboy, 12th June 2019 03:37
    1 Attachment(s)
    • Replies: 1
    • Views: 150
    ThisIsNotSam
    12th June 2019, 14:16 Go to last post

  9. Fault simulation of leon3mp mismatched with commercial diagnosis tool

    Started by LeoYou, 12th June 2019 09:00
    • Replies: 0
    • Views: 89
    LeoYou
    12th June 2019, 09:00 Go to last post

  10. ATPG Test Coverage for stuck@ and @speed

    Started by sandy2811, 25th March 2019 15:08
    • Replies: 3
    • Views: 300
    xodus_fr
    11th June 2019, 07:16 Go to last post

  11. What is Tranisition Delay and Path Delay Fault models in DFT ATPG?

    Started by Nanda_DFT, 19th February 2019 07:03
    • Replies: 1
    • Views: 191
    xodus_fr
    11th June 2019, 07:07 Go to last post

  12. [moved] Digital Transition Capture

    Started by minhchau, 8th June 2019 16:40
    3 Attachment(s)
    • Replies: 11
    • Views: 441
    summitville
    10th June 2019, 19:40 Go to last post

  13. Delay a signal in a system verilog testbench using jaspergold

    Started by haammzzaa, 10th June 2019 13:29
    • Replies: 4
    • Views: 137
    ThisIsNotSam
    10th June 2019, 16:01 Go to last post

  14. [SOLVED] How to re-synthesize a circuit with ABC synthesizer?

    Started by amin-ea, 25th May 2019 12:06
    • Replies: 5
    • Views: 319
    amin-ea
    10th June 2019, 08:40 Go to last post

  15. [SOLVED] Methodology to calculate the Clock Uncertainity values.

    Started by Wyre, 9th June 2019 10:35
    • Replies: 1
    • Views: 115
    ThisIsNotSam
    9th June 2019, 16:13 Go to last post

  16. Post-layout Simulation Errors in Virtuoso with av_extracted view

    Started by minmin_J, 6th June 2019 18:31
    • Replies: 1
    • Views: 202
    Dominik Przyborowski
    6th June 2019, 19:18 Go to last post

  17. System verilog, fork join_any

    Started by surerdra, 4th June 2019 08:49
    • Replies: 3
    • Views: 265
    surerdra
    5th June 2019, 07:05 Go to last post

  18. Add output signal to reliability analysis virtuoso-cadence

    Started by antlhem, 31st May 2019 12:11
    1 Attachment(s)
    • Replies: 2
    • Views: 230
    antlhem
    3rd June 2019, 15:19 Go to last post

  19. Post synthesis simulation shows setup and hold time violations while DC doesn't

    Started by dormant_bci, 30th May 2019 00:32
    • Replies: 8
    • Views: 687
    ThisIsNotSam
    2nd June 2019, 22:43 Go to last post

  20. Can you use StarRC to extract a certain subcell and all its connections to topcell?

    Started by majd229, 2nd June 2019 17:14
    • Replies: 1
    • Views: 164
    timof
    2nd June 2019, 21:31 Go to last post

  21. Optimizing case statement with large input

    Started by stanford, 30th May 2019 03:01
    • Replies: 8
    • Views: 668
    asdf44
    1st June 2019, 02:42 Go to last post

  22. if/else vs. if/if in combo logic

    Started by stanford, 30th May 2019 02:09
    • Replies: 10
    • Views: 459
    asdf44
    1st June 2019, 02:39 Go to last post

  23. Overloading Arithmethic operators in Design Compiler

    Started by javierh.santiago, 31st May 2019 17:57
    • Replies: 2
    • Views: 372
    javierh.santiago
    1st June 2019, 01:46 Go to last post

  24. Code coverage of a design

    Started by vyella1, 31st May 2019 04:12
    • Replies: 1
    • Views: 192
    ThisIsNotSam
    31st May 2019, 15:50 Go to last post

  25. blocking assignment in always_comb

    Started by stanford, 28th May 2019 04:25
    • Replies: 3
    • Views: 267
    dave_59
    28th May 2019, 19:22 Go to last post

  26. How to fix a setup violation /hold violations in net-to-net path ??

    Started by hcu, 26th May 2019 07:10
    1 Attachment(s)
    • Replies: 9
    • Views: 461
    ThisIsNotSam
    28th May 2019, 14:05 Go to last post

  27. Need to Make Monte Carlo Simulation fast

    Started by Syfulcste, 23rd May 2019 03:18
    • Replies: 9
    • Views: 1,146
    ThisIsNotSam
    27th May 2019, 02:27 Go to last post

  28. [SOLVED] Innovus changing pin connections

    Started by Alexxk, 20th May 2019 13:08
    • Replies: 6
    • Views: 981
    ThisIsNotSam
    22nd May 2019, 16:50 Go to last post

  29. Output of exors are showing x in EDA playground

    Started by sushl, 21st May 2019 11:58
    • Replies: 2
    • Views: 323
    sushl
    22nd May 2019, 02:17 Go to last post

  30. Multiple sources for a clock

    Started by kishoresai1996, 21st May 2019 18:04
    • Replies: 1
    • Views: 311
    ThisIsNotSam
    21st May 2019, 19:16 Go to last post
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