1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    124,419
Page 1 of 817 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24501

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,259
    klug
    25th March 2007, 08:41 Go to last post

  1. Using a BFM in system verification code.

    Started by dipk11, 15th November 2019 07:49
    • Replies: 6
    • Views: 255
    dipk11
    Today, 09:27 Go to last post

  2. SystemVerilog Interface signal assignment

    Started by ghertz, Yesterday 17:30
    • Replies: 2
    • Views: 155
    ghertz
    Yesterday, 23:46 Go to last post

  3. asynchronous D Flip flop with negative edge triggered clk,set and reset

    Started by Knowledge.seeker, Yesterday 11:11
    • Replies: 2
    • Views: 152
    dick_freebird
    Yesterday, 23:09 Go to last post

  4. DFT Visualizer Data View

    Started by Vignesh_J, 15th November 2019 13:24
    • Replies: 2
    • Views: 237
    Vignesh_J
    Yesterday, 08:03 Go to last post

  5. How to find the operating frequency for an ASIC?

    Started by daskk62, 17th November 2019 19:18
    • Replies: 2
    • Views: 130
    Tieny
    17th November 2019, 22:51 Go to last post

  6. How to generate sine wave using Verilog?

    Started by h_upadhyay, 9th November 2019 06:59
    • Replies: 9
    • Views: 604
    wwfeldman
    16th November 2019, 15:03 Go to last post

  7. Tool inserted DFT lockup latch is not transparent in functional mode (no test port)

    Started by Ashish Agrawal, 14th November 2019 18:32
    • Replies: 1
    • Views: 158
    Tieny
    15th November 2019, 12:12 Go to last post

  8. max_transition Violation

    Started by vyella1, 13th November 2019 22:17
    • Replies: 1
    • Views: 169
    ThisIsNotSam
    14th November 2019, 13:29 Go to last post

  9. Synopsys DC: Tracing clock path

    Started by vaibhava, 13th November 2019 08:36
    • Replies: 1
    • Views: 102
    ThisIsNotSam
    14th November 2019, 13:27 Go to last post

  10. What are the meaings of the following Calibre warnings

    Started by aditya1579, 13th November 2019 03:44
    • Replies: 2
    • Views: 179
    ThisIsNotSam
    14th November 2019, 13:25 Go to last post

  11. DFT parallel pattern simulation mismatch analysis

    Started by Vignesh_J, 13th November 2019 13:33
    • Replies: 1
    • Views: 131
    Tieny
    14th November 2019, 04:34 Go to last post

  12. For DFT perspective ,what happens when there are no capture clock

    Started by Varun124, 28th September 2019 08:31
    • Replies: 4
    • Views: 472
    Tieny
    13th November 2019, 09:46 Go to last post

  13. [moved] Value of lateral electric field(E0) in UMC 65 technology

    Started by abhishek260, 11th November 2019 12:41
    • Replies: 2
    • Views: 368
    timof
    12th November 2019, 02:31 Go to last post

  14. What is meant by Split CODEC IN DFT ?

    Started by Varun124, 12th October 2019 10:18
    • Replies: 1
    • Views: 319
    Tieny
    11th November 2019, 10:15 Go to last post

  15. LBIST low test coverage

    Started by vijay82, 23rd October 2019 08:21
    • Replies: 5
    • Views: 475
    Tieny
    11th November 2019, 10:07 Go to last post

  16. MBIST DONE & GO failing conditions

    Started by vipul982, 6th November 2019 14:13
    • Replies: 1
    • Views: 273
    Tieny
    11th November 2019, 10:03 Go to last post

  17. [SOLVED] [moved] What is Cadence genus synthesis, report power?

    Started by daskk62, 8th November 2019 18:50
    • Replies: 1
    • Views: 269
    ThisIsNotSam
    9th November 2019, 09:02 Go to last post

  18. External C++ compilation and DPI question

    Started by ghertz, 1st November 2019 23:39
    • Replies: 14
    • Views: 633
    ghertz
    6th November 2019, 00:20 Go to last post

  19. In PrimeTime, is there a similar command for setting output load cell to all outputs?

    Started by majd229, 5th November 2019 18:27
    • Replies: 0
    • Views: 200
    majd229
    5th November 2019, 18:27 Go to last post

  20. What is Negative timing checks

    Started by Varun124, 5th November 2019 11:32
    • Replies: 1
    • Views: 140
    ThisIsNotSam
    5th November 2019, 12:49 Go to last post

  21. SiliconSmart pin and lib file

    Started by xabosexi, 4th November 2019 08:04
    • Replies: 1
    • Views: 141
    ThisIsNotSam
    4th November 2019, 12:22 Go to last post

  22. Mipi D-phy physical layer implementation

    Started by MaheshC, 4th November 2019 10:33
    • Replies: 0
    • Views: 114
    MaheshC
    4th November 2019, 10:33 Go to last post

  23. How does aging is conducted exactly in Cadence?

    Started by antlhem, 31st October 2019 11:42
    3 Attachment(s)
    • Replies: 3
    • Views: 420
    antlhem
    2nd November 2019, 14:25 Go to last post

  24. How to measure the C parasitic (internal capacitance) of an inverter using Spectre ?

    Started by Puppet123, 26th October 2019 14:35
    2 Attachment(s)
    • Replies: 17
    • Views: 1,319
    timof
    31st October 2019, 17:22 Go to last post

  25. Moved: CMOS ring oscillator frequency degradation through years

    Started by antlhem, 2nd November 2019 15:00
    •  
    •  

  26. Voltage drop of on die power gating cells

    Started by volsky, 29th October 2019 07:34
    • Replies: 4
    • Views: 326
    ThisIsNotSam
    30th October 2019, 12:19 Go to last post

  27. [SOLVED] Preventing using a certain cell in cadence encounter

    Started by Abdo_Mgdy, 29th October 2019 12:39
    • Replies: 2
    • Views: 213
    Abdo_Mgdy
    29th October 2019, 14:22 Go to last post

  28. Solution for ICC mismatch in units

    Started by Vlsi24, 29th October 2019 08:06
    • Replies: 0
    • Views: 105
    Vlsi24
    29th October 2019, 08:06 Go to last post

  29. Getting exact values of VIL, VOL, VIH and VOH ?

    Started by Robotduck, 25th October 2019 15:35
    • Replies: 0
    • Views: 263
    Robotduck
    25th October 2019, 15:35 Go to last post

  30. Transient Simulation in Cadence

    Started by KingDarius6288, 24th October 2019 02:33
    • Replies: 2
    • Views: 300
    ThisIsNotSam
    24th October 2019, 08:00 Go to last post
Powered by vBulletin™
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.