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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,156
    klug
    25th March 2007, 08:41 Go to last post

  1. rtl code to find the smallest

    Started by stanford, 20th February 2019 08:47
    • Replies: 10
    • Views: 240
    ThisIsNotSam
    Yesterday, 23:34 Go to last post

  2. Question related to high latency

    Started by kirankumark0489, 19th February 2019 23:34
    • Replies: 3
    • Views: 150
    ThisIsNotSam
    Yesterday, 23:32 Go to last post

  3. [moved] Area and Gate Equivalent in Leonardo Spectrum Report

    Started by NehaJain1234, 20th February 2019 16:21
    2 Attachment(s)
    • Replies: 3
    • Views: 132
    ThisIsNotSam
    Yesterday, 16:10 Go to last post

  4. LBIST architecture - Industry standards

    Started by Nanda_DFT, 20th February 2019 06:09
    • Replies: 1
    • Views: 57
    ArakelTheDragon
    Yesterday, 11:54 Go to last post

  5. Test-per-scan v/s Test-per-clock

    Started by Nanda_DFT, 20th February 2019 06:11
    • Replies: 1
    • Views: 75
    ArakelTheDragon
    Yesterday, 11:50 Go to last post

  6. Logical and physical 0.13 or 0.18 um technology library

    Started by Abdo18, 20th February 2019 20:45
    • Replies: 0
    • Views: 44
    Abdo18
    20th February 2019, 20:45 Go to last post

  7. On-Chip Clock logic (macros) placement during Testability insertion

    Started by Nanda_DFT, 20th February 2019 06:08
    • Replies: 1
    • Views: 78
    ThisIsNotSam
    20th February 2019, 16:01 Go to last post

  8. Test vector patterns in LEC

    Started by Fati_hv, 20th February 2019 09:40
    • Replies: 0
    • Views: 54
    Fati_hv
    20th February 2019, 09:40 Go to last post

  9. What are common supports in LEC?

    Started by Fati_hv, 20th February 2019 09:12
    • Replies: 0
    • Views: 49
    Fati_hv
    20th February 2019, 09:12 Go to last post

  10. Synopsys Technology File (STF)

    Started by manpmanp, 20th February 2019 09:07
    • Replies: 0
    • Views: 59
    manpmanp
    20th February 2019, 09:07 Go to last post

  11. DFT Scan chain blocking detection

    Started by Nanda_DFT, 20th February 2019 06:04
    • Replies: 0
    • Views: 40
    Nanda_DFT
    20th February 2019, 06:04 Go to last post

  12. [SOLVED] Clock domain crossing problem in DFT

    Started by Nanda_DFT, 19th February 2019 07:06
    • Replies: 2
    • Views: 124
    Nanda_DFT
    20th February 2019, 05:56 Go to last post

  13. What is Tranisition Delay and Path Delay Fault models in DFT ATPG?

    Started by Nanda_DFT, 19th February 2019 07:03
    • Replies: 0
    • Views: 48
    Nanda_DFT
    19th February 2019, 07:03 Go to last post

  14. Post layout delay in cadence

    Started by umaizameh, 14th February 2019 06:53
    • Replies: 7
    • Views: 431
    oratie
    19th February 2019, 06:34 Go to last post

  15. How to Dump e-vcd File in Verilog HDL ?

    Started by sreejeesh_sreedharan, 14th February 2019 08:28
    • Replies: 2
    • Views: 136
    ThisIsNotSam
    14th February 2019, 16:39 Go to last post

  16. Sample files needed for working with Automatic PnR

    Started by LostEagle, 14th February 2019 00:17
    • Replies: 1
    • Views: 115
    ThisIsNotSam
    14th February 2019, 02:05 Go to last post

  17. Timing issues in netlist simualtion - SDF simulation of IP block

    Started by manpmanp, 11th February 2019 16:27
    1 Attachment(s)
    • Replies: 4
    • Views: 205
    manpmanp
    13th February 2019, 09:34 Go to last post

  18. Using SPEF files for STA in INNOVUS

    Started by Windywast, 12th February 2019 01:37
    • Replies: 3
    • Views: 197
    ThisIsNotSam
    12th February 2019, 17:49 Go to last post

  19. Help to synthesize floating point MAC in Design Compiler using DesignWare library.

    Started by DreamCaCao, 7th February 2019 06:25
    • Replies: 4
    • Views: 316
    ckqee
    11th February 2019, 19:41 Go to last post

  20. What does it mean to have a sequential encoding scheme to enumerate states?

    Started by MightyFunkster, 11th February 2019 17:03
    • Replies: 1
    • Views: 100
    ads-ee
    11th February 2019, 17:19 Go to last post

  21. synthesized netlists simulation issue

    Started by manpmanp, 7th February 2019 17:42
    1 Attachment(s)
    • Replies: 6
    • Views: 240
    ThisIsNotSam
    11th February 2019, 16:19 Go to last post

  22. DFT issues on scan clock input as "x"

    Started by skyworld_cy, 9th February 2019 10:08
    1 Attachment(s)
    • Replies: 5
    • Views: 300
    ThisIsNotSam
    10th February 2019, 03:47 Go to last post

  23. How do you simulate a mixed-signal system?

    Started by blacki, 8th February 2019 17:22
    1 Attachment(s)
    • Replies: 2
    • Views: 137
    BradtheRad
    9th February 2019, 05:40 Go to last post

  24. What's the difference between creating ndm using oas and lef

    Started by Studentofknowledge, 8th February 2019 17:37
    • Replies: 1
    • Views: 85
    ThisIsNotSam
    8th February 2019, 18:46 Go to last post

  25. MCR - Metal Cap Reduction

    Started by Studentofknowledge, 8th February 2019 17:44
    • Replies: 1
    • Views: 86
    KlausST
    8th February 2019, 18:11 Go to last post

  26. Have you ever done timing simulation with ARM standard cell library ?

    Started by Yongchan, 8th February 2019 02:15
    • Replies: 0
    • Views: 124
    Yongchan
    8th February 2019, 02:15 Go to last post

  27. Automatize simulations in Modelsim

    Started by javierh.santiago, 5th February 2019 22:44
    • Replies: 2
    • Views: 283
    dave_59
    8th February 2019, 00:12 Go to last post

  28. what are the inputs and outputs for floorplanning?

    Started by lh-, 3rd February 2019 18:28
    1 Attachment(s)
    • Replies: 8
    • Views: 406
    lh-
    7th February 2019, 19:42 Go to last post

  29. Digital filter projects

    Started by blacki, 6th February 2019 04:53
    • Replies: 7
    • Views: 305
    dpaul
    7th February 2019, 14:16 Go to last post

  30. finFET's behavior with Temperature

    Started by Wyre, 6th February 2019 10:28
    • Replies: 1
    • Views: 216
    ThisIsNotSam
    7th February 2019, 02:58 Go to last post
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