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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,267
    klug
    25th March 2007, 08:41 Go to last post

  1. Divison by 2 syntesizable RTL coding

    Started by sky_above, 26th May 2018 16:55
    • Replies: 4
    • Views: 79
    andre_teprom
    Yesterday, 23:01 Go to last post

  2. Output combinational output and valid sequential

    Started by sky_above, 26th May 2018 16:22
    • Replies: 3
    • Views: 66
    swabhi812
    Yesterday, 22:19 Go to last post

  3. D Flipflop with enable does not have the else part in RTL in the if-else statement

    Started by sky_above, 25th May 2018 15:07
    • Replies: 8
    • Views: 556
    FvM
    Yesterday, 18:44 Go to last post

  4. generic parameter while instantiating design at top level if allowed

    Started by sky_above, Yesterday 10:05
    • Replies: 1
    • Views: 47
    pancho_hideboo
    Yesterday, 13:49 Go to last post

  5. Realization of D flip flop by basic gates from library while synthesizing

    Started by sky_above, 26th May 2018 16:47
    • Replies: 1
    • Views: 40
    barry
    26th May 2018, 17:32 Go to last post

  6. If the rtl of adder is correct and instance declaration is correct and also ripple ca

    Started by sky_above, 26th May 2018 16:44
    • Replies: 0
    • Views: 193
    sky_above
    26th May 2018, 16:44 Go to last post

  7. Whether synthesis tool will realize comparators or not

    Started by sky_above, 26th May 2018 15:48
    • Replies: 0
    • Views: 31
    sky_above
    26th May 2018, 15:48 Go to last post

  8. Read operation of a memory and clock cycles

    Started by sky_above, 26th May 2018 07:34
    • Replies: 2
    • Views: 62
    KlausST
    26th May 2018, 12:08 Go to last post

  9. Timing through the d pin

    Started by stanford, 22nd May 2018 06:23
    • Replies: 3
    • Views: 118
    ads-ee
    26th May 2018, 00:23 Go to last post

  10. Async set deassertion

    Started by stanford, 25th May 2018 07:03
    • Replies: 1
    • Views: 74
    barry
    25th May 2018, 23:40 Go to last post

  11. How to figure out whether it is setup or hold issue on real silicon

    Started by stanford, 24th May 2018 00:58
    • Replies: 4
    • Views: 170
    ThisIsNotSam
    25th May 2018, 22:29 Go to last post

  12. Cell Characterization Determining Slew vs Capacitive Values for Templates

    Started by ranaya, 23rd May 2018 19:20
    • Replies: 2
    • Views: 90
    artmalik
    25th May 2018, 19:51 Go to last post

  13. Difference in Delays of the same cells in best run and worst run

    Started by Stichi_1985, 25th May 2018 06:44
    • Replies: 2
    • Views: 61
    ThisIsNotSam
    25th May 2018, 17:49 Go to last post

  14. CADENCE XSIM Default Timescale

    Started by jiminization, 25th May 2018 12:29
    • Replies: 1
    • Views: 41
    ThisIsNotSam
    25th May 2018, 17:43 Go to last post

  15. D flip flop RTL without Qbar

    Started by sky_above, 24th May 2018 14:37
    • Replies: 7
    • Views: 103
    FvM
    24th May 2018, 19:15 Go to last post

  16. [SOLVED] Synthesize an RTL from two technology .db files (of same node)

    Started by ranaya, 22nd May 2018 20:17
    • Replies: 6
    • Views: 138
    rca
    24th May 2018, 15:09 Go to last post

  17. Clock gating and cdc on clock_req

    Started by stanford, 22nd May 2018 23:15
    • Replies: 3
    • Views: 174
    FvM
    24th May 2018, 10:49 Go to last post

  18. UPF: What is isolation sense in isolation strategy?

    Started by swabhi812, 20th May 2018 01:01
    • Replies: 3
    • Views: 222
    stanford
    22nd May 2018, 06:47 Go to last post

  19. DC-topo and ICC environment comparison

    Started by ua6bqg, 7th May 2018 17:19
    • Replies: 6
    • Views: 249
    slutarius
    22nd May 2018, 01:38 Go to last post

  20. multiple registers inside if-else of an always block

    Started by sky_above, 16th May 2018 13:44
    2 Attachment(s)
    • Replies: 15
    • Views: 333
    ads-ee
    21st May 2018, 17:15 Go to last post

  21. Digital VLSI verification engineer - required knowledge

    Started by NikosTS, 2nd May 2018 17:36
    • Replies: 7
    • Views: 342
    swabhi812
    18th May 2018, 19:38 Go to last post

  22. Capacitance of the ESD protection devices, the bond pad, the bond wire

    Started by littlerock, 17th May 2018 11:03
    5 Attachment(s)
    • Replies: 7
    • Views: 273
    ThisIsNotSam
    18th May 2018, 14:32 Go to last post

  23. Selecting CTS topology in ICC

    Started by Vamsi Srikanth S, 17th May 2018 12:57
    • Replies: 2
    • Views: 136
    Vamsi Srikanth S
    17th May 2018, 19:04 Go to last post

  24. Questions on DFT autofix

    Started by childs72, 17th May 2018 02:54
    • Replies: 1
    • Views: 98
    Tieny
    17th May 2018, 07:06 Go to last post

  25. PTPX Switching power calculation

    Started by Mohammed Abrar, 16th May 2018 01:06
    • Replies: 1
    • Views: 124
    slutarius
    17th May 2018, 05:34 Go to last post

  26. RTL for linear search

    Started by sky_above, 14th May 2018 13:59
    • Replies: 19
    • Views: 525
    ThisIsNotSam
    16th May 2018, 15:11 Go to last post

  27. Why higherk frequency circuit may encounter hold time violation for low frequency?

    Started by Anklon, 13th May 2018 11:08
    • Replies: 7
    • Views: 746
    ThisIsNotSam
    16th May 2018, 15:10 Go to last post

  28. 4 bit multiplier from 2 bit multiplier

    Started by sky_above, 14th May 2018 13:56
    • Replies: 3
    • Views: 106
    FvM
    14th May 2018, 15:24 Go to last post

  29. Synopsys tools to find controllability and observability

    Started by Ziki, 10th May 2018 19:34
    • Replies: 1
    • Views: 226
    dpaul
    11th May 2018, 13:40 Go to last post

  30. Cadence encounter - Custom level shifters and power domains APR

    Started by NikosTS, 9th May 2018 14:55
    • Replies: 3
    • Views: 274
    NikosTS
    10th May 2018, 14:34 Go to last post
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