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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,297
    25th March 2007, 08:41 Go to last post
  1. FERROCORE FR3 more information?

    Started by Coper, Yesterday 10:42
    • Replies: 2
    • Views: 129
    Yesterday, 14:47 Go to last post
  2. CRC Error insertion and detection

    Started by rrucha, 17th July 2019 21:01
    • Replies: 4
    • Views: 281
    19th July 2019, 19:19 Go to last post
  3. dft-how to use .bench format

    Started by avinashkumar, 18th July 2019 09:18
    • Replies: 1
    • Views: 142
    19th July 2019, 12:16 Go to last post
    • Replies: 0
    • Views: 86
    17th July 2019, 19:12 Go to last post
  4. Tech library problem

    Started by abdoboua, 16th July 2019 12:15
    • Replies: 3
    • Views: 170
    16th July 2019, 18:49 Go to last post
    • Replies: 4
    • Views: 229
    16th July 2019, 17:30 Go to last post
  5. Help needed for spice conversion from mdl syntax

    Started by smurtuzah, 16th July 2019 13:29
    • Replies: 0
    • Views: 101
    16th July 2019, 13:29 Go to last post
  6. DRC problem with layout in cadence 617

    Started by abdoboua, 8th July 2019 19:05
    • Replies: 1
    • Views: 155
    16th July 2019, 11:35 Go to last post
  7. Problem when installing Calibre

    Started by abdoboua, 10th July 2019 20:35
    • Replies: 1
    • Views: 151
    15th July 2019, 16:22 Go to last post
  8. ModelSim simulation error

    Started by garvind25, 11th July 2019 10:42
    • Replies: 11
    • Views: 458
    15th July 2019, 15:59 Go to last post
  9. Cannot find vdd in the design

    Started by kartikpujari, 14th July 2019 05:25
    • Replies: 2
    • Views: 205
    14th July 2019, 19:44 Go to last post
    • Replies: 1
    • Views: 317
    14th July 2019, 18:48 Go to last post
  10. Systemverilog type cast or integer division

    Started by parafux, 10th July 2019 13:51
    • Replies: 2
    • Views: 205
    13th July 2019, 18:53 Go to last post
  11. Global Buffer Access Normalized Energy Cost

    Started by moa375, 12th July 2019 21:51
    • Replies: 0
    • Views: 155
    12th July 2019, 21:51 Go to last post
  12. What do you mean by Predictive FIFO?

    Started by rameshbabur, 11th July 2019 08:01
    • Replies: 2
    • Views: 238
    12th July 2019, 19:01 Go to last post
    • Replies: 2
    • Views: 218
    12th July 2019, 18:46 Go to last post
  13. Digital design of a GPU

    Started by adwnis123, 11th July 2019 14:06
    • Replies: 3
    • Views: 296
    12th July 2019, 14:00 Go to last post
  14. Saving the layout in innovus

    Started by Chinmaye, 10th July 2019 11:45
    • Replies: 7
    • Views: 339
    11th July 2019, 17:44 Go to last post
    • Replies: 3
    • Views: 250
    10th July 2019, 21:41 Go to last post
  15. [SOLVED] Error during clock tree synthesis in innovus

    Started by Chinmaye, 10th July 2019 10:51
    • Replies: 1
    • Views: 125
    10th July 2019, 17:34 Go to last post
  16. pins of symbol and layout do not match

    Started by abdoboua, 9th July 2019 12:01
    • Replies: 4
    • Views: 221
    9th July 2019, 21:59 Go to last post
  17. Help in understanding innovus

    Started by Chinmaye, 5th July 2019 06:56
    • Replies: 5
    • Views: 468
    9th July 2019, 14:30 Go to last post
    • Replies: 2
    • Views: 156
    8th July 2019, 15:51 Go to last post