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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,825
    klug
    25th March 2007, 08:41 Go to last post

  1. Need to Make Monte Carlo Simulation fast

    Started by Syfulcste, Yesterday 03:18
    • Replies: 4
    • Views: 150
    Syfulcste
    Today, 03:26 Go to last post

  2. [SOLVED] Innovus changing pin connections

    Started by Alexxk, 20th May 2019 13:08
    • Replies: 6
    • Views: 515
    ThisIsNotSam
    22nd May 2019, 16:50 Go to last post

  3. Output of exors are showing x in EDA playground

    Started by sushl, 21st May 2019 11:58
    • Replies: 2
    • Views: 198
    sushl
    22nd May 2019, 02:17 Go to last post

  4. Multiple sources for a clock

    Started by kishoresai1996, 21st May 2019 18:04
    • Replies: 1
    • Views: 132
    ThisIsNotSam
    21st May 2019, 19:16 Go to last post

  5. Handling LEC for multibit flipflop

    Started by fragnen, 3rd April 2019 14:47
    • Replies: 1
    • Views: 372
    Spoorthi_Harithas
    21st May 2019, 06:55 Go to last post

  6. Hierarchical and Flat LEC

    Started by fragnen, 5th April 2019 08:37
    • Replies: 1
    • Views: 355
    Spoorthi_Harithas
    21st May 2019, 06:54 Go to last post

  7. Last step of tapeoout---sealring and dummy fill density

    Started by AllenD, 18th May 2019 15:36
    • Replies: 1
    • Views: 291
    ThisIsNotSam
    20th May 2019, 16:16 Go to last post

  8. TSMC LVS errors after sealring

    Started by AllenD, 19th May 2019 08:50
    • Replies: 1
    • Views: 252
    ThisIsNotSam
    20th May 2019, 16:14 Go to last post

  9. ADS1115 issue for taking values of 4th digit after decimal point

    Started by RenesasT, 25th April 2019 09:36
    • Replies: 6
    • Views: 540
    KlausST
    20th May 2019, 01:30 Go to last post

  10. [moved] Saving data from reliability simulation Virtuoso Cadence

    Started by antlhem, 17th May 2019 17:23
    1 Attachment(s)
    • Replies: 0
    • Views: 129
    antlhem
    17th May 2019, 17:23 Go to last post

  11. [SOLVED] Hz vs number of bits

    Started by tahirsengine, 3rd May 2019 11:47
    • Replies: 6
    • Views: 423
    KlausST
    17th May 2019, 06:42 Go to last post

  12. LEC at top level of a SOC

    Started by fragnen, 7th May 2019 14:22
    • Replies: 1
    • Views: 139
    vipul982
    17th May 2019, 06:28 Go to last post

  13. How does Foundry provide different Process Models?

    Started by Wyre, 13th May 2019 09:22
    • Replies: 1
    • Views: 214
    ThisIsNotSam
    13th May 2019, 16:35 Go to last post

  14. recovery time of sync reset vs. async reset

    Started by stanford, 9th May 2019 02:29
    • Replies: 5
    • Views: 2,348
    stanford
    9th May 2019, 18:36 Go to last post

  15. TSMC 65nm Calibre dummy insertion tool

    Started by AllenD, 5th May 2019 11:36
    • Replies: 8
    • Views: 3,207
    AllenD
    9th May 2019, 09:26 Go to last post

  16. synthesizing memory as latches

    Started by vyella1, 8th May 2019 17:19
    • Replies: 1
    • Views: 787
    ThisIsNotSam
    8th May 2019, 18:23 Go to last post

  17. Design to state position of first one from lsb every clock for parallel data coming

    Started by fragnen, 12th April 2019 14:18
    1 Attachment(s)
    • Replies: 11
    • Views: 2,897
    Akanimo
    8th May 2019, 00:17 Go to last post

  18. [Questa] How to colorize the Transcript window (files, directories, etc)?

    Started by ldm.eth, 5th May 2019 16:51
    • Replies: 2
    • Views: 168
    ldm.eth
    5th May 2019, 18:14 Go to last post

  19. How to create *.mpf in the "middle of work"?

    Started by ldm.eth, 5th May 2019 14:59
    • Replies: 0
    • Views: 84
    ldm.eth
    5th May 2019, 14:59 Go to last post

  20. How PA/PTPX handle analog macro

    Started by tarkyss, 5th May 2019 10:11
    • Replies: 0
    • Views: 106
    tarkyss
    5th May 2019, 10:11 Go to last post

  21. How to reduce the ringing that occur in the PI analysis using the package.

    Started by savithad, 4th May 2019 09:29
    • Replies: 0
    • Views: 128
    savithad
    4th May 2019, 09:29 Go to last post

  22. Always @ flop holding value when else is not specified

    Started by stanford, 3rd May 2019 04:55
    • Replies: 2
    • Views: 233
    asdf44
    3rd May 2019, 17:13 Go to last post

  23. How to use the verilog obfuscator?

    Started by nagulapatigirireddy, 2nd May 2019 14:54
    1 Attachment(s)
    • Replies: 3
    • Views: 282
    ads-ee
    3rd May 2019, 16:41 Go to last post

  24. DC Optimize Registers message

    Started by mwb, 1st May 2019 17:22
    • Replies: 0
    • Views: 230
    mwb
    1st May 2019, 17:22 Go to last post

  25. Design Compiler Register Retiming and CDC

    Started by mwb, 24th April 2019 10:48
    • Replies: 2
    • Views: 1,294
    mwb
    1st May 2019, 17:13 Go to last post

  26. How to synchronize two LFSR between PRBS generator and checker

    Started by stanford, 29th April 2019 19:16
    • Replies: 7
    • Views: 4,238
    FvM
    1st May 2019, 10:41 Go to last post

  27. Writing ModelSim do files

    Started by tahirsengine, 18th April 2019 07:54
    • Replies: 3
    • Views: 651
    dave_59
    26th April 2019, 15:02 Go to last post

  28. [moved] Learning DFT as an intern and need help with .dft.v files

    Started by linaxus, 12th April 2019 01:08
    • Replies: 1
    • Views: 251
    vipul982
    25th April 2019, 06:20 Go to last post

  29. 32x32 Single Cycle Fast Multiplier

    Started by Mr.PAP, 18th April 2019 12:56
    • Replies: 10
    • Views: 7,340
    Mr.PAP
    24th April 2019, 06:25 Go to last post

  30. Synth. area reduced when adding a pipeline register

    Started by oAwad, 22nd April 2019 22:02
    • Replies: 4
    • Views: 1,599
    ThisIsNotSam
    23rd April 2019, 14:56 Go to last post
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