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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,259
    25th March 2007, 08:41 Go to last post
  1. Problem when installing Calibre

    Started by abdoboua, 10th July 2019 20:35
    • Replies: 1
    • Views: 106
    Yesterday, 16:22 Go to last post
  2. ModelSim simulation error

    Started by garvind25, 11th July 2019 10:42
    • Replies: 11
    • Views: 367
    Yesterday, 15:59 Go to last post
  3. Cannot find vdd in the design

    Started by kartikpujari, 14th July 2019 05:25
    • Replies: 2
    • Views: 146
    14th July 2019, 19:44 Go to last post
    • Replies: 1
    • Views: 284
    14th July 2019, 18:48 Go to last post
  4. Systemverilog type cast or integer division

    Started by parafux, 10th July 2019 13:51
    • Replies: 2
    • Views: 172
    13th July 2019, 18:53 Go to last post
  5. Global Buffer Access Normalized Energy Cost

    Started by moa375, 12th July 2019 21:51
    • Replies: 0
    • Views: 130
    12th July 2019, 21:51 Go to last post
  6. What do you mean by Predictive FIFO?

    Started by rameshbabur, 11th July 2019 08:01
    • Replies: 2
    • Views: 202
    12th July 2019, 19:01 Go to last post
    • Replies: 2
    • Views: 177
    12th July 2019, 18:46 Go to last post
  7. Digital design of a GPU

    Started by adwnis123, 11th July 2019 14:06
    • Replies: 3
    • Views: 258
    12th July 2019, 14:00 Go to last post
  8. Saving the layout in innovus

    Started by Chinmaye, 10th July 2019 11:45
    • Replies: 7
    • Views: 293
    11th July 2019, 17:44 Go to last post
    • Replies: 3
    • Views: 216
    10th July 2019, 21:41 Go to last post
  9. [SOLVED] Error during clock tree synthesis in innovus

    Started by Chinmaye, 10th July 2019 10:51
    • Replies: 1
    • Views: 108
    10th July 2019, 17:34 Go to last post
  10. pins of symbol and layout do not match

    Started by abdoboua, 9th July 2019 12:01
    • Replies: 4
    • Views: 174
    9th July 2019, 21:59 Go to last post
  11. Help in understanding innovus

    Started by Chinmaye, 5th July 2019 06:56
    • Replies: 5
    • Views: 408
    9th July 2019, 14:30 Go to last post
  12. DRC problem with layout in cadence 617

    Started by abdoboua, 8th July 2019 19:05
    • Replies: 0
    • Views: 104
    8th July 2019, 19:05 Go to last post
    • Replies: 2
    • Views: 133
    8th July 2019, 15:51 Go to last post
  13. Clock Buffer Questions

    Started by promach, 8th July 2019 15:26
    • Replies: 0
    • Views: 126
    8th July 2019, 15:26 Go to last post
  14. problem when zooming to see layers

    Started by abdoboua, 5th July 2019 11:23
    • Replies: 7
    • Views: 369
    8th July 2019, 14:11 Go to last post
    • Replies: 6
    • Views: 440
    7th July 2019, 14:35 Go to last post
  15. Getting an error in icc2_shell. Need help

    Started by nitheeshm, 6th July 2019 21:57
    • Replies: 0
    • Views: 180
    6th July 2019, 21:57 Go to last post
  16. [SOLVED] Timing slack showing Unconstrained after synthesis in genus

    Started by Chinmaye, 4th July 2019 08:37
    • Replies: 5
    • Views: 284
    5th July 2019, 14:08 Go to last post
  17. Asynchronous Scan clocks

    Started by Varun124, 3rd July 2019 20:17
    • Replies: 1
    • Views: 170
    4th July 2019, 19:33 Go to last post
  18. Lockup Latch for DFT purpose

    Started by Varun124, 3rd July 2019 19:34
    • Replies: 0
    • Views: 83
    3rd July 2019, 19:34 Go to last post
    • Replies: 2
    • Views: 203
    3rd July 2019, 18:13 Go to last post
    • Replies: 0
    • Views: 163
    3rd July 2019, 17:18 Go to last post