1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    121,766
Page 1 of 815 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24421

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,536
    klug
    25th March 2007, 08:41 Go to last post

  1. LEC between two netlists

    Started by fragnen, Today 13:22
    • Replies: 1
    • Views: 53
    TonyLS
    Today, 20:54 Go to last post

  2. Working with multible libraries in Modelsim

    Started by javierh.santiago, Yesterday 20:04
    • Replies: 1
    • Views: 98
    ads-ee
    Today, 02:16 Go to last post

  3. Convert ITF file to ict for captable generation

    Started by Chinmaye, 14th August 2019 17:30
    • Replies: 4
    • Views: 382
    Chinmaye
    16th August 2019, 10:10 Go to last post

  4. Protocol Design - System Verilog

    Started by fazimohd, 12th August 2019 12:53
    • Replies: 5
    • Views: 362
    ThisIsNotSam
    14th August 2019, 09:24 Go to last post

  5. How to generate test patterns in TetraMax with hold time violation

    Started by saicom, 12th August 2019 10:52
    • Replies: 0
    • Views: 127
    saicom
    12th August 2019, 10:52 Go to last post

  6. How to install and use Standard Cell Library in Virtuoso?

    Started by mosdarsh, 10th August 2019 18:02
    • Replies: 6
    • Views: 350
    mosdarsh
    11th August 2019, 17:53 Go to last post

  7. How to pass arguments to PrimeTime TCL script? (using pt_shell -file myScript.tcl )

    Started by majd229, 29th July 2019 18:55
    • Replies: 2
    • Views: 376
    javierh.santiago
    9th August 2019, 20:41 Go to last post

  8. Max tran, max cap ,max fanout

    Started by Akshaykumarbm, 8th August 2019 07:49
    • Replies: 2
    • Views: 215
    akshay0993
    9th August 2019, 19:41 Go to last post

  9. What is a Via Ladder ?

    Started by akshay0993, 9th August 2019 19:40
    • Replies: 0
    • Views: 97
    akshay0993
    9th August 2019, 19:40 Go to last post

  10. GLS with a Timing Model using PrimeTime and Modelsim

    Started by javierh.santiago, 7th August 2019 00:06
    • Replies: 2
    • Views: 246
    javierh.santiago
    7th August 2019, 18:40 Go to last post

  11. How to get all Objects in the Design in ICC2

    Started by Seshas241, 3rd August 2019 16:13
    • Replies: 0
    • Views: 223
    Seshas241
    3rd August 2019, 16:13 Go to last post

  12. How to get_attribute of a user defined attribute in a timing lib in PrimeTime?

    Started by majd229, 31st July 2019 22:47
    • Replies: 0
    • Views: 242
    majd229
    31st July 2019, 22:47 Go to last post

  13. generic ancillary data extractor and inserter

    Started by yashjain, 28th July 2019 08:01
    • Replies: 2
    • Views: 315
    yashjain
    28th July 2019, 14:20 Go to last post

  14. Can't Read SAED32nm libraries for design compiler

    Started by ibtesam90, 23rd July 2019 17:50
    1 Attachment(s)
    • Replies: 5
    • Views: 544
    oratie
    25th July 2019, 19:52 Go to last post

  15. [SOLVED] $urandom_range is generating same values

    Started by swabhi812, 23rd July 2019 22:26
    • Replies: 2
    • Views: 345
    swabhi812
    24th July 2019, 06:25 Go to last post

  16. In PrimeTime, how can I view setup/hold times per endpoint in easy format for parsing

    Started by majd229, 19th July 2019 16:35
    • Replies: 4
    • Views: 421
    majd229
    23rd July 2019, 17:17 Go to last post

  17. how to design combinational parts of benchmark circuits

    Started by avinashkumar, 23rd July 2019 13:54
    • Replies: 2
    • Views: 208
    avinashkumar
    23rd July 2019, 16:33 Go to last post

  18. Simulation problem with MMSIM using smic 65nm technology

    Started by abdoboua, 23rd July 2019 09:10
    2 Attachment(s)
    • Replies: 2
    • Views: 281
    abdoboua
    23rd July 2019, 15:17 Go to last post

  19. FERROCORE FR3 more information?

    Started by Coper, 22nd July 2019 10:42
    • Replies: 2
    • Views: 428
    FvM
    22nd July 2019, 14:47 Go to last post

  20. CRC Error insertion and detection

    Started by rrucha, 17th July 2019 21:01
    • Replies: 4
    • Views: 482
    rrucha
    19th July 2019, 19:19 Go to last post

  21. dft-how to use .bench format

    Started by avinashkumar, 18th July 2019 09:18
    • Replies: 1
    • Views: 287
    dpaul
    19th July 2019, 12:16 Go to last post

  22. DFT - Tetramax for pattern generation and test coverage

    Started by avinashkumar, 17th July 2019 19:12
    • Replies: 0
    • Views: 202
    avinashkumar
    17th July 2019, 19:12 Go to last post

  23. In PrimeTime, whats are -start_end_pair and -cover_design in report_timing cmd?

    Started by majd229, 17th July 2019 16:19
    • Replies: 0
    • Views: 199
    majd229
    17th July 2019, 16:19 Go to last post

  24. Input & output delay in mixed signal chip - RTL Signal Integrity

    Started by The_Dutchman, 14th July 2019 09:46
    1 Attachment(s)
    • Replies: 3
    • Views: 433
    ThisIsNotSam
    16th July 2019, 18:55 Go to last post

  25. Tech library problem

    Started by abdoboua, 16th July 2019 12:15
    4 Attachment(s)
    • Replies: 3
    • Views: 328
    ThisIsNotSam
    16th July 2019, 18:49 Go to last post

  26. [SOLVED] What is the difference of power estimation between Design Compiler and PrimeTIme PX

    Started by kkpark, 16th July 2019 06:34
    • Replies: 4
    • Views: 364
    ThisIsNotSam
    16th July 2019, 17:30 Go to last post

  27. [m]What is the difference between "Damascene copper" interconnect and normal copper ?

    Started by RohithRaj, 16th July 2019 13:22
    • Replies: 1
    • Views: 250
    ThisIsNotSam
    16th July 2019, 17:24 Go to last post

  28. Help needed for Spice conversion from MDL Syntax

    Started by smurtuzah, 16th July 2019 13:29
    • Replies: 0
    • Views: 191
    smurtuzah
    16th July 2019, 13:29 Go to last post

  29. DRC problem with layout in cadence 617

    Started by abdoboua, 8th July 2019 19:05
    • Replies: 1
    • Views: 263
    jbeniston
    16th July 2019, 11:35 Go to last post

  30. How do I know inbetween which pins do arcs exist in PrimeTime for timing libs?

    Started by majd229, 15th July 2019 20:40
    • Replies: 1
    • Views: 236
    oratie
    16th July 2019, 06:14 Go to last post
Powered by vBulletin™
Copyright © 2017 vBulletin Solutions, Inc. All rights reserved.