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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,417
    25th March 2007, 08:41 Go to last post
  1. A Revolutionary Massively Parallel Processing Architecture

    Started by paulpawlenko, 14th July 2018 01:16
    2 Pages
    1 2
    • Replies: 39
    • Views: 1,364
    Today, 16:04 Go to last post
  2. Create Block in innovus to use on other designs

    Started by rmachado, 4th July 2018 17:43
    2 Pages
    1 2
    • Replies: 21
    • Views: 394
    Today, 15:32 Go to last post
  3. mod % vs divider (are they synthesizable?)

    Started by stanford, 20th July 2018 23:10
    • Replies: 4
    • Views: 175
    Today, 08:04 Go to last post
  4. RTL auto code generation

    Started by ctzof, 21st July 2018 13:20
    • Replies: 3
    • Views: 231
    Yesterday, 16:49 Go to last post
  5. DFT command operation doubt

    Started by Baskar, 14th February 2018 13:29
    • Replies: 2
    • Views: 611
    20th July 2018, 16:53 Go to last post
    • Replies: 2
    • Views: 98
    20th July 2018, 16:48 Go to last post
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  6. difference between priority case and case

    Started by stanford, 19th July 2018 23:15
    • Replies: 1
    • Views: 93
    20th July 2018, 01:12 Go to last post
    • Replies: 4
    • Views: 201
    18th July 2018, 19:05 Go to last post
  7. Explain tech file name rule

    Started by faunusest, 18th July 2018 04:02
    • Replies: 1
    • Views: 104
    18th July 2018, 14:12 Go to last post
    • Replies: 1
    • Views: 135
    18th July 2018, 08:13 Go to last post
  8. latency of the dsync output

    Started by stanford, 11th July 2018 19:58
    • Replies: 9
    • Views: 353
    17th July 2018, 19:30 Go to last post
  9. X propagation on input when else is not there

    Started by stanford, 12th July 2018 23:00
    • Replies: 8
    • Views: 348
    17th July 2018, 19:24 Go to last post
  10. lw, sw in a processor

    Started by stanford, 16th July 2018 06:14
    • Replies: 3
    • Views: 209
    17th July 2018, 19:17 Go to last post
  11. TCL Script for adding wires on SoC Encounter

    Started by Mahmoud_Dagher, 17th July 2018 14:49
    • Replies: 0
    • Views: 82
    17th July 2018, 14:49 Go to last post
  12. Comparing two numbers

    Started by Pravesh_Rathee, 11th July 2018 17:54
    • Replies: 12
    • Views: 384
    13th July 2018, 20:29 Go to last post
  13. [SOLVED] Regarding placement legalization in cadence

    Started by pavan muvvala, 12th July 2018 07:45
    • Replies: 3
    • Views: 158
    13th July 2018, 19:47 Go to last post
  14. Parallel Pattern Simulation

    Started by sandy2811, 3rd July 2018 18:28
    • Replies: 4
    • Views: 243
    13th July 2018, 11:39 Go to last post
    • Replies: 2
    • Views: 145
    12th July 2018, 09:27 Go to last post
  15. fifo memory initialization

    Started by stanford, 6th July 2018 23:28
    • Replies: 3
    • Views: 332
    7th July 2018, 20:59 Go to last post
    • Replies: 2
    • Views: 187
    6th July 2018, 01:34 Go to last post
  16. Manual Intentional Routing

    Started by Mahmoud_Dagher, 3rd July 2018 20:01
    • Replies: 5
    • Views: 269
    5th July 2018, 14:12 Go to last post
    • Replies: 1
    • Views: 121
    4th July 2018, 16:51 Go to last post
    • Replies: 4
    • Views: 264
    3rd July 2018, 17:05 Go to last post
  17. Recovery and removal time of async reset

    Started by stanford, 29th June 2018 09:32
    • Replies: 3
    • Views: 255
    2nd July 2018, 22:26 Go to last post