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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,399
    klug
    25th March 2007, 08:41 Go to last post

  1. lw, sw in a processor

    Started by stanford, Yesterday 06:14
    • Replies: 2
    • Views: 103
    stanford
    Yesterday, 22:10 Go to last post

  2. X propagation on input when else is not there

    Started by stanford, 12th July 2018 23:00
    • Replies: 7
    • Views: 229
    dave_59
    Yesterday, 16:44 Go to last post

  3. A Revolutionary Massively Parallel Processing Architecture

    Started by paulpawlenko, 14th July 2018 01:16
    • Replies: 17
    • Views: 576
    paulpawlenko
    Yesterday, 01:05 Go to last post

  4. Comparing two numbers

    Started by Pravesh_Rathee, 11th July 2018 17:54
    • Replies: 12
    • Views: 290
    ads-ee
    13th July 2018, 20:29 Go to last post

  5. [SOLVED] Regarding placement legalization in cadence

    Started by pavan muvvala, 12th July 2018 07:45
    • Replies: 3
    • Views: 120
    ThisIsNotSam
    13th July 2018, 19:47 Go to last post

  6. Parallel Pattern Simulation

    Started by sandy2811, 3rd July 2018 18:28
    • Replies: 4
    • Views: 196
    Adarsh24
    13th July 2018, 11:39 Go to last post

  7. DFT: Simulation of ATPG has mismatches for SDF MTM Spec maximum only.

    Started by Adarsh24, 13th July 2018 08:43
    • Replies: 0
    • Views: 56
    Adarsh24
    13th July 2018, 08:43 Go to last post

  8. latency of the dsync output

    Started by stanford, 11th July 2018 19:58
    • Replies: 8
    • Views: 212
    stanford
    12th July 2018, 22:49 Go to last post

  9. How can we make D flip-flop with clear using 2:1 mux only.

    Started by aincrad, 12th July 2018 06:47
    1 Attachment(s)
    • Replies: 2
    • Views: 116
    aincrad
    12th July 2018, 09:27 Go to last post

  10. Encrypt verilog with ablity to synthesize in cadence tool

    Started by smsskil, 11th July 2018 08:48
    • Replies: 3
    • Views: 107
    pancho_hideboo
    11th July 2018, 12:00 Go to last post

  11. [Moved]: Verilog code to read .txt (hexa value)file and and to store in PC

    Started by vachanukb, 6th July 2018 19:41
    • Replies: 3
    • Views: 273
    dave_59
    9th July 2018, 20:14 Go to last post

  12. [SOLVED] 5 connectivity problems in my ASIC implementation: [The net has an antenna]

    Started by Mahmoud_Dagher, 9th July 2018 15:31
    5 Attachment(s)
    • Replies: 1
    • Views: 147
    ThisIsNotSam
    9th July 2018, 17:27 Go to last post

  13. fifo memory initialization

    Started by stanford, 6th July 2018 23:28
    • Replies: 3
    • Views: 295
    ThisIsNotSam
    7th July 2018, 20:59 Go to last post

  14. which default is taken in a case block inside an always_comb

    Started by stanford, 5th July 2018 22:16
    • Replies: 2
    • Views: 157
    asdf44
    6th July 2018, 01:34 Go to last post

  15. Create Block in innovus to use on other designs

    Started by rmachado, 4th July 2018 17:43
    • Replies: 2
    • Views: 113
    rmachado
    5th July 2018, 14:41 Go to last post

  16. Manual Intentional Routing

    Started by Mahmoud_Dagher, 3rd July 2018 20:01
    • Replies: 5
    • Views: 224
    ThisIsNotSam
    5th July 2018, 14:12 Go to last post

  17. How do I do an ASIC post-synthesis timing simulation in Modelsim for Verilog

    Started by AlexKeys, 4th July 2018 04:25
    • Replies: 2
    • Views: 184
    rmachado
    4th July 2018, 17:57 Go to last post

  18. [SOLVED] Request for Cadance Encounter commands of different violations

    Started by pavan muvvala, 4th July 2018 09:14
    • Replies: 1
    • Views: 101
    ThisIsNotSam
    4th July 2018, 16:51 Go to last post

  19. Synopsys: DC synthesis of design with different clocks

    Started by Vivek2Keviv, 2nd July 2018 22:21
    1 Attachment(s)
    • Replies: 4
    • Views: 232
    ThisIsNotSam
    3rd July 2018, 17:05 Go to last post

  20. Recovery and removal time of async reset

    Started by stanford, 29th June 2018 09:32
    • Replies: 3
    • Views: 225
    FvM
    2nd July 2018, 22:26 Go to last post

  21. What is attenuation of a signal through an ideal channel (FR4) in a chip-to-chip link

    Started by bit_an, 1st July 2018 10:57
    • Replies: 0
    • Views: 328
    bit_an
    1st July 2018, 10:57 Go to last post

  22. Variable in Design Compiler for clock gating

    Started by aditya1579, 22nd June 2018 10:57
    • Replies: 9
    • Views: 549
    jbeniston
    29th June 2018, 15:58 Go to last post

  23. 2-Gbit Parallel NOR Flash PC28F00BM29EWHA replacement...

    Started by e-music, 28th June 2018 21:52
    1 Attachment(s)
    • Replies: 0
    • Views: 143
    e-music
    28th June 2018, 21:52 Go to last post

  24. [SOLVED] Layout filemerge problem

    Started by Mahmoud_Dagher, 28th June 2018 14:18
    • Replies: 1
    • Views: 143
    ThisIsNotSam
    28th June 2018, 16:10 Go to last post

  25. Script for adding wires in Encounter

    Started by Mahmoud_Dagher, 19th June 2018 03:10
    • Replies: 5
    • Views: 272
    Mahmoud_Dagher
    28th June 2018, 12:11 Go to last post

  26. TSMC and spice model of library cells

    Started by nka, 27th June 2018 01:27
    • Replies: 5
    • Views: 302
    ThisIsNotSam
    27th June 2018, 20:18 Go to last post

  27. Prime Time mismatch on get_timing_paths and report_cell

    Started by matteof93, 26th June 2018 00:36
    • Replies: 7
    • Views: 325
    ThisIsNotSam
    27th June 2018, 20:16 Go to last post

  28. Clock slew and data slew

    Started by sjt1003, 22nd June 2018 05:52
    • Replies: 1
    • Views: 203
    ktr
    26th June 2018, 16:26 Go to last post

  29. modelsim simulation after syntesis

    Started by carmeloA, 25th June 2018 09:15
    • Replies: 3
    • Views: 200
    ThisIsNotSam
    25th June 2018, 15:01 Go to last post

  30. [SOLVED] FSM output function of the encoded states

    Started by carmeloA, 24th June 2018 12:03
    • Replies: 2
    • Views: 265
    carmeloA
    25th June 2018, 09:22 Go to last post
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