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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,771
    25th March 2007, 08:41 Go to last post
  1. I2C not working properly

    Started by rmachado, 2nd September 2019 14:39
    2 Pages
    1 2
    • Replies: 20
    • Views: 819
    14th September 2019, 20:36 Go to last post
    • Replies: 3
    • Views: 207
    14th September 2019, 11:56 Go to last post
  2. scan chain inside memory

    Started by fragnen, 13th September 2019 09:19
    • Replies: 3
    • Views: 151
    13th September 2019, 11:46 Go to last post
  3. Overwrite cell delay.

    Started by Yussef, 11th September 2019 13:46
    • Replies: 4
    • Views: 228
    12th September 2019, 14:04 Go to last post
  4. SAIF file generation in VCS tool

    Started by maru2488, 6th September 2019 10:23
    • Replies: 0
    • Views: 190
    6th September 2019, 10:23 Go to last post
    • Replies: 1
    • Views: 224
    6th September 2019, 06:55 Go to last post
  5. Inducing delays in WGL files

    Started by tahirsengine, 5th September 2019 14:17
    • Replies: 0
    • Views: 159
    5th September 2019, 14:17 Go to last post
  6. Warnings in nano route in innovus

    Started by Chinmaye, 5th September 2019 11:18
    • Replies: 1
    • Views: 152
    5th September 2019, 12:06 Go to last post
  7. DFT- Circuit Netlist

    Started by avinashkumar, 1st September 2019 15:57
    • Replies: 2
    • Views: 338
    5th September 2019, 03:53 Go to last post
  8. vcd file generation for netlist

    Started by maru2488, 4th September 2019 07:19
    • Replies: 1
    • Views: 156
    4th September 2019, 09:43 Go to last post
  9. Using multilayer AHB-Lite

    Started by Haraldovs, 3rd September 2019 11:27
    • Replies: 3
    • Views: 264
    4th September 2019, 08:23 Go to last post
    • Replies: 3
    • Views: 411
    4th September 2019, 07:26 Go to last post
  10. Different ways of reading design in ICC

    Started by Dan_Yang, 2nd September 2019 16:14
    • Replies: 2
    • Views: 199
    3rd September 2019, 14:45 Go to last post
  11. Time Constraints in Placement

    Started by Dan_Yang, 2nd September 2019 16:19
    • Replies: 2
    • Views: 262
    3rd September 2019, 12:07 Go to last post
  12. SRAM1RW512x32 module for PULPino microprocessor

    Started by Abdo_Mgdy, 1st September 2019 10:05
    • Replies: 0
    • Views: 128
    1st September 2019, 10:05 Go to last post
  13. Difference between mebes & Job Deck

    Started by RohithRaj, 31st August 2019 17:02
    • Replies: 0
    • Views: 147
    31st August 2019, 17:02 Go to last post
    • Replies: 3
    • Views: 289
    31st August 2019, 08:19 Go to last post
  14. [SOLVED] [moved] Routing signal like clock tree in Cadence Encounter

    Started by Abdo_Mgdy, 27th August 2019 13:40
    • Replies: 3
    • Views: 285
    31st August 2019, 08:18 Go to last post
  15. power analysis using synopsys DC compiler

    Started by avishek_sinha_roy, 28th August 2019 19:03
    • Replies: 5
    • Views: 371
    30th August 2019, 11:54 Go to last post
  16. Beginning and end of a time step

    Started by stanford, 22nd August 2019 02:59
    • Replies: 11
    • Views: 749
    29th August 2019, 07:29 Go to last post
  17. Verifying Large ASIC

    Started by khtsoi, 26th August 2019 14:55
    • Replies: 6
    • Views: 573
    28th August 2019, 07:58 Go to last post
  18. AMBA AXI AxLOCK brief

    Started by surerdra, 27th August 2019 05:27
    • Replies: 1
    • Views: 252
    27th August 2019, 16:01 Go to last post
  19. For doing ECO on netlist

    Started by fragnen, 26th August 2019 08:16
    • Replies: 7
    • Views: 406
    27th August 2019, 10:03 Go to last post
    • Replies: 0
    • Views: 251
    23rd August 2019, 14:51 Go to last post
  20. Lockup Latch for DFT purpose

    Started by Varun124, 3rd July 2019 19:34
    • Replies: 1
    • Views: 277
    21st August 2019, 18:52 Go to last post
  21. Serial scan patterns are failing

    Started by praveenb824, 21st August 2019 07:20
    • Replies: 1
    • Views: 214
    21st August 2019, 16:06 Go to last post
  22. LEC between two netlists

    Started by fragnen, 20th August 2019 13:22
    • Replies: 3
    • Views: 326
    21st August 2019, 13:58 Go to last post
  23. Working with multible libraries in Modelsim

    Started by javierh.santiago, 19th August 2019 20:04
    • Replies: 1
    • Views: 213
    20th August 2019, 02:16 Go to last post