1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    108,814
Page 1 of 802 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24054

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,399
    25th March 2007, 08:41 Go to last post
  1. lw, sw in a processor

    Started by stanford, Yesterday 06:14
    • Replies: 2
    • Views: 103
    Yesterday, 22:10 Go to last post
  2. X propagation on input when else is not there

    Started by stanford, 12th July 2018 23:00
    • Replies: 7
    • Views: 229
    Yesterday, 16:44 Go to last post
  3. Comparing two numbers

    Started by Pravesh_Rathee, 11th July 2018 17:54
    • Replies: 12
    • Views: 290
    13th July 2018, 20:29 Go to last post
  4. [SOLVED] Regarding placement legalization in cadence

    Started by pavan muvvala, 12th July 2018 07:45
    • Replies: 3
    • Views: 120
    13th July 2018, 19:47 Go to last post
  5. Parallel Pattern Simulation

    Started by sandy2811, 3rd July 2018 18:28
    • Replies: 4
    • Views: 196
    13th July 2018, 11:39 Go to last post
    • Replies: 0
    • Views: 56
    13th July 2018, 08:43 Go to last post
  6. latency of the dsync output

    Started by stanford, 11th July 2018 19:58
    • Replies: 8
    • Views: 212
    12th July 2018, 22:49 Go to last post
    • Replies: 2
    • Views: 116
    12th July 2018, 09:27 Go to last post
  7. fifo memory initialization

    Started by stanford, 6th July 2018 23:28
    • Replies: 3
    • Views: 295
    7th July 2018, 20:59 Go to last post
    • Replies: 2
    • Views: 157
    6th July 2018, 01:34 Go to last post
  8. Create Block in innovus to use on other designs

    Started by rmachado, 4th July 2018 17:43
    • Replies: 2
    • Views: 113
    5th July 2018, 14:41 Go to last post
  9. Manual Intentional Routing

    Started by Mahmoud_Dagher, 3rd July 2018 20:01
    • Replies: 5
    • Views: 224
    5th July 2018, 14:12 Go to last post
    • Replies: 1
    • Views: 101
    4th July 2018, 16:51 Go to last post
    • Replies: 4
    • Views: 232
    3rd July 2018, 17:05 Go to last post
  10. Recovery and removal time of async reset

    Started by stanford, 29th June 2018 09:32
    • Replies: 3
    • Views: 225
    2nd July 2018, 22:26 Go to last post
  11. Variable in Design Compiler for clock gating

    Started by aditya1579, 22nd June 2018 10:57
    • Replies: 9
    • Views: 549
    29th June 2018, 15:58 Go to last post
    • Replies: 0
    • Views: 143
    28th June 2018, 21:52 Go to last post
  12. [SOLVED] Layout filemerge problem

    Started by Mahmoud_Dagher, 28th June 2018 14:18
    • Replies: 1
    • Views: 143
    28th June 2018, 16:10 Go to last post
  13. Script for adding wires in Encounter

    Started by Mahmoud_Dagher, 19th June 2018 03:10
    • Replies: 5
    • Views: 272
    28th June 2018, 12:11 Go to last post
  14. TSMC and spice model of library cells

    Started by nka, 27th June 2018 01:27
    • Replies: 5
    • Views: 302
    27th June 2018, 20:18 Go to last post
    • Replies: 7
    • Views: 325
    27th June 2018, 20:16 Go to last post
  15. Clock slew and data slew

    Started by sjt1003, 22nd June 2018 05:52
    • Replies: 1
    • Views: 203
    26th June 2018, 16:26 Go to last post
  16. modelsim simulation after syntesis

    Started by carmeloA, 25th June 2018 09:15
    • Replies: 3
    • Views: 200
    25th June 2018, 15:01 Go to last post
  17. [SOLVED] FSM output function of the encoded states

    Started by carmeloA, 24th June 2018 12:03
    • Replies: 2
    • Views: 265
    25th June 2018, 09:22 Go to last post