1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    110,832
Page 1 of 805 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24136

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,550
    25th March 2007, 08:41 Go to last post
  1. Timing Budgeting between Blocks

    Started by GDesign, Today 12:08
    • Replies: 5
    • Views: 98
    Today, 17:10 Go to last post
    • Replies: 2
    • Views: 107
    Yesterday, 17:54 Go to last post
    • Replies: 6
    • Views: 209
    Yesterday, 13:05 Go to last post
  2. How crosstalk is reduced by shield net ??

    Started by tejthammic, 17th September 2018 15:26
    • Replies: 1
    • Views: 118
    17th September 2018, 18:10 Go to last post
  3. Regarding MTech thesis topic in Verilog in frontend

    Started by edeepak93, 16th September 2018 12:54
    • Replies: 1
    • Views: 134
    16th September 2018, 14:22 Go to last post
  4. Characterizing cells with verilog-A models for components

    Started by frasheed, 15th September 2018 15:00
    • Replies: 1
    • Views: 142
    15th September 2018, 17:41 Go to last post
  5. Innovus (SoC Encounter) Post Layout Power Estimation

    Started by ranaya, 13th September 2018 10:47
    • Replies: 5
    • Views: 219
    14th September 2018, 16:07 Go to last post
  6. Tools for DFT (SCAN insertion and ATPG)

    Started by kimthanhvu178, 13th September 2018 09:06
    • Replies: 0
    • Views: 70
    13th September 2018, 09:06 Go to last post
  7. .lib internal_power question

    Started by hznichol, 13th September 2018 02:20
    • Replies: 1
    • Views: 117
    13th September 2018, 06:59 Go to last post
  8. Endcap and Decap Usage in P&R

    Started by ranaya, 12th September 2018 14:53
    • Replies: 3
    • Views: 145
    12th September 2018, 17:55 Go to last post
    • Replies: 1
    • Views: 369
    11th September 2018, 00:42 Go to last post
  9. How to use Synopsys saed 28/32 technology file

    Started by jcll, 10th September 2018 19:33
    • Replies: 1
    • Views: 99
    11th September 2018, 00:41 Go to last post
    • Replies: 7
    • Views: 443
    10th September 2018, 21:34 Go to last post
  10. why does power no longer scale with technology?

    Started by kaushikrvs, 9th September 2018 23:14
    • Replies: 3
    • Views: 230
    10th September 2018, 17:44 Go to last post
  11. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 1
    • Views: 156
    8th September 2018, 16:02 Go to last post
  12. Query regarding Physical design flow

    Started by ajayg0880, 8th September 2018 07:28
    • Replies: 1
    • Views: 106
    8th September 2018, 16:01 Go to last post
    • Replies: 1
    • Views: 138
    8th September 2018, 16:00 Go to last post
  13. Different types of pads in VLSI?

    Started by maniroop, 6th September 2018 06:17
    • Replies: 1
    • Views: 230
    6th September 2018, 13:29 Go to last post
  14. What does this assignment mean?

    Started by rmk423, 3rd September 2018 08:34
    • Replies: 3
    • Views: 314
    5th September 2018, 06:34 Go to last post
  15. [LEC] Why needed in ASIC flow?

    Started by ivlsi, 23rd August 2018 19:16
    • Replies: 10
    • Views: 589
    4th September 2018, 01:52 Go to last post
  16. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 2
    • Views: 196
    31st August 2018, 07:37 Go to last post
    • Replies: 3
    • Views: 219
    30th August 2018, 04:49 Go to last post
    • Replies: 0
    • Views: 160
    28th August 2018, 19:42 Go to last post
  17. what is the usage of the port in the fpga?

    Started by liletian, 28th August 2018 19:12
    • Replies: 1
    • Views: 119
    28th August 2018, 19:20 Go to last post
  18. Timing Checks in primetime

    Started by kishoresai1996, 27th August 2018 10:39
    • Replies: 3
    • Views: 219
    28th August 2018, 14:20 Go to last post
    • Replies: 4
    • Views: 318
    28th August 2018, 14:19 Go to last post
  19. How to find min setup time from DB

    Started by ckdrv, 27th August 2018 18:12
    • Replies: 0
    • Views: 130
    27th August 2018, 18:12 Go to last post
  20. How do I synthesize an inout port using DC?

    Started by kos8108, 27th August 2018 14:55
    • Replies: 0
    • Views: 82
    27th August 2018, 14:55 Go to last post