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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,784
    klug
    25th March 2007, 08:41 Go to last post

  1. Problem adding reset to master slave D-FF for phase detector

    Started by yefj, 13th September 2019 12:46
    12 Attachment(s)
    • Replies: 5
    • Views: 276
    FvM
    Today, 18:33 Go to last post

  2. Gate Level Simulation

    Started by fragnen, Yesterday 10:13
    • Replies: 3
    • Views: 180
    pancho_hideboo
    Today, 14:15 Go to last post

  3. vcd file generation for netlist

    Started by maru2488, 4th September 2019 07:19
    • Replies: 2
    • Views: 182
    vipul982
    Today, 12:45 Go to last post

  4. The collection of VLSI/ASIC logic design interview questions

    Started by vlsifaq, 23rd August 2019 14:51
    • Replies: 1
    • Views: 282
    vlsifaq
    Today, 11:27 Go to last post

  5. Lockup Latch for DFT purpose

    Started by Varun124, 3rd July 2019 19:34
    • Replies: 5
    • Views: 378
    TonyLS
    Yesterday, 16:50 Go to last post

  6. scan chain inside memory

    Started by fragnen, 13th September 2019 09:19
    • Replies: 4
    • Views: 218
    anuraagkn
    Yesterday, 12:32 Go to last post

  7. I2C not working properly

    Started by rmachado, 2nd September 2019 14:39
    2 Pages •
    1 2
    7 Attachment(s)
    • Replies: 20
    • Views: 968
    vGoodtimes
    14th September 2019, 20:36 Go to last post

  8. Overwrite cell delay.

    Started by Yussef, 11th September 2019 13:46
    • Replies: 4
    • Views: 252
    Yussef
    12th September 2019, 14:04 Go to last post

  9. How to fix errors in lint summary (check_timing_intent) during synthesis in Genus?

    Started by asic_architect, 8th September 2019 04:25
    • Replies: 3
    • Views: 328
    ThisIsNotSam
    9th September 2019, 08:37 Go to last post

  10. How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retiming.

    Started by asic_architect, 31st August 2019 23:13
    • Replies: 10
    • Views: 555
    ThisIsNotSam
    8th September 2019, 07:48 Go to last post

  11. SAIF file generation in VCS tool

    Started by maru2488, 6th September 2019 10:23
    • Replies: 0
    • Views: 200
    maru2488
    6th September 2019, 10:23 Go to last post

  12. Trends and Relationships with Threshold Voltages and Liberty Files

    Started by janthonym, 5th September 2019 21:13
    • Replies: 1
    • Views: 235
    ThisIsNotSam
    6th September 2019, 06:55 Go to last post

  13. Inducing delays in WGL files

    Started by tahirsengine, 5th September 2019 14:17
    • Replies: 0
    • Views: 174
    tahirsengine
    5th September 2019, 14:17 Go to last post

  14. Warnings in nano route in innovus

    Started by Chinmaye, 5th September 2019 11:18
    • Replies: 1
    • Views: 159
    ThisIsNotSam
    5th September 2019, 12:06 Go to last post

  15. DFT- Circuit Netlist

    Started by avinashkumar, 1st September 2019 15:57
    • Replies: 2
    • Views: 351
    avinashkumar
    5th September 2019, 03:53 Go to last post

  16. Using multilayer AHB-Lite

    Started by Haraldovs, 3rd September 2019 11:27
    • Replies: 3
    • Views: 275
    dpaul
    4th September 2019, 08:23 Go to last post

  17. large slack (Reg2Reg) after placement (IC Compiler & Physical design)

    Started by Dan_Yang, 2nd September 2019 16:30
    • Replies: 3
    • Views: 426
    ThisIsNotSam
    4th September 2019, 07:26 Go to last post

  18. Different ways of reading design in ICC

    Started by Dan_Yang, 2nd September 2019 16:14
    • Replies: 2
    • Views: 206
    Dan_Yang
    3rd September 2019, 14:45 Go to last post

  19. Time Constraints in Placement

    Started by Dan_Yang, 2nd September 2019 16:19
    • Replies: 2
    • Views: 270
    ThisIsNotSam
    3rd September 2019, 12:07 Go to last post

  20. SRAM1RW512x32 module for PULPino microprocessor

    Started by Abdo_Mgdy, 1st September 2019 10:05
    • Replies: 0
    • Views: 131
    Abdo_Mgdy
    1st September 2019, 10:05 Go to last post

  21. Difference between mebes & Job Deck

    Started by RohithRaj, 31st August 2019 17:02
    • Replies: 0
    • Views: 151
    RohithRaj
    31st August 2019, 17:02 Go to last post

  22. [moved] Adding lockup latches manually in Cadence Encounter

    Started by Abdo_Mgdy, 27th August 2019 13:37
    • Replies: 3
    • Views: 300
    ThisIsNotSam
    31st August 2019, 08:19 Go to last post

  23. [SOLVED] [moved] Routing signal like clock tree in Cadence Encounter

    Started by Abdo_Mgdy, 27th August 2019 13:40
    • Replies: 3
    • Views: 295
    ThisIsNotSam
    31st August 2019, 08:18 Go to last post

  24. power analysis using synopsys DC compiler

    Started by avishek_sinha_roy, 28th August 2019 19:03
    • Replies: 5
    • Views: 386
    avishek_sinha_roy
    30th August 2019, 11:54 Go to last post

  25. Beginning and end of a time step

    Started by stanford, 22nd August 2019 02:59
    • Replies: 11
    • Views: 773
    dave_59
    29th August 2019, 07:29 Go to last post

  26. Verifying Large ASIC

    Started by khtsoi, 26th August 2019 14:55
    • Replies: 6
    • Views: 591
    ThisIsNotSam
    28th August 2019, 07:58 Go to last post

  27. AMBA AXI AxLOCK brief

    Started by surerdra, 27th August 2019 05:27
    • Replies: 1
    • Views: 255
    ads-ee
    27th August 2019, 16:01 Go to last post

  28. For doing ECO on netlist

    Started by fragnen, 26th August 2019 08:16
    • Replies: 7
    • Views: 428
    dpaul
    27th August 2019, 10:03 Go to last post

  29. Serial scan patterns are failing

    Started by praveenb824, 21st August 2019 07:20
    • Replies: 1
    • Views: 218
    TonyLS
    21st August 2019, 16:06 Go to last post

  30. LEC between two netlists

    Started by fragnen, 20th August 2019 13:22
    • Replies: 3
    • Views: 334
    TonyLS
    21st August 2019, 13:58 Go to last post
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