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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,702
    klug
    25th March 2007, 08:41 Go to last post

  1. Pico second precision up counter

    Started by npsnpsnps, 14th November 2018 12:21
    • Replies: 8
    • Views: 403
    ThisIsNotSam
    Yesterday, 21:48 Go to last post

  2. I have a Micro Code design assignment, how to proceed?

    Started by kaushikrvs, 17th November 2018 20:51
    • Replies: 1
    • Views: 255
    ThisIsNotSam
    18th November 2018, 15:51 Go to last post

  3. What are the normal tricks to closing time in rc and encounter?

    Started by liletian, 13th November 2018 18:56
    • Replies: 1
    • Views: 177
    ThisIsNotSam
    15th November 2018, 03:17 Go to last post

  4. How does variable bit shift operation get synthesize in hw?

    Started by stanford, 14th November 2018 04:37
    • Replies: 1
    • Views: 191
    FvM
    14th November 2018, 09:05 Go to last post

  5. Ringing between pads and digital inputs?

    Started by Alexxk, 13th November 2018 08:28
    • Replies: 4
    • Views: 198
    dick_freebird
    13th November 2018, 18:50 Go to last post

  6. What does this mean in standard cell library?

    Started by liletian, 13th November 2018 07:14
    • Replies: 1
    • Views: 120
    oratie
    13th November 2018, 08:32 Go to last post

  7. Prime Time power estimation whith .spef file

    Started by jmaileh.b, 12th November 2018 08:00
    • Replies: 0
    • Views: 129
    jmaileh.b
    12th November 2018, 08:00 Go to last post

  8. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 5
    • Views: 517
    kumar_eee
    10th November 2018, 17:51 Go to last post

  9. How do I synthesize an inout port using DC?

    Started by kos8108, 27th August 2018 14:55
    • Replies: 1
    • Views: 226
    TonyLS
    9th November 2018, 21:41 Go to last post

  10. Logic Path Activation Probability Depending on Input Data Pattern

    Started by ranaya, 9th November 2018 12:12
    • Replies: 1
    • Views: 208
    ThisIsNotSam
    9th November 2018, 15:22 Go to last post

  11. what is the usage of the port in the fpga?

    Started by liletian, 28th August 2018 19:12
    • Replies: 4
    • Views: 358
    dpaul
    9th November 2018, 10:26 Go to last post

  12. CUVMUR error for VHDL code and Verilog testbench

    Started by shreyakishore, 6th November 2018 21:22
    5 Attachment(s)
    • Replies: 3
    • Views: 191
    FvM
    8th November 2018, 08:35 Go to last post

  13. SiliconSmart set_config_opt for individual bus pins

    Started by jiminization, 8th November 2018 07:21
    • Replies: 0
    • Views: 80
    jiminization
    8th November 2018, 07:21 Go to last post

  14. What does this mean in RC?

    Started by liletian, 6th November 2018 01:17
    • Replies: 6
    • Views: 367
    liletian
    7th November 2018, 23:46 Go to last post

  15. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 3
    • Views: 342
    TonyLS
    6th November 2018, 22:32 Go to last post

  16. Bottom up synthesis using dc compiler

    Started by IngleA, 23rd October 2018 18:45
    2 Attachment(s)
    • Replies: 1
    • Views: 160
    TonyLS
    6th November 2018, 22:25 Go to last post

  17. SiliconSmart Multi-Bit definition

    Started by jiminization, 6th November 2018 12:00
    • Replies: 0
    • Views: 92
    jiminization
    6th November 2018, 12:00 Go to last post

  18. How to fix setup timing violations for a design with high speed clock?

    Started by kurax, 31st October 2018 13:45
    • Replies: 6
    • Views: 344
    ThisIsNotSam
    5th November 2018, 21:30 Go to last post

  19. [SOLVED] Parasitic Extraction for New Standard Cells

    Started by ranaya, 5th November 2018 10:23
    • Replies: 0
    • Views: 133
    ranaya
    5th November 2018, 10:23 Go to last post

  20. SiliconSmart clock gating cells

    Started by jiminization, 5th November 2018 04:51
    • Replies: 0
    • Views: 93
    jiminization
    5th November 2018, 04:51 Go to last post

  21. What are the port in the digital design?

    Started by liletian, 3rd November 2018 03:09
    • Replies: 2
    • Views: 293
    timof
    4th November 2018, 01:57 Go to last post

  22. Bencmakrak Circuits - Verilog Netlis

    Started by frasheed, 3rd November 2018 15:23
    • Replies: 3
    • Views: 195
    dave_59
    3rd November 2018, 19:19 Go to last post

  23. Which is more susceptible to variation, HVT or LVT?

    Started by kyon_lee, 2nd November 2018 00:52
    • Replies: 2
    • Views: 194
    dick_freebird
    2nd November 2018, 17:34 Go to last post

  24. port CLASS BUMP in output LEF

    Started by alphus, 29th October 2018 11:18
    • Replies: 5
    • Views: 277
    ThisIsNotSam
    2nd November 2018, 14:22 Go to last post

  25. [SOLVED] How to define SDC constraints for two clock domains fed by single source?

    Started by Pramod_B, 31st October 2018 07:44
    1 Attachment(s)
    • Replies: 15
    • Views: 571
    dpaul
    2nd November 2018, 10:43 Go to last post

  26. Converting Synopsys SAED32nm EDK .tf file into .lef file

    Started by dlvalencia, 31st October 2018 19:53
    • Replies: 3
    • Views: 213
    ThisIsNotSam
    2nd November 2018, 00:34 Go to last post

  27. Static & Dynamic IR analysis operating conditions

    Started by sdbot, 23rd September 2018 23:55
    • Replies: 4
    • Views: 434
    kayexu
    1st November 2018, 16:47 Go to last post

  28. SiliconSmart Import Errors

    Started by jiminization, 30th October 2018 10:17
    • Replies: 1
    • Views: 153
    ThisIsNotSam
    31st October 2018, 15:38 Go to last post

  29. Layers for blocking metal auto fill in TSMC

    Started by Potatoze, 30th October 2018 23:15
    • Replies: 2
    • Views: 187
    ThisIsNotSam
    31st October 2018, 15:31 Go to last post

  30. Format of CDL netlist

    Started by joharali, 31st October 2018 15:09
    • Replies: 0
    • Views: 125
    joharali
    31st October 2018, 15:09 Go to last post
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