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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 33,429
    25th March 2007, 08:41 Go to last post
  1. Metastabilty and data loss

    Started by sherline123, 5th December 2019 15:58
    • Replies: 7
    • Views: 205
    Today, 15:13 Go to last post
    • Replies: 0
    • Views: 136
    Yesterday, 11:44 Go to last post
  2. How hold violation caused by below mentioned Scenceio

    Started by Varun124, 6th December 2019 14:06
    • Replies: 1
    • Views: 134
    6th December 2019, 20:21 Go to last post
    • Replies: 1
    • Views: 145
    6th December 2019, 16:13 Go to last post
  3. Timing ARC for Asynchronous Signal

    Started by Varun124, 4th December 2019 21:09
    • Replies: 3
    • Views: 241
    6th December 2019, 09:26 Go to last post
  4. Getting connectivity information from fsdb file

    Started by tomer, 5th December 2019 09:26
    • Replies: 1
    • Views: 137
    5th December 2019, 12:39 Go to last post
  5. [SOLVED] Why remove scan chain before the placement?

    Started by akhil_psm, 2nd December 2019 17:42
    • Replies: 3
    • Views: 235
    4th December 2019, 08:11 Go to last post
  6. Creating Power ring around macros

    Started by blue1, 3rd December 2019 09:05
    • Replies: 1
    • Views: 101
    3rd December 2019, 10:58 Go to last post
  7. MBIST DONE & GO failing conditions

    Started by vipul982, 6th November 2019 14:13
    • Replies: 2
    • Views: 353
    3rd December 2019, 09:29 Go to last post
  8. Leakge current in low Vt cells

    Started by riti, 2nd December 2019 21:06
    • Replies: 2
    • Views: 178
    3rd December 2019, 08:06 Go to last post
  9. ATPG stuff, tell me what you think

    Started by firewireblue, 30th November 2019 00:04
    • Replies: 3
    • Views: 269
    2nd December 2019, 10:19 Go to last post
    • Replies: 2
    • Views: 247
    2nd December 2019, 10:17 Go to last post
    • Replies: 2
    • Views: 489
    2nd December 2019, 10:15 Go to last post
  10. DDR4 SDRAM test signal is abnormal

    Started by williamli186, 27th November 2019 12:03
    • Replies: 0
    • Views: 241
    27th November 2019, 12:03 Go to last post
  11. Use of Cascaded Dividers in the Design

    Started by Varun124, 27th November 2019 06:57
    • Replies: 0
    • Views: 344
    27th November 2019, 06:57 Go to last post
  12. Using a BFM in system verification code.

    Started by dipk11, 15th November 2019 07:49
    • Replies: 7
    • Views: 552
    26th November 2019, 07:34 Go to last post
  13. Clock divider circuit

    Started by promach, 24th November 2019 05:39
    • Replies: 2
    • Views: 358
    25th November 2019, 12:04 Go to last post
    • Replies: 1
    • Views: 260
    25th November 2019, 08:44 Go to last post
  14. Why CTS in physical design?

    Started by Dan_Yang, 24th November 2019 16:09
    • Replies: 1
    • Views: 255
    25th November 2019, 08:43 Go to last post
    • Replies: 5
    • Views: 486
    22nd November 2019, 10:18 Go to last post
  15. [moved] How to detect the faulty flop in scan chain

    Started by Sunilverma03, 21st November 2019 05:33
    • Replies: 0
    • Views: 214
    21st November 2019, 05:33 Go to last post
    • Replies: 2
    • Views: 268
    21st November 2019, 03:36 Go to last post
  16. SystemVerilog Interface signal assignment

    Started by ghertz, 18th November 2019 17:30
    • Replies: 2
    • Views: 241
    18th November 2019, 23:46 Go to last post
    • Replies: 2
    • Views: 247
    18th November 2019, 23:09 Go to last post
  17. DFT Visualizer Data View

    Started by Vignesh_J, 15th November 2019 13:24
    • Replies: 2
    • Views: 319
    18th November 2019, 08:03 Go to last post
  18. How to find the operating frequency for an ASIC?

    Started by daskk62, 17th November 2019 19:18
    • Replies: 2
    • Views: 225
    17th November 2019, 22:51 Go to last post
  19. How to generate sine wave using Verilog?

    Started by h_upadhyay, 9th November 2019 06:59
    • Replies: 9
    • Views: 734
    16th November 2019, 15:03 Go to last post
  20. max_transition Violation

    Started by vyella1, 13th November 2019 22:17
    • Replies: 1
    • Views: 266
    14th November 2019, 13:29 Go to last post
  21. Synopsys DC: Tracing clock path

    Started by vaibhava, 13th November 2019 08:36
    • Replies: 1
    • Views: 154
    14th November 2019, 13:27 Go to last post