1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    128,076
Page 1 of 819 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24565

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 35,767
    25th March 2007, 08:41 Go to last post
    • Replies: 0
    • Views: 82
    Yesterday, 08:07 Go to last post
  1. ISCAS 89-s38417 testbench required

    Started by tanish, 17th February 2020 04:00
    • Replies: 2
    • Views: 262
    18th February 2020, 13:42 Go to last post
  2. Question about scan pattern simulation

    Started by tpoleped08, 13th February 2020 20:04
    • Replies: 1
    • Views: 261
    14th February 2020, 04:59 Go to last post
  3. Using generate and for loop to index signal name

    Started by stanford, 12th February 2020 22:47
    • Replies: 1
    • Views: 206
    13th February 2020, 01:07 Go to last post
  4. Clock Tree Synthesis

    Started by seahwan95, 11th February 2020 03:26
    • Replies: 1
    • Views: 229
    11th February 2020, 09:36 Go to last post
  5. How to write a 'req' before 'ack' systemverilog assertion?

    Started by ash72, 10th February 2020 21:41
    • Replies: 0
    • Views: 156
    10th February 2020, 21:41 Go to last post
  6. Boundary Cell in Core Chip

    Started by akhil_psm, 9th December 2019 17:50
    • Replies: 2
    • Views: 703
    8th February 2020, 02:05 Go to last post
    • Replies: 1
    • Views: 417
    8th February 2020, 01:46 Go to last post
  7. DFT - unused faults in atpg

    Started by avinashkumar, 5th February 2020 18:34
    • Replies: 0
    • Views: 211
    5th February 2020, 18:34 Go to last post
  8. [SOLVED] CDC RTL Simulation vs non-CDC RTL Simulation

    Started by kungchuking, 31st December 2019 16:05
    • Replies: 2
    • Views: 480
    5th February 2020, 15:46 Go to last post
  9. [SOLVED] DFT Compiler: Clock pin not active when scan clock is on

    Started by kungchuking, 31st January 2020 06:06
    • Replies: 4
    • Views: 477
    5th February 2020, 15:41 Go to last post
  10. [SOLVED] Design not simulating for different technology node

    Started by vyella1, 3rd February 2020 17:19
    • Replies: 3
    • Views: 1,602
    4th February 2020, 23:34 Go to last post
  11. Input/Inout Pin Capacitance Attributes

    Started by janthonym, 4th February 2020 17:49
    • Replies: 1
    • Views: 171
    4th February 2020, 18:37 Go to last post
    • Replies: 2
    • Views: 303
    30th January 2020, 08:04 Go to last post
    • Replies: 0
    • Views: 267
    29th January 2020, 03:57 Go to last post
  12. Interface Logic Model in Synosys is obsolete

    Started by ldhung, 22nd January 2020 13:35
    • Replies: 2
    • Views: 518
    26th January 2020, 10:56 Go to last post
  13. [ Describing PG Pins at RTL Level UPF ]

    Started by whizkid123, 23rd January 2020 07:49
    • Replies: 1
    • Views: 300
    23rd January 2020, 08:31 Go to last post
  14. DFT Reset Constraints Handling in Spyglass DFT SGDC

    Started by whizkid123, 14th January 2020 08:58
    • Replies: 2
    • Views: 729
    17th January 2020, 06:47 Go to last post
  15. Verdi: Assertion debug mode question

    Started by swabhi812, 15th January 2020 00:02
    • Replies: 0
    • Views: 349
    15th January 2020, 00:02 Go to last post
  16. Why not simulate ATPG pattern in ATPG TetraMAX tool

    Started by abgohil013, 17th December 2019 11:05
    • Replies: 4
    • Views: 796
    14th January 2020, 09:53 Go to last post
  17. Why we insert Mbist before scan ?

    Started by alp507, 3rd January 2020 05:52
    • Replies: 4
    • Views: 617
    14th January 2020, 09:02 Go to last post
  18. Innovus CTS .tcl Script Qustions

    Started by EEPuppyPuppy, 16th December 2019 22:12
    • Replies: 5
    • Views: 1,078
    14th January 2020, 08:20 Go to last post
  19. Innovus Command Questions

    Started by EEPuppyPuppy, 13th January 2020 23:22
    • Replies: 1
    • Views: 339
    14th January 2020, 08:19 Go to last post
  20. Synopsys TetraMax ATPG B16-1 and B12-1 Error

    Started by ibtesam90, 13th January 2020 16:57
    • Replies: 0
    • Views: 270
    13th January 2020, 16:57 Go to last post
  21. Understanding LVS results (hierarchical)

    Started by aditya1579, 12th January 2020 08:31
    • Replies: 2
    • Views: 470
    13th January 2020, 04:27 Go to last post
  22. Smaller die size by tighter SPICE corners?

    Started by Macduff, 8th January 2020 11:05
    • Replies: 4
    • Views: 508
    10th January 2020, 19:24 Go to last post
  23. [SOLVED] Short violations in Innovus (due to special route)

    Started by Fati_hv, 9th January 2020 11:19
    • Replies: 4
    • Views: 582
    10th January 2020, 17:30 Go to last post
  24. Does Opentimer tool for STA support VHDL netlist

    Started by garvind25, 6th January 2020 19:37
    • Replies: 2
    • Views: 494
    8th January 2020, 08:19 Go to last post
  25. DIE Size calculations in TSMC22ULL GF""FDX

    Started by Elec Singh, 8th January 2020 01:13
    • Replies: 1
    • Views: 301
    8th January 2020, 08:17 Go to last post