1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    111,846
Page 1 of 806 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24169

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,622
    25th March 2007, 08:41 Go to last post
  1. Static & Dynamic IR analysis operating conditions

    Started by sdbot, 23rd September 2018 23:55
    • Replies: 3
    • Views: 220
    Today, 08:59 Go to last post
  2. [SOLVED] Bad handle or reference

    Started by ranayehya, Yesterday 22:15
    • Replies: 1
    • Views: 80
    Today, 07:44 Go to last post
    • Replies: 1
    • Views: 132
    17th October 2018, 10:32 Go to last post
    • Replies: 0
    • Views: 81
    17th October 2018, 03:32 Go to last post
  3. [Synopsys VCS] Recommended Materials

    Started by ivlsi, 16th October 2018 17:26
    • Replies: 0
    • Views: 76
    16th October 2018, 17:26 Go to last post
    • Replies: 1
    • Views: 83
    16th October 2018, 13:25 Go to last post
  4. [SOLVED] Hold time violations in post layout simulation (Although STA is fine)

    Started by ranaya, 12th October 2018 10:00
    • Replies: 5
    • Views: 199
    16th October 2018, 12:35 Go to last post
    • Replies: 1
    • Views: 96
    16th October 2018, 08:28 Go to last post
  5. Multi-vth design not performed

    Started by onta00, 15th October 2018 14:28
    • Replies: 4
    • Views: 159
    16th October 2018, 07:10 Go to last post
    • Replies: 3
    • Views: 150
    15th October 2018, 19:19 Go to last post
  6. CMOS inverter output ?

    Started by IngleA, 1st October 2018 18:49
    • Replies: 8
    • Views: 362
    15th October 2018, 18:24 Go to last post
  7. [LEC] Why needed in ASIC flow?

    Started by ivlsi, 23rd August 2018 19:16
    • Replies: 12
    • Views: 894
    15th October 2018, 12:52 Go to last post
  8. Critical Path in a design

    Started by onta00, 11th October 2018 12:06
    • Replies: 4
    • Views: 214
    15th October 2018, 08:07 Go to last post
  9. SYNOPSIS - Clock creation and delivery to submodules

    Started by kls213, 11th October 2018 17:08
    • Replies: 3
    • Views: 222
    15th October 2018, 08:05 Go to last post
  10. [SOLVED] Fatal error while running top module || UVM

    Started by ranayehya, 13th October 2018 18:33
    • Replies: 4
    • Views: 167
    14th October 2018, 19:36 Go to last post
  11. Max capacitance violation on macro clk pin

    Started by shragh, 14th October 2018 08:00
    • Replies: 2
    • Views: 107
    14th October 2018, 19:10 Go to last post
  12. What is going on with my D flip-flop in Hspice?

    Started by Amamiya_Ren, 12th October 2018 14:35
    • Replies: 3
    • Views: 139
    12th October 2018, 14:55 Go to last post
  13. One clock cycle delay for the input data

    Started by riz1679, 12th October 2018 09:54
    • Replies: 1
    • Views: 85
    12th October 2018, 10:04 Go to last post
    • Replies: 3
    • Views: 178
    11th October 2018, 15:11 Go to last post
    • Replies: 0
    • Views: 67
    11th October 2018, 11:41 Go to last post
  14. Closed: Input reference library in synopsys ic compiler tool

    Started by harshahari, 20th April 2018 12:12
    • Replies: 1
    • Views: 375
    11th October 2018, 11:31 Go to last post
    • Replies: 0
    • Views: 45
    11th October 2018, 11:09 Go to last post
  15. Memory BIST insertion Synopsys flow

    Started by shmd19, 10th October 2018 17:05
    • Replies: 0
    • Views: 86
    10th October 2018, 17:05 Go to last post
  16. Cadence ATPG TCL script

    Started by Nitin1245, 5th October 2018 09:39
    • Replies: 4
    • Views: 239
    8th October 2018, 13:30 Go to last post
    • Replies: 1
    • Views: 78
    8th October 2018, 13:28 Go to last post
    • Replies: 1
    • Views: 202
    6th October 2018, 19:01 Go to last post
  17. [SOLVED] QuestaSim / ModelSim fatal error during simulation

    Started by riz1679, 5th October 2018 10:44
    • Replies: 3
    • Views: 132
    5th October 2018, 15:01 Go to last post
    • Replies: 5
    • Views: 426
    4th October 2018, 08:36 Go to last post
  18. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 4
    • Views: 317
    4th October 2018, 08:34 Go to last post