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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,162
    klug
    25th March 2007, 08:41 Go to last post

  1. Logical and physical 0.13 or 0.18 um technology library

    Started by Abdo18, 20th February 2019 20:45
    • Replies: 1
    • Views: 101
    ThisIsNotSam
    Yesterday, 22:10 Go to last post

  2. how does insertion delay affect timing

    Started by stanford, Yesterday 20:02
    • Replies: 1
    • Views: 51
    ThisIsNotSam
    Yesterday, 22:07 Go to last post

  3. Liberate - Custom Cell Characterization

    Started by manpmanp, Yesterday 17:10
    • Replies: 1
    • Views: 35
    ThisIsNotSam
    Yesterday, 19:53 Go to last post

  4. [moved] Area and Gate Equivalent in Leonardo Spectrum Report

    Started by NehaJain1234, 20th February 2019 16:21
    3 Attachment(s)
    • Replies: 5
    • Views: 177
    ThisIsNotSam
    Yesterday, 16:08 Go to last post

  5. rtl code to find the smallest

    Started by stanford, 20th February 2019 08:47
    • Replies: 10
    • Views: 263
    ThisIsNotSam
    21st February 2019, 23:34 Go to last post

  6. Question related to high latency

    Started by kirankumark0489, 19th February 2019 23:34
    • Replies: 3
    • Views: 160
    ThisIsNotSam
    21st February 2019, 23:32 Go to last post

  7. LBIST architecture - Industry standards

    Started by Nanda_DFT, 20th February 2019 06:09
    • Replies: 1
    • Views: 62
    ArakelTheDragon
    21st February 2019, 11:54 Go to last post

  8. Test-per-scan v/s Test-per-clock

    Started by Nanda_DFT, 20th February 2019 06:11
    • Replies: 1
    • Views: 82
    ArakelTheDragon
    21st February 2019, 11:50 Go to last post

  9. On-Chip Clock logic (macros) placement during Testability insertion

    Started by Nanda_DFT, 20th February 2019 06:08
    • Replies: 1
    • Views: 82
    ThisIsNotSam
    20th February 2019, 16:01 Go to last post

  10. Test vector patterns in LEC

    Started by Fati_hv, 20th February 2019 09:40
    • Replies: 0
    • Views: 63
    Fati_hv
    20th February 2019, 09:40 Go to last post

  11. What are common supports in LEC?

    Started by Fati_hv, 20th February 2019 09:12
    • Replies: 0
    • Views: 52
    Fati_hv
    20th February 2019, 09:12 Go to last post

  12. Synopsys Technology File (STF)

    Started by manpmanp, 20th February 2019 09:07
    • Replies: 0
    • Views: 63
    manpmanp
    20th February 2019, 09:07 Go to last post

  13. DFT Scan chain blocking detection

    Started by Nanda_DFT, 20th February 2019 06:04
    • Replies: 0
    • Views: 41
    Nanda_DFT
    20th February 2019, 06:04 Go to last post

  14. [SOLVED] Clock domain crossing problem in DFT

    Started by Nanda_DFT, 19th February 2019 07:06
    • Replies: 2
    • Views: 127
    Nanda_DFT
    20th February 2019, 05:56 Go to last post

  15. What is Tranisition Delay and Path Delay Fault models in DFT ATPG?

    Started by Nanda_DFT, 19th February 2019 07:03
    • Replies: 0
    • Views: 52
    Nanda_DFT
    19th February 2019, 07:03 Go to last post

  16. Post layout delay in cadence

    Started by umaizameh, 14th February 2019 06:53
    • Replies: 7
    • Views: 434
    oratie
    19th February 2019, 06:34 Go to last post

  17. How to Dump e-vcd File in Verilog HDL ?

    Started by sreejeesh_sreedharan, 14th February 2019 08:28
    • Replies: 2
    • Views: 136
    ThisIsNotSam
    14th February 2019, 16:39 Go to last post

  18. Sample files needed for working with Automatic PnR

    Started by LostEagle, 14th February 2019 00:17
    • Replies: 1
    • Views: 115
    ThisIsNotSam
    14th February 2019, 02:05 Go to last post

  19. Timing issues in netlist simualtion - SDF simulation of IP block

    Started by manpmanp, 11th February 2019 16:27
    1 Attachment(s)
    • Replies: 4
    • Views: 208
    manpmanp
    13th February 2019, 09:34 Go to last post

  20. Using SPEF files for STA in INNOVUS

    Started by Windywast, 12th February 2019 01:37
    • Replies: 3
    • Views: 200
    ThisIsNotSam
    12th February 2019, 17:49 Go to last post

  21. Help to synthesize floating point MAC in Design Compiler using DesignWare library.

    Started by DreamCaCao, 7th February 2019 06:25
    • Replies: 4
    • Views: 317
    ckqee
    11th February 2019, 19:41 Go to last post

  22. What does it mean to have a sequential encoding scheme to enumerate states?

    Started by MightyFunkster, 11th February 2019 17:03
    • Replies: 1
    • Views: 101
    ads-ee
    11th February 2019, 17:19 Go to last post

  23. synthesized netlists simulation issue

    Started by manpmanp, 7th February 2019 17:42
    1 Attachment(s)
    • Replies: 6
    • Views: 241
    ThisIsNotSam
    11th February 2019, 16:19 Go to last post

  24. DFT issues on scan clock input as "x"

    Started by skyworld_cy, 9th February 2019 10:08
    1 Attachment(s)
    • Replies: 5
    • Views: 300
    ThisIsNotSam
    10th February 2019, 03:47 Go to last post

  25. How do you simulate a mixed-signal system?

    Started by blacki, 8th February 2019 17:22
    1 Attachment(s)
    • Replies: 2
    • Views: 137
    BradtheRad
    9th February 2019, 05:40 Go to last post

  26. What's the difference between creating ndm using oas and lef

    Started by Studentofknowledge, 8th February 2019 17:37
    • Replies: 1
    • Views: 85
    ThisIsNotSam
    8th February 2019, 18:46 Go to last post

  27. MCR - Metal Cap Reduction

    Started by Studentofknowledge, 8th February 2019 17:44
    • Replies: 1
    • Views: 86
    KlausST
    8th February 2019, 18:11 Go to last post

  28. Have you ever done timing simulation with ARM standard cell library ?

    Started by Yongchan, 8th February 2019 02:15
    • Replies: 0
    • Views: 124
    Yongchan
    8th February 2019, 02:15 Go to last post

  29. Automatize simulations in Modelsim

    Started by javierh.santiago, 5th February 2019 22:44
    • Replies: 2
    • Views: 284
    dave_59
    8th February 2019, 00:12 Go to last post

  30. what are the inputs and outputs for floorplanning?

    Started by lh-, 3rd February 2019 18:28
    1 Attachment(s)
    • Replies: 8
    • Views: 407
    lh-
    7th February 2019, 19:42 Go to last post
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