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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,678
    klug
    25th March 2007, 08:41 Go to last post

  1. Prime Time power estimation whith .spef file

    Started by jmaileh.b, Today 08:00
    • Replies: 0
    • Views: 61
    jmaileh.b
    Today, 08:00 Go to last post

  2. Dynamic IR drop analysis

    Started by ajayg0880, 8th September 2018 07:25
    • Replies: 5
    • Views: 471
    kumar_eee
    10th November 2018, 17:51 Go to last post

  3. How do I synthesize an inout port using DC?

    Started by kos8108, 27th August 2018 14:55
    • Replies: 1
    • Views: 197
    TonyLS
    9th November 2018, 21:41 Go to last post

  4. Logic Path Activation Probability Depending on Input Data Pattern

    Started by ranaya, 9th November 2018 12:12
    • Replies: 1
    • Views: 180
    ThisIsNotSam
    9th November 2018, 15:22 Go to last post

  5. what is the usage of the port in the fpga?

    Started by liletian, 28th August 2018 19:12
    • Replies: 4
    • Views: 311
    dpaul
    9th November 2018, 10:26 Go to last post

  6. CUVMUR error for VHDL code and Verilog testbench

    Started by shreyakishore, 6th November 2018 21:22
    5 Attachment(s)
    • Replies: 3
    • Views: 158
    FvM
    8th November 2018, 08:35 Go to last post

  7. SiliconSmart set_config_opt for individual bus pins

    Started by jiminization, 8th November 2018 07:21
    • Replies: 0
    • Views: 61
    jiminization
    8th November 2018, 07:21 Go to last post

  8. What does this mean in RC?

    Started by liletian, 6th November 2018 01:17
    • Replies: 6
    • Views: 309
    liletian
    7th November 2018, 23:46 Go to last post

  9. Design Compiler Command Needed

    Started by aditya1579, 28th August 2018 03:02
    • Replies: 3
    • Views: 313
    TonyLS
    6th November 2018, 22:32 Go to last post

  10. Bottom up synthesis using dc compiler

    Started by IngleA, 23rd October 2018 18:45
    2 Attachment(s)
    • Replies: 1
    • Views: 135
    TonyLS
    6th November 2018, 22:25 Go to last post

  11. SiliconSmart Multi-Bit definition

    Started by jiminization, 6th November 2018 12:00
    • Replies: 0
    • Views: 76
    jiminization
    6th November 2018, 12:00 Go to last post

  12. How to fix setup timing violations for a design with high speed clock?

    Started by kurax, 31st October 2018 13:45
    • Replies: 6
    • Views: 286
    ThisIsNotSam
    5th November 2018, 21:30 Go to last post

  13. [SOLVED] Parasitic Extraction for New Standard Cells

    Started by ranaya, 5th November 2018 10:23
    • Replies: 0
    • Views: 115
    ranaya
    5th November 2018, 10:23 Go to last post

  14. SiliconSmart clock gating cells

    Started by jiminization, 5th November 2018 04:51
    • Replies: 0
    • Views: 78
    jiminization
    5th November 2018, 04:51 Go to last post

  15. What are the port in the digital design?

    Started by liletian, 3rd November 2018 03:09
    • Replies: 2
    • Views: 255
    timof
    4th November 2018, 01:57 Go to last post

  16. Bencmakrak Circuits - Verilog Netlis

    Started by frasheed, 3rd November 2018 15:23
    • Replies: 3
    • Views: 166
    dave_59
    3rd November 2018, 19:19 Go to last post

  17. Which is more susceptible to variation, HVT or LVT?

    Started by kyon_lee, 2nd November 2018 00:52
    • Replies: 2
    • Views: 162
    dick_freebird
    2nd November 2018, 17:34 Go to last post

  18. port CLASS BUMP in output LEF

    Started by alphus, 29th October 2018 11:18
    • Replies: 5
    • Views: 234
    ThisIsNotSam
    2nd November 2018, 14:22 Go to last post

  19. [SOLVED] How to define SDC constraints for two clock domains fed by single source?

    Started by Pramod_B, 31st October 2018 07:44
    1 Attachment(s)
    • Replies: 15
    • Views: 451
    dpaul
    2nd November 2018, 10:43 Go to last post

  20. Converting Synopsys SAED32nm EDK .tf file into .lef file

    Started by dlvalencia, 31st October 2018 19:53
    • Replies: 3
    • Views: 177
    ThisIsNotSam
    2nd November 2018, 00:34 Go to last post

  21. Static & Dynamic IR analysis operating conditions

    Started by sdbot, 23rd September 2018 23:55
    • Replies: 4
    • Views: 398
    kayexu
    1st November 2018, 16:47 Go to last post

  22. SiliconSmart Import Errors

    Started by jiminization, 30th October 2018 10:17
    • Replies: 1
    • Views: 130
    ThisIsNotSam
    31st October 2018, 15:38 Go to last post

  23. Layers for blocking metal auto fill in TSMC

    Started by Potatoze, 30th October 2018 23:15
    • Replies: 2
    • Views: 158
    ThisIsNotSam
    31st October 2018, 15:31 Go to last post

  24. Format of CDL netlist

    Started by joharali, 31st October 2018 15:09
    • Replies: 0
    • Views: 104
    joharali
    31st October 2018, 15:09 Go to last post

  25. [SOLVED] Fixing setup violations in RTL

    Started by biju4u90, 22nd October 2018 20:26
    • Replies: 6
    • Views: 376
    dpaul
    29th October 2018, 16:42 Go to last post

  26. How to use the TSMC auto dummy fill with Calibre

    Started by Potatoze, 25th October 2018 20:17
    • Replies: 1
    • Views: 154
    ThisIsNotSam
    29th October 2018, 14:11 Go to last post

  27. VDD VSS Short due to bad via alignment

    Started by shragh, 26th October 2018 21:04
    1 Attachment(s)
    • Replies: 1
    • Views: 240
    ThisIsNotSam
    27th October 2018, 22:51 Go to last post

  28. is the race condition normally observed in RC timing analysis?

    Started by liletian, 24th October 2018 19:30
    • Replies: 9
    • Views: 351
    dick_freebird
    26th October 2018, 19:27 Go to last post

  29. Create Block in innovus to use on other designs

    Started by rmachado, 4th July 2018 17:43
    2 Pages •
    1 2
    10 Attachment(s)
    • Replies: 22
    • Views: 1,098
    rmachado
    26th October 2018, 10:11 Go to last post

  30. DFT reset shielding functional reset

    Started by sythe, 24th October 2018 14:29
    • Replies: 0
    • Views: 131
    sythe
    24th October 2018, 14:29 Go to last post
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