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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 37,312
    25th March 2007, 08:41 Go to last post
  1. Results for hierarchical LVS

    Started by aditya1579, 4th March 2020 12:54
    • Replies: 2
    • Views: 365
    Today, 07:05 Go to last post
  2. DRC rules for Double Pattern Test

    Started by aditya1579, 25th May 2020 08:53
    • Replies: 2
    • Views: 194
    Today, 02:26 Go to last post
    • Replies: 6
    • Views: 170
    Today, 02:14 Go to last post
  3. DFT -lbist pattern simulation

    Started by avinashkumar, 26th May 2020 12:57
    • Replies: 0
    • Views: 175
    26th May 2020, 12:57 Go to last post
  4. DFT compiler commands

    Started by chis4yu, 26th May 2020 08:20
    • Replies: 0
    • Views: 124
    26th May 2020, 08:20 Go to last post
  5. Memory repair with efuse and bira

    Started by mona_patel, 26th May 2020 06:09
    • Replies: 0
    • Views: 120
    26th May 2020, 06:09 Go to last post
  6. Tetramax custom patterns

    Started by chis4yu, 25th May 2020 22:26
    • Replies: 0
    • Views: 122
    25th May 2020, 22:26 Go to last post
  7. Floorplanning Guidelines for TSMC 7nm

    Started by aditya1579, 21st May 2020 12:47
    • Replies: 5
    • Views: 425
    24th May 2020, 09:54 Go to last post
  8. DFT compiler with multimodes

    Started by chis4yu, 23rd May 2020 01:21
    • Replies: 0
    • Views: 161
    23rd May 2020, 01:21 Go to last post
  9. Port placement in a design block

    Started by karthikshetty, 22nd May 2020 05:01
    • Replies: 0
    • Views: 258
    22nd May 2020, 05:01 Go to last post
  10. COmparator using xor gate

    Started by djc, 20th May 2020 07:41
    • Replies: 6
    • Views: 367
    21st May 2020, 10:13 Go to last post
  11. CADENCE is disabling functions alone

    Started by lufer17, 18th May 2020 14:28
    • Replies: 6
    • Views: 378
    20th May 2020, 22:20 Go to last post
  12. CADENCE: layout error

    Started by lufer17, 18th May 2020 14:45
    • Replies: 8
    • Views: 424
    20th May 2020, 15:05 Go to last post
  13. MBIST clocks synchronization

    Started by mona_patel, 19th May 2020 07:13
    • Replies: 2
    • Views: 256
    20th May 2020, 10:32 Go to last post
    • Replies: 7
    • Views: 609
    19th May 2020, 15:30 Go to last post
  14. [SOLVED] P&R Buffer Reduction in a Shift Register

    Started by ranaya, 17th May 2020 18:02
    • Replies: 8
    • Views: 415
    19th May 2020, 15:28 Go to last post
    • Replies: 2
    • Views: 342
    19th May 2020, 15:20 Go to last post
  15. Plotting delay vs. load capacitance in Hspice

    Started by reddvoid, 19th May 2020 08:34
    • Replies: 0
    • Views: 147
    19th May 2020, 08:34 Go to last post
  16. VCS2016 cannot compile ok

    Started by luoyanghero, 18th May 2020 11:09
    • Replies: 0
    • Views: 250
    18th May 2020, 11:09 Go to last post
    • Replies: 1
    • Views: 271
    17th May 2020, 19:05 Go to last post
  17. ModelSim/QuestaSim SE/PE versions -> what's mean?

    Started by ivlsi, 15th May 2020 13:17
    • Replies: 1
    • Views: 213
    15th May 2020, 15:34 Go to last post
  18. Sequential depth in DFT

    Started by msancheti, 15th May 2020 12:49
    • Replies: 0
    • Views: 130
    15th May 2020, 12:49 Go to last post
    • Replies: 0
    • Views: 171
    15th May 2020, 02:06 Go to last post
    • Replies: 0
    • Views: 161
    14th May 2020, 18:12 Go to last post
  19. Other end arrival time

    Started by guptya, 6th May 2020 13:19
    • Replies: 7
    • Views: 828
    14th May 2020, 11:02 Go to last post
  20. Modelsim Coverage Reporting

    Started by Battawi, 12th May 2020 22:16
    • Replies: 3
    • Views: 362
    13th May 2020, 15:34 Go to last post