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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 31,589
    klug
    25th March 2007, 08:41 Go to last post

  1. 32x32 Single Cycle Fast Multiplier

    Started by Mr.PAP, Yesterday 12:56
    • Replies: 6
    • Views: 156
    Mr.PAP
    Today, 07:43 Go to last post

  2. priority on two asynch triggered events

    Started by stanford, Yesterday 23:50
    • Replies: 3
    • Views: 70
    stanford
    Today, 01:39 Go to last post

  3. 6T SRAM read/write current

    Started by Windywast, Yesterday 20:30
    • Replies: 2
    • Views: 69
    dick_freebird
    Yesterday, 22:03 Go to last post

  4. Writing ModelSim do files

    Started by tahirsengine, Yesterday 07:54
    • Replies: 1
    • Views: 82
    dpaul
    Yesterday, 10:55 Go to last post

  5. Trouble inserting level shifters with upf and design compiler

    Started by beeflobill, 8th April 2019 19:20
    • Replies: 3
    • Views: 538
    ThisIsNotSam
    16th April 2019, 18:10 Go to last post

  6. [Verilog] Asynchronous Reset

    Started by EEPuppyPuppy, 15th April 2019 21:13
    • Replies: 5
    • Views: 211
    FvM
    16th April 2019, 07:58 Go to last post

  7. Design to state position of first one from lsb every clock for parallel data coming

    Started by fragnen, 12th April 2019 14:18
    • Replies: 8
    • Views: 726
    stanford
    15th April 2019, 18:53 Go to last post

  8. Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 1
    • Views: 100
    oratie
    12th April 2019, 16:53 Go to last post

  9. DFT pins disabled during LEC

    Started by fragnen, 12th April 2019 14:41
    • Replies: 0
    • Views: 95
    fragnen
    12th April 2019, 14:41 Go to last post

  10. Reset during lec between rtl and synthesized netlist

    Started by fragnen, 12th April 2019 14:12
    • Replies: 1
    • Views: 154
    ThisIsNotSam
    12th April 2019, 14:30 Go to last post

  11. Single SPI SS to control multiple devices

    Started by tahirsengine, 12th April 2019 08:07
    • Replies: 1
    • Views: 188
    KlausST
    12th April 2019, 08:25 Go to last post

  12. [moved] Learning DFT as an intern and need help with .dft.v files

    Started by linaxus, 12th April 2019 01:08
    • Replies: 0
    • Views: 126
    linaxus
    12th April 2019, 01:08 Go to last post

  13. [SOLVED] [moved] Parameterized Module in Design Compiler

    Started by blindscience, 10th April 2019 18:49
    • Replies: 1
    • Views: 146
    blindscience
    10th April 2019, 22:17 Go to last post

  14. RedHawk PowerGrid analysis. what are key parameters

    Started by reddvoid, 8th April 2019 07:24
    1 Attachment(s)
    • Replies: 0
    • Views: 150
    reddvoid
    8th April 2019, 08:49 Go to last post

  15. Hierarchical and Flat LEC

    Started by fragnen, 5th April 2019 08:37
    • Replies: 0
    • Views: 265
    fragnen
    5th April 2019, 08:37 Go to last post

  16. Cadence SimVision waveform dump for parameterized multibit signals

    Started by swabhi812, 4th April 2019 22:53
    • Replies: 0
    • Views: 151
    swabhi812
    4th April 2019, 22:53 Go to last post

  17. Handling LEC for multibit flipflop

    Started by fragnen, 3rd April 2019 14:47
    • Replies: 0
    • Views: 274
    fragnen
    3rd April 2019, 14:47 Go to last post

  18. Digital on top mixed signal design

    Started by Alexxk, 2nd April 2019 14:41
    • Replies: 1
    • Views: 354
    ThisIsNotSam
    2nd April 2019, 18:24 Go to last post

  19. Verdi dump wave compatibility setting

    Started by luoyanghero, 2nd April 2019 07:26
    • Replies: 0
    • Views: 127
    luoyanghero
    2nd April 2019, 07:26 Go to last post

  20. Test vector patterns in LEC

    Started by Fati_hv, 20th February 2019 09:40
    • Replies: 1
    • Views: 327
    Fati_hv
    1st April 2019, 09:38 Go to last post

  21. SCRIPT Find out all the logical drivers of a pin of any standard cell in the netlist?

    Started by QuyVo, 28th March 2019 19:50
    1 Attachment(s)
    • Replies: 8
    • Views: 1,618
    ThisIsNotSam
    31st March 2019, 20:11 Go to last post

  22. Three-state buffer cell characterization

    Started by dr_kca, 29th March 2019 08:57
    • Replies: 0
    • Views: 158
    dr_kca
    29th March 2019, 08:57 Go to last post

  23. fsm for detecting if a number is divisible by 5 when lsb comes first

    Started by rtldesign, 25th March 2019 22:01
    1 Attachment(s)
    • Replies: 16
    • Views: 1,686
    dpaul
    28th March 2019, 09:27 Go to last post

  24. How does Primetime work?

    Started by badari259, 27th March 2019 14:59
    • Replies: 1
    • Views: 190
    ThisIsNotSam
    27th March 2019, 16:40 Go to last post

  25. [SOLVED] Verilog print out %d longer than 32bit

    Started by childs72, 27th March 2019 08:24
    • Replies: 0
    • Views: 119
    childs72
    27th March 2019, 08:24 Go to last post

  26. Bluetooth connection with a smartphone?

    Started by 600V3Phase, 26th March 2019 01:58
    • Replies: 7
    • Views: 314
    dpaul
    26th March 2019, 17:28 Go to last post

  27. Need help with VCS part compilation

    Started by Groh, 26th March 2019 13:35
    • Replies: 0
    • Views: 141
    Groh
    26th March 2019, 13:35 Go to last post

  28. ATPG Test Coverage for stuck@ and @speed

    Started by sandy2811, 25th March 2019 15:08
    • Replies: 2
    • Views: 161
    sandy2811
    25th March 2019, 18:06 Go to last post

  29. Static timing analysis

    Started by gaurp, 17th March 2019 20:38
    • Replies: 4
    • Views: 981
    swabhi812
    22nd March 2019, 19:29 Go to last post

  30. Shadow path causing parallel simulation to fail. Serial is passing.

    Started by finsiherfish, 22nd March 2019 16:36
    • Replies: 0
    • Views: 202
    finsiherfish
    22nd March 2019, 16:36 Go to last post
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