1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    120,060
Page 1 of 812 1 2 3 11 51 101 501 ... LastLast
Threads 1 to 30 of 24359

Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 32,044
    25th March 2007, 08:41 Go to last post
    • Replies: 2
    • Views: 56
    Today, 15:55 Go to last post
  1. Synposys Tcyc not observed

    Started by blindscience, Yesterday 18:29
    • Replies: 0
    • Views: 42
    Yesterday, 18:29 Go to last post
  2. How to clock gate in hierarchy?

    Started by DimitrisStathis, 17th June 2019 17:29
    • Replies: 5
    • Views: 165
    18th June 2019, 18:06 Go to last post
  3. Test and dft logic verification in flow and the lec

    Started by fragnen, 12th April 2019 14:14
    • Replies: 4
    • Views: 264
    18th June 2019, 09:29 Go to last post
  4. Coverage improvement from AU.TC faults

    Started by aakashaspires, 17th June 2019 08:59
    • Replies: 1
    • Views: 80
    17th June 2019, 16:17 Go to last post
  5. meaning of placeable cells

    Started by sharanbr123, 14th June 2019 12:52
    • Replies: 2
    • Views: 162
    14th June 2019, 17:23 Go to last post
    • Replies: 1
    • Views: 163
    12th June 2019, 14:16 Go to last post
    • Replies: 0
    • Views: 102
    12th June 2019, 09:00 Go to last post
  6. ATPG Test Coverage for stuck@ and @speed

    Started by sandy2811, 25th March 2019 15:08
    • Replies: 3
    • Views: 318
    11th June 2019, 07:16 Go to last post
    • Replies: 1
    • Views: 205
    11th June 2019, 07:07 Go to last post
  7. [moved] Digital Transition Capture

    Started by minhchau, 8th June 2019 16:40
    • Replies: 11
    • Views: 493
    10th June 2019, 19:40 Go to last post
    • Replies: 4
    • Views: 163
    10th June 2019, 16:01 Go to last post
  8. [SOLVED] How to re-synthesize a circuit with ABC synthesizer?

    Started by amin-ea, 25th May 2019 12:06
    • Replies: 5
    • Views: 341
    10th June 2019, 08:40 Go to last post
  9. [SOLVED] Methodology to calculate the Clock Uncertainity values.

    Started by Wyre, 9th June 2019 10:35
    • Replies: 1
    • Views: 126
    9th June 2019, 16:13 Go to last post
  10. System verilog, fork join_any

    Started by surerdra, 4th June 2019 08:49
    • Replies: 3
    • Views: 283
    5th June 2019, 07:05 Go to last post
    • Replies: 2
    • Views: 242
    3rd June 2019, 15:19 Go to last post
  11. Optimizing case statement with large input

    Started by stanford, 30th May 2019 03:01
    • Replies: 8
    • Views: 698
    1st June 2019, 02:42 Go to last post
  12. if/else vs. if/if in combo logic

    Started by stanford, 30th May 2019 02:09
    • Replies: 10
    • Views: 492
    1st June 2019, 02:39 Go to last post
    • Replies: 2
    • Views: 388
    1st June 2019, 01:46 Go to last post
  13. [SOLVED] Code coverage of a design

    Started by vyella1, 31st May 2019 04:12
    • Replies: 1
    • Views: 205
    31st May 2019, 15:50 Go to last post
  14. blocking assignment in always_comb

    Started by stanford, 28th May 2019 04:25
    • Replies: 3
    • Views: 284
    28th May 2019, 19:22 Go to last post
    • Replies: 9
    • Views: 502
    28th May 2019, 14:05 Go to last post