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Forum: ASIC Design Methodologies and Tools (Digital)

ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

  1. Sticky Thread Sticky: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!

    Started by klug, 25th March 2007 08:41
    • Replies: 0
    • Views: 30,313
    klug
    25th March 2007, 08:41 Go to last post

  1. Plotting the transient noise distribution in virtuoso

    Started by romanb, Yesterday 19:27
    • Replies: 0
    • Views: 47
    romanb
    Yesterday, 19:27 Go to last post

  2. Memory/macro internal clock insertion delay

    Started by argha, 16th June 2018 20:12
    • Replies: 0
    • Views: 113
    argha
    16th June 2018, 20:12 Go to last post

  3. Import a layout from Encounter to Virtuoso

    Started by Mahmoud_Dagher, 14th June 2018 14:53
    • Replies: 3
    • Views: 168
    slizak
    15th June 2018, 21:14 Go to last post

  4. When is data captured and data launched in SPI transmission?

    Started by kaushikrvs, 15th June 2018 13:04
    • Replies: 2
    • Views: 145
    ads-ee
    15th June 2018, 15:36 Go to last post

  5. SPI Slave with strange behavior

    Started by rmachado, 9th June 2018 13:59
    2 Pages •
    1 2
    9 Attachment(s)
    • Replies: 25
    • Views: 562
    rmachado
    15th June 2018, 10:57 Go to last post

  6. SDC constraints for asynchronous reset

    Started by Alexxk, 14th June 2018 12:04
    • Replies: 2
    • Views: 92
    slutarius
    15th June 2018, 10:36 Go to last post

  7. Timing Sign off from Primetime

    Started by sreejinair, 11th June 2018 14:38
    • Replies: 4
    • Views: 263
    sreejinair
    12th June 2018, 15:33 Go to last post

  8. async fifo - almost full/empty

    Started by stanford, 10th June 2018 08:24
    • Replies: 4
    • Views: 208
    FvM
    11th June 2018, 07:34 Go to last post

  9. What happens when the width is too large for the length of the MOSFET?

    Started by littlerock, 5th June 2018 09:41
    • Replies: 4
    • Views: 314
    frankrose
    9th June 2018, 17:56 Go to last post

  10. UMC 65nm without TLU+ files

    Started by ua6bqg, 8th June 2018 16:30
    • Replies: 1
    • Views: 115
    ThisIsNotSam
    8th June 2018, 18:00 Go to last post

  11. [moved] Physical design placement timing issue

    Started by prabhu14, 7th June 2018 19:05
    • Replies: 2
    • Views: 170
    ThisIsNotSam
    8th June 2018, 14:54 Go to last post

  12. Cadence lint error: CLKDMN

    Started by Sam26, 7th June 2018 10:45
    • Replies: 3
    • Views: 163
    Sam26
    8th June 2018, 12:37 Go to last post

  13. [moved] 50Mz to 1 kHz clock generator

    Started by sanjaysharmaiitk, 8th June 2018 09:26
    3 Attachment(s)
    • Replies: 1
    • Views: 130
    KlausST
    8th June 2018, 10:14 Go to last post

  14. Cell Characterization Determining Slew vs Capacitive Values for Templates

    Started by ranaya, 23rd May 2018 19:20
    • Replies: 6
    • Views: 339
    ThisIsNotSam
    7th June 2018, 14:35 Go to last post

  15. Cadence Encounter place and route - Pins not covered by metal layer

    Started by NikosTS, 7th May 2018 10:01
    • Replies: 10
    • Views: 513
    jackoup
    4th June 2018, 11:41 Go to last post

  16. Program Error:unhandled pattern type while reading external VCDE pattern in TetraMax

    Started by edab_johnhsu, 4th June 2018 07:56
    • Replies: 0
    • Views: 263
    edab_johnhsu
    4th June 2018, 07:56 Go to last post

  17. bit width for addition

    Started by sky_above, 2nd June 2018 14:04
    • Replies: 3
    • Views: 213
    vGoodtimes
    3rd June 2018, 22:22 Go to last post

  18. Realization of D flip flop by basic gates from library while synthesizing

    Started by sky_above, 26th May 2018 16:47
    • Replies: 7
    • Views: 380
    FvM
    2nd June 2018, 16:10 Go to last post

  19. Output combinational output and valid sequential

    Started by sky_above, 26th May 2018 16:22
    • Replies: 9
    • Views: 384
    barry
    2nd June 2018, 15:28 Go to last post

  20. Books or websites to learn digital system design

    Started by sky_above, 2nd June 2018 14:01
    • Replies: 0
    • Views: 125
    sky_above
    2nd June 2018, 14:01 Go to last post

  21. TrueNorth Evaluation Board

    Started by mwn1, 2nd June 2018 04:58
    • Replies: 0
    • Views: 90
    mwn1
    2nd June 2018, 04:58 Go to last post

  22. Force deposit through testbench

    Started by rmk423, 25th April 2018 06:50
    • Replies: 4
    • Views: 477
    ads-ee
    31st May 2018, 16:27 Go to last post

  23. HSPICE 2013 SP2 28T Full Adder Simulation Problem

    Started by Mohammad Amin Nili, 29th May 2018 21:59
    2 Attachment(s)
    • Replies: 7
    • Views: 363
    FvM
    30th May 2018, 13:29 Go to last post

  24. generic parameter while instantiating design at top level if allowed

    Started by sky_above, 27th May 2018 10:05
    • Replies: 7
    • Views: 335
    ads-ee
    29th May 2018, 18:28 Go to last post

  25. Is that possible to synthesize mixed (vhdl & verilog) design using DC ?

    Started by kos8108, 29th May 2018 05:53
    • Replies: 2
    • Views: 192
    ThisIsNotSam
    29th May 2018, 15:27 Go to last post

  26. If the rtl of adder is correct and instance declaration is correct and also ripple ca

    Started by sky_above, 26th May 2018 16:44
    • Replies: 2
    • Views: 425
    sky_above
    28th May 2018, 11:58 Go to last post

  27. Divison by 2 syntesizable RTL coding

    Started by sky_above, 26th May 2018 16:55
    • Replies: 4
    • Views: 220
    andre_teprom
    27th May 2018, 23:01 Go to last post

  28. D Flipflop with enable does not have the else part in RTL in the if-else statement

    Started by sky_above, 25th May 2018 15:07
    • Replies: 8
    • Views: 882
    FvM
    27th May 2018, 18:44 Go to last post

  29. Whether synthesis tool will realize comparators or not

    Started by sky_above, 26th May 2018 15:48
    • Replies: 0
    • Views: 90
    sky_above
    26th May 2018, 15:48 Go to last post

  30. Read operation of a memory and clock cycles

    Started by sky_above, 26th May 2018 07:34
    • Replies: 2
    • Views: 133
    KlausST
    26th May 2018, 12:08 Go to last post
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