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dpaul

Using a Xilinx IP in your design without generating it using the Coregen flow.

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Using a Xilinx IP in your design without generating it using the Coregen flow.
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I will take the example of the LogiCORE IP - AXI Interconnect v.1.06.a (DS768).

Consider the situation that you want to connect multiple masters and multiple slaves to a Xilinx AXI Interconnect IP. Consider that your target implementation FPGA is not a Series7 device (e.g.- Spartan6 or Virtex6). In this situation Coregen will not allow you to generate an AXI Interconnect with multiple masters and slaves.

How do you deal with such a situation?

I will roughly tell you what needs can be done, from where the RTL of the IP can be fetched, and the most important parameter that needs to be modified so that one can integrate the RTL of this IP with the top-level design.

Note:
This is not the recommended way to use a Xilinx IP.
Xilinx IPs can ONLY be used in your design if your design is implemented on a Xilinx FPGA.

IP Source:
To get the RTL for the AXI Interconnect v.1.06.a IP, first locate the Xilinx installation directory in your work environment. It would be very similar to the path given below (you might need to adjust the version of Xilinx, etc).
$Xilinx/14.4/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_06_a/hdl/verilog

You may directly point the paths in your filelist to this dir. for the source RTL files or make a local copy and then point accordingly.


What to change:
The axi_interconnect.v is only file where the changes need to be done. This is the only file
which needs to be instiantiated in your top module. In this file we only change the parameters. In the top_module you have to connect only the ports.

The parameters to be modified will depend heavily on your axi interconnect implementation environment. So I am not going to discuss all the parameter modifications that have to be done. Please refer to the doc ds768_axi_interconnect.pdf. Trust me, the documentation is good and clear!

Perhaps the most important and complicated portion of the parameters configuration are C_M_AXI_BASE_ADDR and C_M_AXI_HIGH_ADDR. They are required to set the base and high addresses for each connected slave. If they are not properly specified, then the address decoder of the axi interconnect will not allow to pass the data to the proper slave.

First take a look at the default value of these parameters in the pristine axi_interconnect.v file.

Now let us assume that there are two connected slaves with the following base and high addresses.
Slave0 base address = 32'h84000000
Slave1 base address = 32'h84020000
Slave0 high address = 32'h84000fff
Slave1 high address = 32'h84020fff

I am taking the example where the P_NUM_ADDR_RANGES parameter has been kept to 16 (default). So for this example I am using only 1 address range and 15 would be unused for both the slaves.

So the parameters C_M_AXI_BASE_ADDR and C_M_AXI_HIGH_ADDR will ultimately translate to the following:

Code:
parameter [`P_MAX_M*`P_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR =  { { {15{64'hFFFFFFFF_FFFFFFFF}}, 64'h00000000_84020000 },   // Slave1 base address
                                                                      { {15{64'hFFFFFFFF_FFFFFFFF}}, 64'h00000000_84000000 } } ,// Slave0 base address   
   
parameter [`P_MAX_M*`P_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR =  { { {15{64'h00000000_00000000}}, 64'h00000000_84020fff },    // Slave1 high address
                                                                      { {15{64'h00000000_00000000}}, 64'h00000000_84000fff } } , // Slave0 high address
Caution - Never change the 64'hxxxxxxxx_xxxxxxxx format used above. Anything like 32'hxxxxxxxx would not work!

Hence you easily extend this axi_interconnect.v to support multi-master and multi-slave environment.

Hope this would be useful.
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