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  1. Programmable Cyclic On-Off Timer with Relay Output

    Hi,
    This project is to build cyclic on-off programmable timer. In this project user can set ON timer and Off time using keys and 7 segment display. Relay is provided as output, where relay will be remained ON for ON time and it will goes OFF after ON time overs. And Relay will remain Off till Off time overs.


    Components required for the project:
    1 x PIC16F876A
    4 x Keys
    4 x 7 Segment

    Here is hex file path:
    https://github.com/embhobbb/electronicsDIY ...
    Categories
    Uncategorized
  2. What Programming Language Skills Do Employers Want?

    "What programming language skills do employers want? Online job-search firm Indeed took a look at three months (18 May to 18 August) of 2018 job listings in its tech software category to find out. The company ranked programming languages according to the percentage of job postings within the category that included mention of the language."


    https://spectrum.ieee.org/view-from-...employers-want
  3. David Patterson Says It’s Time for New Computer Architectures and Software Languages

    Moore’s Law is over, ushering in a golden age for computer architecture, says RISC pioneer

    David Patterson—University of California professor, Google engineer, and RISC pioneer—says there’s no better time than now to be a computer architect.

    Some highlights

    "As an example on the software side, Patterson indicated that rewriting Python into C gets you a 50x speedup in performance. Add in various optimization techniques and the speedup increases dramatically. ...
  4. [Vivado 18.2] IP Packager PCIe4 Missing Interfaces

    Feedback:
    Please leave the comment below.
    Is this blog entry helpful or does it need an improvement?

    The problem:
    In Vivado 2018.2 in the IP Packager when I was trying to make a custom component with mating interfaces to control PCIe4 IP Core, I couldn't do it because in the IP Packager PCIe4 control interfaces were missing, e.g.:
    VLNV xilinx.com:display_pcie4:pcie4_cfg_mgmt_rtl:1.0
    VLNV xilinx.com:display_pcie4:pcie4_cfg_pm_rtl:1.0

    The only ...

    Updated 20th September 2018 at 06:51 by niciki

    Categories
    Xilinx Vivado Workarounds , Vivado , IP , Interface , PCIe4
  5. [Vivado 18.2] IP Packager TCL commands missing for interface parameters values

    The problem:
    In Vivado 2018.2 in the IP Packager, when we want to set a value for any interface parameter, we won't get any TCL commands in the Tcl Console.
    This is probably a bug in the Vivado 2018.2.

    The following images visualize the problem:

    Click image for larger version. 

Name:	01_Edit_Interface.png 
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Size:	19.4 KB 
ID:	147090 Click image for larger version. 

Name:	02_Edit_Interface_parameters_missing.png 
Views:	218 
Size:	28.3 KB 
ID:	147091

    Click image for larger version. 

Name:	03_Edit_Interface_adding_parameters.png 
Views:	231 
Size:	33.4 KB 
ID:	147092 Click image for larger version. 

Name:	04_Edit_Interface_adding_parameters.png 
Views:	230 
Size:	33.0 KB 
ID:	147093

    Click image for larger version. 

Name:	05_Edit_Interface_adding_values.png 
Views:	246 
Size:	30.1 KB 
ID:	147094 Click image for larger version. 

Name:	06_Tcl_Console_doesnt_contain_values.png 
Views:	219 
Size:	11.2 KB 
ID:	147095
    ...

    Updated 20th September 2018 at 06:52 by niciki

    Categories
    Xilinx Vivado Workarounds , Vivado , IP , Interface , TCL
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