sata_test Project Status (12/03/2014 - 16:00:36)
Project File: ml405_sata.xise Parser Errors: No Errors
Module Name: sata_test Implementation State: Synthesized (Failed)
Target Device: xc4vfx20-10ff672
  • Errors:
X 6 Errors (6 new)
Product Version:ISE 14.6
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 3. Dez 16:00:35 2014X 6 Errors (6 new)00
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMi 3. Dez 16:00:02 2014

Date Generated: 12/03/2014 - 16:00:36