System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH
Path C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt;
C:\Xilinx\13.3\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\system32\WBEM;
C:\Program Files\MiKTeX 2.8\miktex\bin;
c:\program files\common files\divx shared\;
c:\program files\quicktime\qtsystem\;
c:\jentek\bin;
C:\Program Files\MATLAB71\bin\win32;
c:\matlab6p5\bin\win32;
C:\Program Files\Common Files\Roxio Shared\DLLShared\;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Cadence\Orcad_9.2.3\tools\Capture;
C:\Cadence\Orcad_9.2.3\tools\bin;
C:\Cadence\Orcad_9.2.3\tools\jre\bin;
C:\Cadence\Orcad_9.2.3\tools\fet\bin;
C:\Program Files\FreeArc\bin		 C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt;
C:\Xilinx\13.3\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\system32\WBEM;
C:\Program Files\MiKTeX 2.8\miktex\bin;
c:\program files\common files\divx shared\;
c:\program files\quicktime\qtsystem\;
c:\jentek\bin;
C:\Program Files\MATLAB71\bin\win32;
c:\matlab6p5\bin\win32;
C:\Program Files\Common Files\Roxio Shared\DLLShared\;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Cadence\Orcad_9.2.3\tools\Capture;
C:\Cadence\Orcad_9.2.3\tools\bin;
C:\Cadence\Orcad_9.2.3\tools\jre\bin;
C:\Cadence\Orcad_9.2.3\tools\fet\bin;
C:\Program Files\FreeArc\bin		 C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt;
C:\Xilinx\13.3\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\system32\WBEM;
C:\Program Files\MiKTeX 2.8\miktex\bin;
c:\program files\common files\divx shared\;
c:\program files\quicktime\qtsystem\;
c:\jentek\bin;
C:\Program Files\MATLAB71\bin\win32;
c:\matlab6p5\bin\win32;
C:\Program Files\Common Files\Roxio Shared\DLLShared\;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Cadence\Orcad_9.2.3\tools\Capture;
C:\Cadence\Orcad_9.2.3\tools\bin;
C:\Cadence\Orcad_9.2.3\tools\jre\bin;
C:\Cadence\Orcad_9.2.3\tools\fet\bin;
C:\Program Files\FreeArc\bin		 C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt;
C:\Xilinx\13.3\ISE_DS\common\lib\nt;
C:\WINDOWS\system32;
C:\WINDOWS;
C:\WINDOWS\system32\WBEM;
C:\Program Files\MiKTeX 2.8\miktex\bin;
c:\program files\common files\divx shared\;
c:\program files\quicktime\qtsystem\;
c:\jentek\bin;
C:\Program Files\MATLAB71\bin\win32;
c:\matlab6p5\bin\win32;
C:\Program Files\Common Files\Roxio Shared\DLLShared\;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Cadence\Orcad_9.2.3\tools\Capture;
C:\Cadence\Orcad_9.2.3\tools\bin;
C:\Cadence\Orcad_9.2.3\tools\jre\bin;
C:\Cadence\Orcad_9.2.3\tools\fet\bin;
C:\Program Files\FreeArc\bin
XILINX C:\Xilinx\13.3\ISE_DS\ISE\ C:\Xilinx\13.3\ISE_DS\ISE\ C:\Xilinx\13.3\ISE_DS\ISE\ C:\Xilinx\13.3\ISE_DS\ISE\
XILINX_DSP C:\Xilinx\13.3\ISE_DS\ISE C:\Xilinx\13.3\ISE_DS\ISE C:\Xilinx\13.3\ISE_DS\ISE C:\Xilinx\13.3\ISE_DS\ISE
XILINX_EDK C:\Xilinx\13.3\ISE_DS\EDK C:\Xilinx\13.3\ISE_DS\EDK C:\Xilinx\13.3\ISE_DS\EDK C:\Xilinx\13.3\ISE_DS\EDK
XILINX_PLANAHEAD C:\Xilinx\13.3\ISE_DS\PlanAhead C:\Xilinx\13.3\ISE_DS\PlanAhead C:\Xilinx\13.3\ISE_DS\PlanAhead C:\Xilinx\13.3\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   top_nto1_ddr_diff_rx.prj  
-ofn   top_nto1_ddr_diff_rx  
-ofmt   NGC NGC
-p   xc6slx16-2-csg324  
-top   top_nto1_ddr_diff_rx  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc6slx16-csg324-2 None
-uc   C:/Users/Scott/Product Development/8200 Development/FPGA Development/Support Docs/XAPP1064/Verilog_Source/Top level examples/BUFIO2 DDR/top_nto1_ddr_diff_rx.ucf None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xt Extra Cost Tables 0 0
-ir Use RLOC Constraints OFF OFF
-t Starting Placer Cost Table (1-100) Map 1 0
-r Register Ordering 4 4
-intstyle   ise None
-lc LUT Combining off off
-o   top_nto1_ddr_diff_rx_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc6slx16-csg324-2 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise  
-mt Enable Multi-Threading off off
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz/2193 MHz Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz/2193 MHz Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz/2193 MHz Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz/2193 MHz
Host sdenenberg sdenenberg sdenenberg sdenenberg
OS Name Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional
OS Release Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600) Service Pack 3 (build 2600)