top_nto1_ddr_diff_rx Project Status
Project File: LVDSdeserializationTest.xise Parser Errors: No Errors
Module Name: top_nto1_ddr_diff_rx Implementation State: Placed and Routed
Target Device: xc6slx16-2csg324
  • Errors:
X 1 Error (0 new)
Product Version:ISE 13.3
  • Warnings:
2 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
X 125 Signals Not Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 36 18,224 1%  
    Number used as Flip Flops 36      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 52 9,112 1%  
    Number used as logic 52 9,112 1%  
        Number using O6 output only 37      
        Number using O5 output only 0      
        Number using O5 and O6 15      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
Number of occupied Slices 20 2,278 1%  
Nummber of MUXCYs used 12 4,556 1%  
Number of LUT Flip Flop pairs used 52      
    Number with an unused Flip Flop 21 52 40%  
    Number with an unused LUT 0 52 0%  
    Number of fully used LUT-FF pairs 31 52 59%  
    Number of unique control sets 5      
    Number of slice register sites lost
        to control set restrictions
20 18,224 1%  
Number of bonded IOBs 23 232 9%  
    Number of LOCed IOBs 23 23 100%  
    IOB Flip Flops 16      
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 2 32 6%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 1      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 4 248 1%  
    Number used as ILOGIC2s 0      
    Number used as ISERDES2s 4      
Number of IODELAY2/IODRP2/IODRP2_MCBs 6 248 2%  
    Number used as IODELAY2s 6      
    Number used as IODRP2s 0      
    Number used as IODRP2_MCBs 0      
Number of OLOGIC2/OSERDES2s 16 248 6%  
    Number used as OLOGIC2s 16      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.85      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: X 125 Signals Not Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Feb 24 16:53:04 2012003 Infos (3 new)
Translation ReportCurrentFri Feb 24 16:53:12 2012001 Info (0 new)
Map ReportCurrentFri Feb 24 16:53:30 2012005 Infos (0 new)
Place and Route ReportCurrentFri Feb 24 16:53:37 2012X 1 Error (0 new)2 Warnings (0 new)0
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 02/24/2012 - 17:34:55