| EDGEPENH_CW Project Status | |||
| Project File: | edgepenh_cw.ise | Current State: | Synthesized |
| Module Name: | edgepenh_cw |
|
No Errors |
| Target Device: | xc2vp30-7ff896 |
|
484 Warnings |
| Product Version: | ISE 9.2.04i |
|
Mon Feb 16 15:50:47 2015 |
| EDGEPENH_CW Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary (estimated values) | |||
| Logic Utilization | Used | Available | Utilization |
| Number of Slices | 361 | 13696 | 2% |
| Number of Slice Flip Flops | 579 | 27392 | 2% |
| Number of 4 input LUTs | 391 | 27392 | 1% |
| Number of bonded IOBs | 28 | 556 | 5% |
| Number of BRAMs | 9 | 136 | 6% |
| Number of MULT18X18s | 5 | 136 | 3% |
| Number of GCLKs | 1 | 16 | 6% |
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Mon Feb 16 15:50:46 2015 | 0 | 484 Warnings | 1 Info |
| Translation Report | |||||
| Map Report | |||||
| Place and Route Report | |||||
| Static Timing Report | |||||
| Bitgen Report | |||||