Static Timing Analysis

Project : crosspoint switch test
Build Time : 08/09/22 12:57:07
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(routed) Clock_1(routed) 1.000 kHz 1.000 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
SPIM_IntClock CyMASTER_CLK 8.000 MHz 8.000 MHz 24.450 MHz
Clock_1 CyMASTER_CLK 1.000 kHz 1.000 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 125ns(8 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_243/q \SPIM:BSPIM:sR16:Dp:u0\/route_si 24.450 MHz 40.900 84.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,4) 1 Net_243 Net_243/clock_0 Net_243/q 1.250
Route 1 Net_243 Net_243/q xp_data(0)/pin_input 6.950
iocell21 P0[0] 1 xp_data(0) xp_data(0)/pin_input xp_data(0)/pad_out 15.251
iocell21 P0[0] 1 xp_data(0) xp_data(0)/pad_out xp_data(0)/pad_in 0.000
iocell21 P0[0] 1 xp_data(0) xp_data(0)/pad_in xp_data(0)/fb 7.922
Route 1 \SPIM:Net_244\ xp_data(0)/fb \SPIM:BSPIM:sR16:Dp:u0\/route_si 6.027
datapathcell1 U(3,4) 1 \SPIM:BSPIM:sR16:Dp:u0\ SETUP 3.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:sR16:Dp:u1\/f1_load 57.428 MHz 17.413 107.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 5.124
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u1\/f1_load 4.149
datapathcell2 U(2,4) 1 \SPIM:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR16:Dp:u1\/f1_load 57.438 MHz 17.410 107.590
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 5.121
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u1\/f1_load 4.149
datapathcell2 U(2,4) 1 \SPIM:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:sR16:Dp:u1\/f1_load 60.390 MHz 16.559 108.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 4.270
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u1\/f1_load 4.149
datapathcell2 U(2,4) 1 \SPIM:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:sR16:Dp:u0\/f1_load 60.401 MHz 16.556 108.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 5.124
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u0\/f1_load 3.292
datapathcell1 U(3,4) 1 \SPIM:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR16:Dp:u0\/f1_load 60.412 MHz 16.553 108.447
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 5.121
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u0\/f1_load 3.292
datapathcell1 U(3,4) 1 \SPIM:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR16:Dp:u1\/f1_load 60.540 MHz 16.518 108.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 4.229
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u1\/f1_load 4.149
datapathcell2 U(2,4) 1 \SPIM:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:sR16:Dp:u1\/f1_load 61.170 MHz 16.348 108.652
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 4.059
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u1\/f1_load 4.149
datapathcell2 U(2,4) 1 \SPIM:BSPIM:sR16:Dp:u1\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:sR16:Dp:u0\/f1_load 63.686 MHz 15.702 109.298
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 4.270
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u0\/f1_load 3.292
datapathcell1 U(3,4) 1 \SPIM:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR16:Dp:u0\/f1_load 63.853 MHz 15.661 109.339
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 4.229
macrocell1 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR16:Dp:u0\/f1_load 3.292
datapathcell1 U(3,4) 1 \SPIM:BSPIM:sR16:Dp:u0\ SETUP 2.850
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIM:BSPIM:sR16:Dp:u0\/sol_msb \SPIM:BSPIM:sR16:Dp:u1\/sir 0.170
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \SPIM:BSPIM:sR16:Dp:u0\ \SPIM:BSPIM:sR16:Dp:u0\/clock \SPIM:BSPIM:sR16:Dp:u0\/sol_msb 0.170
Route 1 \SPIM:BSPIM:sR16:Dp:u0.sol_msb__sig\ \SPIM:BSPIM:sR16:Dp:u0\/sol_msb \SPIM:BSPIM:sR16:Dp:u1\/sir 0.000
datapathcell2 U(2,4) 1 \SPIM:BSPIM:sR16:Dp:u1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,5) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/clock_0 \SPIM:BSPIM:load_cond\/q 1.250
macrocell11 U(2,5) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 2.299
macrocell11 U(2,5) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 3.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_2\/main_5 2.976
macrocell8 U(2,5) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_cond\/main_5 3.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_cond\/main_5 2.976
macrocell11 U(2,5) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_1\/main_5 3.759
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:state_1\/main_5 3.139
macrocell9 U(3,5) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:ld_ident\/main_5 3.759
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:ld_ident\/main_5 3.139
macrocell12 U(3,5) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_1\/main_3 3.903
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_1\/main_3 3.283
macrocell9 U(3,5) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:ld_ident\/main_3 3.903
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:ld_ident\/main_3 3.283
macrocell12 U(3,5) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 3.910
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 3.290
macrocell9 U(3,5) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:ld_ident\/main_6 3.910
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:ld_ident\/main_6 3.290
macrocell12 U(3,5) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_IntClock
Source Destination Delay (ns)
xp_data(0)_PAD:in \SPIM:BSPIM:sR16:Dp:u0\/route_si 17.449
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 xp_data(0)_PAD xp_data(0)_PAD:in xp_data(0)/pad_in 0.000
iocell21 P0[0] 1 xp_data(0) xp_data(0)/pad_in xp_data(0)/fb 7.922
Route 1 \SPIM:Net_244\ xp_data(0)/fb \SPIM:BSPIM:sR16:Dp:u0\/route_si 6.027
datapathcell1 U(3,4) 1 \SPIM:BSPIM:sR16:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPIM_IntClock
Source Destination Delay (ns)
Net_239/q ss(0)_PAD 23.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,4) 1 Net_239 Net_239/clock_0 Net_239/q 1.250
Route 1 Net_239 Net_239/q ss(0)/pin_input 6.638
iocell22 P0[3] 1 ss(0) ss(0)/pin_input ss(0)/pad_out 15.744
Route 1 ss(0)_PAD ss(0)/pad_out ss(0)_PAD 0.000
Clock Clock path delay 0.000
Net_243/q xp_data(0)_PAD:out 23.451
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(2,4) 1 Net_243 Net_243/clock_0 Net_243/q 1.250
Route 1 Net_243 Net_243/q xp_data(0)/pin_input 6.950
iocell21 P0[0] 1 xp_data(0) xp_data(0)/pin_input xp_data(0)/pad_out 15.251
Route 1 xp_data(0)_PAD xp_data(0)/pad_out xp_data(0)_PAD:out 0.000
Clock Clock path delay 0.000
Net_231/q xp_serial_clock(0)_PAD 23.339
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,4) 1 Net_231 Net_231/clock_0 Net_231/q 1.250
Route 1 Net_231 Net_231/q xp_serial_clock(0)/pin_input 6.630
iocell20 P0[2] 1 xp_serial_clock(0) xp_serial_clock(0)/pin_input xp_serial_clock(0)/pad_out 15.459
Route 1 xp_serial_clock(0)_PAD xp_serial_clock(0)/pad_out xp_serial_clock(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock To Output Enable Section
+ SPIM_IntClock
Source Destination Type Delay (ns)
\SPIM:BSPIM:BidirMode:CtrlReg\/control_0 xp_data(0)_PAD:out TURN ON 24.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \SPIM:BSPIM:BidirMode:CtrlReg\ \SPIM:BSPIM:BidirMode:CtrlReg\/clock \SPIM:BSPIM:BidirMode:CtrlReg\/control_0 1.210
Route 1 \SPIM:Net_294\ \SPIM:BSPIM:BidirMode:CtrlReg\/control_0 xp_data(0)/oe 6.421
iocell21 P0[0] 1 xp_data(0) xp_data(0)/oe xp_data(0)/pad_out 17.161
Route 1 xp_data(0)_PAD xp_data(0)/pad_out xp_data(0)_PAD:out 0.000
Clock Clock path delay 0.000
\SPIM:BSPIM:BidirMode:CtrlReg\/control_0 xp_data(0)_PAD:out TURN OFF 24.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,4) 1 \SPIM:BSPIM:BidirMode:CtrlReg\ \SPIM:BSPIM:BidirMode:CtrlReg\/clock \SPIM:BSPIM:BidirMode:CtrlReg\/control_0 1.210
Route 1 \SPIM:Net_294\ \SPIM:BSPIM:BidirMode:CtrlReg\/control_0 xp_data(0)/oe 6.421
iocell21 P0[0] 1 xp_data(0) xp_data(0)/oe xp_data(0)/pad_out 17.161
Route 1 xp_data(0)_PAD xp_data(0)/pad_out xp_data(0)_PAD:out 0.000
Clock Clock path delay 0.000