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00048 #ifndef _POWER_DRV_H_
00049 #define _POWER_DRV_H_
00050
00051 #ifdef __GNUC__
00052 #include <avr/power.h>
00053 #endif
00054
00055 #ifdef __GNUC__
00056 #ifndef CLKSEL0
00057 #define CLKSEL0 _SFR_MEM8(0XD0)
00058 #endif
00059 #ifndef CLKSEL1
00060 #define CLKSEL1 _SFR_MEM8(0XD1)
00061 #endif
00062 #ifndef CLKSTA
00063 #define CLKSTA _SFR_MEM8(0XD2)
00064 #endif
00065 #endif
00066
00070
00071
00072
00073 #define Setup_idle_mode() (SMCR=0,SMCR |= (1<<SE))
00074 #define Setup_power_down_mode() (SMCR=0,SMCR |= (1<<SE)+(1<<SM1))
00075 #define Setup_adc_noise_reduction_mode() (SMCR=0,SMCR |= (1<<SE)+(1<<SM0))
00076 #define Setup_power_save_mode() (SMCR=0,SMCR |= (1<<SE)+(1<<SM1)+(1<<SM0))
00077 #define Setup_standby_mode() (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1))
00078 #define Setup_ext_standby_mode() (SMCR=0,SMCR |= (1<<SE)+(1<<SM2)+(1<<SM1)+(1<<SM0))
00079
00089
00090 #ifdef __GNUC__
00091 #define Clear_prescaler() (clock_prescale_set(0))
00092 #else
00093 #define Clear_prescaler() (Set_cpu_prescaler(0))
00094 #endif
00095
00105 #ifdef __GNUC__
00106 #define Set_cpu_prescaler(x) (clock_prescale_set(x))
00107 #else
00108 extern void Set_cpu_prescaler(U8 x);
00109 #endif
00110
00111
00112 #define Sleep_instruction() {asm("SLEEP");}
00113
00114
00115 #define Set_power_down_mode() set_power_down_mode()
00116 #define Set_idle_mode() set_idle_mode()
00117
00118
00119
00120 void set_idle_mode(void);
00121 void set_power_down_mode(void);
00122 void set_adc_noise_reduction_mode(void);
00123 void set_power_save_mode(void);
00124 void set_standby_mode(void);
00125 void set_ext_standby_mode(void);
00126
00135 #define Enter_idle_mode() (set_idle_mode())
00136
00145 #define Enter_power_down_mode() (set_power_down_mode())
00146
00155 #define Enter_adc_noise_reduction_mode() (set_adc_noise_reduction_mode())
00156
00165 #define Enter_power_save_mode() (set_power_save_mode())
00166
00175 #define Enter_standby_mode() (set_standby_mode())
00176
00185 #define Enter_ext_standby_mode() (set_ext_standby_mode())
00186
00187
00189
00190
00191
00192
00196
00197
00198
00199
00200 #define Enable_external_clock() (CLKSEL0 |= (1<<EXTE))
00201 #define Disable_external_clock() (CLKSEL0 &= ~(1<<EXTE))
00202 #define Enable_RC_clock() (CLKSEL0 |= (1<<RCE))
00203 #define Disable_RC_clock() (CLKSEL0 &= ~(1<<RCE))
00204
00205
00206 #define External_clock_ready() (((CLKSTA&(1<<EXTON)) != 0) ? TRUE : FALSE)
00207 #define RC_clock_ready() (((CLKSTA&(1<<RCON)) != 0) ? TRUE : FALSE)
00208
00209
00210 #define Select_external_clock() (CLKSEL0 |= (1<<CLKS))
00211 #define Select_RC_clock() (CLKSEL0 &= ~(1<<CLKS))
00212
00213
00214
00215 #define Load_ext_clock_config(cfg) (CLKSEL1 = (CLKSEL1&0xF0) | ((cfg&0x0F)<<EXCKSEL0), \
00216 CLKSEL0 = (CLKSEL0&0xCF) | (((cfg&0x30)>>4)<<EXSUT0))
00217
00218 #define Load_RC_clock_config(cfg) (CLKSEL1 = (CLKSEL1&0x0F) | ((cfg&0x0F)<<RCCKSEL0), \
00219 CLKSEL0 = (CLKSEL0&0x3F) | (((cfg&0x30)>>4)<<RCSUT0))
00220
00221
00222
00223
00224
00225 #define OSC_INTRC_0MS 0x02
00226 #define OSC_INTRC_4MS 0x12
00227 #define OSC_INTRC_65MS 0x22
00228
00229
00230 #define OSC_XTAL_RANGE1_258CK_4MS 0x08
00231 #define OSC_XTAL_RANGE1_258CK_65MS 0x18
00232 #define OSC_XTAL_RANGE1_1KCK_0MS 0x28
00233 #define OSC_XTAL_RANGE1_1KCK_4MS 0x38
00234 #define OSC_XTAL_RANGE1_1KCK_65MS 0x09
00235 #define OSC_XTAL_RANGE1_16KCK_0MS 0x19
00236 #define OSC_XTAL_RANGE1_16KCK_4MS 0x29
00237 #define OSC_XTAL_RANGE1_16KCK_65MS 0x39
00238
00239
00240 #define OSC_XTAL_RANGE2_258CK_4MS 0x0A
00241 #define OSC_XTAL_RANGE2_258CK_65MS 0x1A
00242 #define OSC_XTAL_RANGE2_1KCK_0MS 0x2A
00243 #define OSC_XTAL_RANGE2_1KCK_4MS 0x3A
00244 #define OSC_XTAL_RANGE2_1KCK_65MS 0x0B
00245 #define OSC_XTAL_RANGE2_16KCK_0MS 0x1B
00246 #define OSC_XTAL_RANGE2_16KCK_4MS 0x2B
00247 #define OSC_XTAL_RANGE2_16KCK_65MS 0x3B
00248
00249
00250 #define OSC_XTAL_RANGE3_258CK_4MS 0x0C
00251 #define OSC_XTAL_RANGE3_258CK_65MS 0x1C
00252 #define OSC_XTAL_RANGE3_1KCK_0MS 0x2C
00253 #define OSC_XTAL_RANGE3_1KCK_4MS 0x3C
00254 #define OSC_XTAL_RANGE3_1KCK_65MS 0x0D
00255 #define OSC_XTAL_RANGE3_16KCK_0MS 0x1D
00256 #define OSC_XTAL_RANGE3_16KCK_4MS 0x2D
00257 #define OSC_XTAL_RANGE3_16KCK_65MS 0x3D
00258
00259
00260 #define OSC_XTAL_RANGE4_258CK_4MS 0x0E
00261 #define OSC_XTAL_RANGE4_258CK_65MS 0x1E
00262 #define OSC_XTAL_RANGE4_1KCK_0MS 0x2E
00263 #define OSC_XTAL_RANGE4_1KCK_4MS 0x3E
00264 #define OSC_XTAL_RANGE4_1KCK_65MS 0x0F
00265 #define OSC_XTAL_RANGE4_16KCK_0MS 0x1F
00266 #define OSC_XTAL_RANGE4_16KCK_4MS 0x2F
00267 #define OSC_XTAL_RANGE4_16KCK_65MS 0x3F
00268
00269
00270 #define OSC_EXTCLK_0MS 0x00
00271 #define OSC_EXTCLK_4MS 0x10
00272 #define OSC_EXTCLK_65MS 0x20
00273
00274
00275
00276
00277 void Clock_switch_external(void);
00278 void Clock_switch_internal(void);
00279
00281
00282
00283 #endif // _POWER_DRV_H_
00284