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Defines | |
#define | PLL_OUT_FRQ PLL_OUT_96MHZ |
#define | PLL_IN_PRESCAL_DISABLE ( 0<<PINDIV ) |
#define | PLL_IN_PRESCAL_ENABLE ( 1<<PINDIV ) |
#define | PLL_OUT_32MHZ ( (0<<PDIV3)| (O<<PDIV2) | (1<<PDIV1)| (0<<PDIV0)) |
#define | PLL_OUT_40MHZ ( (0<<PDIV3)| (O<<PDIV2) | (1<<PDIV1)| (1<<PDIV0)) |
#define | PLL_OUT_48MHZ ( (0<<PDIV3)| (1<<PDIV2) | (0<<PDIV1)| (0<<PDIV0)) |
#define | PLL_OUT_56MHZ ( (0<<PDIV3)| (1<<PDIV2) | (0<<PDIV1)| (1<<PDIV0)) |
#define | PLL_OUT_64MHZ ( (0<<PDIV3)| (1<<PDIV2) | (1<<PDIV1)| (0<<PDIV0)) |
#define | PLL_OUT_72MHZ ( (0<<PDIV3)| (1<<PDIV2) | (1<<PDIV1)| (1<<PDIVO)) |
#define | PLL_OUT_80MHZ ( (1<<PDIV3)| (0<<PDIV2) | (0<<PDIV1)| (0<<PDIVO)) |
#define | PLL_OUT_88MHZ ( (1<<PDIV3)| (0<<PDIV2) | (0<<PDIV1)| (1<<PDIV0)) |
#define | PLL_OUT_96MHZ ( (1<<PDIV3)| (0<<PDIV2) | (1<<PDIV1)| (0<<PDIV0)) |
#define | PLL_OUT_MSK ( (1<<PDIV3)| (1<<PDIV2) | (1<<PDIV1)| (1<<PDIV0)) |
#define | PLL_USB_DIV (1<<PLLUSB) |
#define | PLL_HS_TMR_PSCAL_NULL ( (0<<PLLTM1) | (0<<PLLTM0) ) |
#define | PLL_HS_TMR_PSCAL_1 ( (0<<PLLTM1) | (1<<PLLTM0) ) |
#define | PLL_HS_TMR_PSCAL_1DOT5 ( (1<<PLLTM1) | (0<<PLLTM0) ) |
#define | PLL_HS_TMR_PSCAL_2 ( (1<<PLLTM1) | (1<<PLLTM0) ) |
#define | PLL_HS_TMR_PSCAL_MSK ( (1<<PLLTM1) | (1<<PLLTM0) ) |
#define | Pll_set_hs_tmr_pscal_null() (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_NULL) |
#define | Pll_set_hs_tmr_pscal_1() (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_1) |
#define | Pll_set_hs_tmr_pscal_1dot5() (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_1DOT5) |
#define | Pll_set_hs_tmr_pscal_2() (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_2) |
#define | Start_pll(in_prescal) (Set_RC_pll_clock(),PLLFRQ &= ~PLL_OUT_MSK,PLLFRQ|= PLL_OUT_FRQ| PLL_USB_DIV , PLLCSR = (in_prescal | (1<<PLLE))) |
#define | Is_pll_ready() (PLLCSR & (1<<PLOCK) ) |
return 1 when PLL locked | |
#define | Wait_pll_ready() while (!(PLLCSR & (1<<PLOCK))) |
Test PLL lock bit and wait until lock is set. | |
#define | Stop_pll() (PLLCSR &= (~(1<<PLLE)),PLLCSR=0 ) |
Stop the PLL. | |
#define | Set_RC_pll_clock() (PLLFRQ |= (1<<PINMUX)) |
Select the internal RC as clock source for PLL. | |
#define | Set_XTAL_pll_clock() (PLLFRQ &= ~(1<<PINMUX)) |
Select XTAL as clock source for PLL. |
Definition in file pll_drv.h.