Static Timing Analysis

Project : Display
Build Time : 09/26/15 13:18:33
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 41.721 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
GLCD_DMA/termout \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_0 41.721 MHz 23.969 17.698
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 GLCD_DMA GLCD_DMA/clock GLCD_DMA/termout 9.000
Route 1 Net_2053 GLCD_DMA/termout \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_0 8.909
datapathcell1 U(2,0) 1 \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
GLCD_DMA/termout \GLCDPWM_1:PWMUDB:runmode_enable\/ar_0 55.860 MHz 17.902 23.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 GLCD_DMA GLCD_DMA/clock GLCD_DMA/termout 9.000
Route 1 Net_2053 GLCD_DMA/termout \GLCDPWM_1:PWMUDB:runmode_enable\/ar_0 8.902
macrocell11 U(2,0) 1 \GLCDPWM_1:PWMUDB:runmode_enable\ RECOVERY -0.000
Clock Skew 0.000
GLCD_DMA/termout Net_1953/ar_0 55.935 MHz 17.878 23.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 GLCD_DMA GLCD_DMA/clock GLCD_DMA/termout 9.000
Route 1 Net_2053 GLCD_DMA/termout Net_1953/ar_0 8.878
macrocell9 U(3,0) 1 Net_1953 RECOVERY -0.000
Clock Skew 0.000
Net_1806/q Net_1873/clk_en 84.260 MHz 11.868 29.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(2,1) 1 Net_1806 Net_1806/clock_0 Net_1806/q 1.250
Route 1 Net_1806 Net_1806/q Net_1808/main_1 2.892
macrocell4 U(2,0) 1 Net_1808 Net_1808/main_1 Net_1808/q 3.350
Route 1 Net_1808 Net_1808/q Net_1873/clk_en 2.276
macrocell6 U(2,0) 1 Net_1873 SETUP 2.100
Clock Skew 0.000
Net_1806/q Net_1889/clk_en 84.260 MHz 11.868 29.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(2,1) 1 Net_1806 Net_1806/clock_0 Net_1806/q 1.250
Route 1 Net_1806 Net_1806/q Net_1808/main_1 2.892
macrocell4 U(2,0) 1 Net_1808 Net_1808/main_1 Net_1808/q 3.350
Route 1 Net_1808 Net_1808/q Net_1889/clk_en 2.276
macrocell7 U(2,0) 1 Net_1889 SETUP 2.100
Clock Skew 0.000
Net_1806/q Net_1902/clk_en 84.260 MHz 11.868 29.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(2,1) 1 Net_1806 Net_1806/clock_0 Net_1806/q 1.250
Route 1 Net_1806 Net_1806/q Net_1808/main_1 2.892
macrocell4 U(2,0) 1 Net_1808 Net_1808/main_1 Net_1808/q 3.350
Route 1 Net_1808 Net_1808/q Net_1902/clk_en 2.276
macrocell8 U(2,0) 1 Net_1902 SETUP 2.100
Clock Skew 0.000
Net_1806/q \GLCDPWM_1:PWMUDB:genblk1:ctrlreg\/clk_en 84.260 MHz 11.868 29.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(2,1) 1 Net_1806 Net_1806/clock_0 Net_1806/q 1.250
Route 1 Net_1806 Net_1806/q Net_1808/main_1 2.892
macrocell4 U(2,0) 1 Net_1808 Net_1808/main_1 Net_1808/q 3.350
Route 1 Net_1808 Net_1808/q \GLCDPWM_1:PWMUDB:genblk1:ctrlreg\/clk_en 2.276
controlcell1 U(2,0) 1 \GLCDPWM_1:PWMUDB:genblk1:ctrlreg\ SETUP 2.100
Clock Skew 0.000
Net_1806/q \GLCDPWM_1:PWMUDB:runmode_enable\/clk_en 84.260 MHz 11.868 29.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(2,1) 1 Net_1806 Net_1806/clock_0 Net_1806/q 1.250
Route 1 Net_1806 Net_1806/q Net_1808/main_1 2.892
macrocell4 U(2,0) 1 Net_1808 Net_1808/main_1 Net_1808/q 3.350
Route 1 Net_1808 Net_1808/q \GLCDPWM_1:PWMUDB:runmode_enable\/clk_en 2.276
macrocell11 U(2,0) 1 \GLCDPWM_1:PWMUDB:runmode_enable\ SETUP 2.100
Clock Skew 0.000
Net_1806/q \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/clk_en 84.260 MHz 11.868 29.799
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(2,1) 1 Net_1806 Net_1806/clock_0 Net_1806/q 1.250
Route 1 Net_1806 Net_1806/q Net_1808/main_1 2.892
macrocell4 U(2,0) 1 Net_1808 Net_1808/main_1 Net_1808/q 3.350
Route 1 Net_1808 Net_1808/q \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/clk_en 2.276
datapathcell1 U(2,0) 1 \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 2.100
Clock Skew 0.000
\GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \GLCDPWM_2:PWMUDB:genblk8:stsreg\/status_2 89.063 MHz 11.228 30.439
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/clock \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \GLCDPWM_2:PWMUDB:tc_i\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/z0_comb \GLCDPWM_2:PWMUDB:status_2\/main_1 2.770
macrocell17 U(2,1) 1 \GLCDPWM_2:PWMUDB:status_2\ \GLCDPWM_2:PWMUDB:status_2\/main_1 \GLCDPWM_2:PWMUDB:status_2\/q 3.350
Route 1 \GLCDPWM_2:PWMUDB:status_2\ \GLCDPWM_2:PWMUDB:status_2\/q \GLCDPWM_2:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(2,1) 1 \GLCDPWM_2:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\GLCDPWM_2:PWMUDB:status_1\/q \GLCDPWM_2:PWMUDB:genblk8:stsreg\/status_1 1.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,1) 1 \GLCDPWM_2:PWMUDB:status_1\ \GLCDPWM_2:PWMUDB:status_1\/clock_0 \GLCDPWM_2:PWMUDB:status_1\/q 1.250
Route 1 \GLCDPWM_2:PWMUDB:status_1\ \GLCDPWM_2:PWMUDB:status_1\/q \GLCDPWM_2:PWMUDB:genblk8:stsreg\/status_1 2.314
statusicell1 U(2,1) 1 \GLCDPWM_2:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\GLCDPWM_2:PWMUDB:status_0\/q \GLCDPWM_2:PWMUDB:genblk8:stsreg\/status_0 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,1) 1 \GLCDPWM_2:PWMUDB:status_0\ \GLCDPWM_2:PWMUDB:status_0\/clock_0 \GLCDPWM_2:PWMUDB:status_0\/q 1.250
Route 1 \GLCDPWM_2:PWMUDB:status_0\ \GLCDPWM_2:PWMUDB:status_0\/q \GLCDPWM_2:PWMUDB:genblk8:stsreg\/status_0 2.323
statusicell1 U(2,1) 1 \GLCDPWM_2:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\GLCDPWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \GLCDPWM_1:PWMUDB:runmode_enable\/main_0 2.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,0) 1 \GLCDPWM_1:PWMUDB:genblk1:ctrlreg\ \GLCDPWM_1:PWMUDB:genblk1:ctrlreg\/clock \GLCDPWM_1:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \GLCDPWM_1:PWMUDB:control_7\ \GLCDPWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \GLCDPWM_1:PWMUDB:runmode_enable\/main_0 2.240
macrocell11 U(2,0) 1 \GLCDPWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\GLCDPWM_2:PWMUDB:genblk1:ctrlreg\/control_7 \GLCDPWM_2:PWMUDB:runmode_enable\/main_0 2.700
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \GLCDPWM_2:PWMUDB:genblk1:ctrlreg\ \GLCDPWM_2:PWMUDB:genblk1:ctrlreg\/clock \GLCDPWM_2:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \GLCDPWM_2:PWMUDB:control_7\ \GLCDPWM_2:PWMUDB:genblk1:ctrlreg\/control_7 \GLCDPWM_2:PWMUDB:runmode_enable\/main_0 2.340
macrocell14 U(2,1) 1 \GLCDPWM_2:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\GLCD_UPDATE:Sync:ctrl_reg\/control_0 Net_1953/clk_en 2.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(3,0) 1 \GLCD_UPDATE:Sync:ctrl_reg\ \GLCD_UPDATE:Sync:ctrl_reg\/busclk \GLCD_UPDATE:Sync:ctrl_reg\/control_0 0.620
Route 1 Net_199 \GLCD_UPDATE:Sync:ctrl_reg\/control_0 Net_1953/clk_en 2.226
macrocell9 U(3,0) 1 Net_1953 HOLD 0.000
Clock Skew 0.000
\GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1889/main_1 3.008
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\ \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/clock \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \GLCDPWM_1:PWMUDB:cmp1_less\ \GLCDPWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1889/main_1 2.228
macrocell7 U(2,0) 1 Net_1889 HOLD 0.000
Clock Skew 0.000
\GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1806/main_1 3.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/clock \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \GLCDPWM_2:PWMUDB:cmp1_less\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1806/main_1 2.292
macrocell3 U(2,1) 1 Net_1806 HOLD 0.000
Clock Skew 0.000
\GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \GLCDPWM_2:PWMUDB:prevCompare1\/main_0 3.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/clock \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \GLCDPWM_2:PWMUDB:cmp1_less\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \GLCDPWM_2:PWMUDB:prevCompare1\/main_0 2.292
macrocell12 U(2,1) 1 \GLCDPWM_2:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \GLCDPWM_2:PWMUDB:status_0\/main_1 3.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,1) 1 \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/clock \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \GLCDPWM_2:PWMUDB:cmp1_less\ \GLCDPWM_2:PWMUDB:sP8:pwmdp:u0\/cl0_comb \GLCDPWM_2:PWMUDB:status_0\/main_1 2.292
macrocell15 U(2,1) 1 \GLCDPWM_2:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\GLCDPWM_2:PWMUDB:prevCompare1\/q \GLCDPWM_2:PWMUDB:status_0\/main_0 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,1) 1 \GLCDPWM_2:PWMUDB:prevCompare1\ \GLCDPWM_2:PWMUDB:prevCompare1\/clock_0 \GLCDPWM_2:PWMUDB:prevCompare1\/q 1.250
Route 1 \GLCDPWM_2:PWMUDB:prevCompare1\ \GLCDPWM_2:PWMUDB:prevCompare1\/q \GLCDPWM_2:PWMUDB:status_0\/main_0 2.295
macrocell15 U(2,1) 1 \GLCDPWM_2:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
Net_1902/q GLCDC(1)_PAD 30.463
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,0) 1 Net_1902 Net_1902/clock_0 Net_1902/q 1.250
Route 1 Net_1902 Net_1902/q Net_1501/main_0 3.713
macrocell1 U(2,0) 1 Net_1501 Net_1501/main_0 Net_1501/q 3.350
Route 1 Net_1501 Net_1501/q GLCDC(1)/pin_input 6.217
iocell2 P12[1] 1 GLCDC(1) GLCDC(1)/pin_input GLCDC(1)/pad_out 15.933
Route 1 GLCDC(1)_PAD GLCDC(1)/pad_out GLCDC(1)_PAD 0.000
Clock Clock path delay 0.000
Net_1902/q GLCDC(0)_PAD 30.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,0) 1 Net_1902 Net_1902/clock_0 Net_1902/q 1.250
Route 1 Net_1902 Net_1902/q Net_1502/main_0 3.713
macrocell2 U(2,0) 1 Net_1502 Net_1502/main_0 Net_1502/q 3.350
Route 1 Net_1502 Net_1502/q GLCDC(0)/pin_input 6.240
iocell1 P12[0] 1 GLCDC(0) GLCDC(0)/pin_input GLCDC(0)/pad_out 15.855
Route 1 GLCDC(0)_PAD GLCDC(0)/pad_out GLCDC(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1844/q GLCDC(4)_PAD 29.320
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,1) 1 Net_1844 Net_1844/clock_0 Net_1844/q 1.250
Route 1 Net_1844 Net_1844/q Net_2051/main_1 2.881
macrocell10 U(2,0) 1 Net_2051 Net_2051/main_1 Net_2051/q 3.350
Route 1 Net_2051 Net_2051/q GLCDC(4)/pin_input 7.055
iocell5 P5[7] 1 GLCDC(4) GLCDC(4)/pin_input GLCDC(4)/pad_out 14.784
Route 1 GLCDC(4)_PAD GLCDC(4)/pad_out GLCDC(4)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_5 GLCDD(5)_PAD 24.010
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_5 2.050
Route 1 Net_131 \GLCD_DATA:Sync:ctrl_reg\/control_5 GLCDD(5)/pin_input 6.622
iocell12 P3[5] 1 GLCDD(5) GLCDD(5)/pin_input GLCDD(5)/pad_out 15.338
Route 1 GLCDD(5)_PAD GLCDD(5)/pad_out GLCDD(5)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_0 GLCDD(0)_PAD 23.248
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_126 \GLCD_DATA:Sync:ctrl_reg\/control_0 GLCDD(0)/pin_input 6.578
iocell7 P3[0] 1 GLCDD(0) GLCDD(0)/pin_input GLCDD(0)/pad_out 14.620
Route 1 GLCDD(0)_PAD GLCDD(0)/pad_out GLCDD(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1902/q GLCDC(3)_PAD 22.883
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,0) 1 Net_1902 Net_1902/clock_0 Net_1902/q 1.250
Route 1 Net_1902 Net_1902/q GLCDC(3)/pin_input 7.243
iocell4 P5[5] 1 GLCDC(3) GLCDC(3)/pin_input GLCDC(3)/pad_out 14.390
Route 1 GLCDC(3)_PAD GLCDC(3)/pad_out GLCDC(3)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_4 GLCDD(4)_PAD 22.788
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_4 2.050
Route 1 Net_130 \GLCD_DATA:Sync:ctrl_reg\/control_4 GLCDD(4)/pin_input 5.751
iocell11 P3[4] 1 GLCDD(4) GLCDD(4)/pin_input GLCDD(4)/pad_out 14.987
Route 1 GLCDD(4)_PAD GLCDD(4)/pad_out GLCDD(4)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_2 GLCDD(2)_PAD 22.764
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_2 2.050
Route 1 Net_128 \GLCD_DATA:Sync:ctrl_reg\/control_2 GLCDD(2)/pin_input 5.719
iocell9 P3[2] 1 GLCDD(2) GLCDD(2)/pin_input GLCDD(2)/pad_out 14.995
Route 1 GLCDD(2)_PAD GLCDD(2)/pad_out GLCDD(2)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_7 GLCDD(7)_PAD 22.727
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_7 2.050
Route 1 Net_133 \GLCD_DATA:Sync:ctrl_reg\/control_7 GLCDD(7)/pin_input 5.516
iocell14 P3[7] 1 GLCDD(7) GLCDD(7)/pin_input GLCDD(7)/pad_out 15.161
Route 1 GLCDD(7)_PAD GLCDD(7)/pad_out GLCDD(7)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_1 GLCDD(1)_PAD 22.586
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_1 2.050
Route 1 Net_127 \GLCD_DATA:Sync:ctrl_reg\/control_1 GLCDD(1)/pin_input 5.557
iocell8 P3[1] 1 GLCDD(1) GLCDD(1)/pin_input GLCDD(1)/pad_out 14.979
Route 1 GLCDD(1)_PAD GLCDD(1)/pad_out GLCDD(1)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_3 GLCDD(3)_PAD 22.452
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_3 2.050
Route 1 Net_129 \GLCD_DATA:Sync:ctrl_reg\/control_3 GLCDD(3)/pin_input 5.811
iocell10 P3[3] 1 GLCDD(3) GLCDD(3)/pin_input GLCDD(3)/pad_out 14.591
Route 1 GLCDD(3)_PAD GLCDD(3)/pad_out GLCDD(3)_PAD 0.000
Clock Clock path delay 0.000
\GLCD_DATA:Sync:ctrl_reg\/control_6 GLCDD(6)_PAD 22.200
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,1) 1 \GLCD_DATA:Sync:ctrl_reg\ \GLCD_DATA:Sync:ctrl_reg\/busclk \GLCD_DATA:Sync:ctrl_reg\/control_6 2.050
Route 1 Net_132 \GLCD_DATA:Sync:ctrl_reg\/control_6 GLCDD(6)/pin_input 5.559
iocell13 P3[6] 1 GLCDD(6) GLCDD(6)/pin_input GLCDD(6)/pad_out 14.591
Route 1 GLCDD(6)_PAD GLCDD(6)/pad_out GLCDD(6)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
GLCD_DMA/termout \GLCDPWM_1:PWMUDB:runmode_enable\/ar_0 55.860 MHz 17.902 23.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 GLCD_DMA GLCD_DMA/clock GLCD_DMA/termout 9.000
Route 1 Net_2053 GLCD_DMA/termout \GLCDPWM_1:PWMUDB:runmode_enable\/ar_0 8.902
macrocell11 U(2,0) 1 \GLCDPWM_1:PWMUDB:runmode_enable\ RECOVERY -0.000
Clock Skew 0.000
GLCD_DMA/termout Net_1953/ar_0 55.935 MHz 17.878 23.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 GLCD_DMA GLCD_DMA/clock GLCD_DMA/termout 9.000
Route 1 Net_2053 GLCD_DMA/termout Net_1953/ar_0 8.878
macrocell9 U(3,0) 1 Net_1953 RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
GLCD_DMA/termout Net_1953/ar_0 17.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 GLCD_DMA GLCD_DMA/clock GLCD_DMA/termout 9.000
Route 1 Net_2053 GLCD_DMA/termout Net_1953/ar_0 8.878
macrocell9 U(3,0) 1 Net_1953 REMOVAL 0.000
Clock Skew 0.000
GLCD_DMA/termout \GLCDPWM_1:PWMUDB:runmode_enable\/ar_0 17.902
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 GLCD_DMA GLCD_DMA/clock GLCD_DMA/termout 9.000
Route 1 Net_2053 GLCD_DMA/termout \GLCDPWM_1:PWMUDB:runmode_enable\/ar_0 8.902
macrocell11 U(2,0) 1 \GLCDPWM_1:PWMUDB:runmode_enable\ REMOVAL 0.000
Clock Skew 0.000