BrieySOC Project Status (04/21/2019 - 18:33:57) | |||
Project File: | BrieySoC01.xise | Parser Errors: | No Errors |
Module Name: | BrieySOC | Implementation State: | Translated (Failed) |
Target Device: | xc6slx9-3csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 3223 | 11440 | 28% | |
Number of Slice LUTs | 4552 | 5720 | 79% | |
Number of fully used LUT-FF pairs | 2346 | 5429 | 43% | |
Number of bonded IOBs | 81 | 200 | 40% | |
Number of Block RAM/FIFO | 7 | 32 | 21% | |
Number of BUFG/BUFGCTRLs | 6 | 16 | 37% | |
Number of DSP48A1s | 4 | 16 | 25% | |
Number of PLL_ADVs | 1 | 2 | 50% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | niedz. 21. kwi 18:33:47 2019 | ||||
Translation Report | Current | niedz. 21. kwi 18:33:55 2019 | X 2 Errors (2 new) | 0 | 2 Infos (0 new) | |
Map Report | Out of Date | sob. 20. kwi 13:31:32 2019 | 0 | 8 Warnings (0 new) | 9 Infos (0 new) | |
Place and Route Report | Out of Date | sob. 20. kwi 13:32:31 2019 | 0 | 9 Warnings (0 new) | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | sob. 20. kwi 13:32:46 2019 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report | Out of Date | pon. 15. kwi 17:26:14 2019 | 0 | 8 Warnings (7 new) | 1 Info (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | pon. 15. kwi 17:26:14 2019 | |
WebTalk Log File | Out of Date | pon. 15. kwi 17:26:18 2019 |