BrieySOC Project Status (04/21/2019 - 18:33:57)
Project File: BrieySoC01.xise Parser Errors: No Errors
Module Name: BrieySOC Implementation State: Translated (Failed)
Target Device: xc6slx9-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 3223 11440 28%
Number of Slice LUTs 4552 5720 79%
Number of fully used LUT-FF pairs 2346 5429 43%
Number of bonded IOBs 81 200 40%
Number of Block RAM/FIFO 7 32 21%
Number of BUFG/BUFGCTRLs 6 16 37%
Number of DSP48A1s 4 16 25%
Number of PLL_ADVs 1 2 50%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentniedz. 21. kwi 18:33:47 2019   
Translation ReportCurrentniedz. 21. kwi 18:33:55 2019X 2 Errors (2 new)02 Infos (0 new)
Map ReportOut of Datesob. 20. kwi 13:31:32 201908 Warnings (0 new)9 Infos (0 new)
Place and Route ReportOut of Datesob. 20. kwi 13:32:31 201909 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportOut of Datesob. 20. kwi 13:32:46 2019003 Infos (0 new)
Bitgen ReportOut of Datepon. 15. kwi 17:26:14 201908 Warnings (7 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Datepon. 15. kwi 17:26:14 2019
WebTalk Log FileOut of Datepon. 15. kwi 17:26:18 2019

Date Generated: 04/21/2019 - 18:33:57