Briey Project Status (04/15/2019 - 17:26:17)
Project File: BrieySoC01.xise Parser Errors: No Errors
Module Name: Briey Implementation State: Programming File Generated
Target Device: xc6slx9-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,219 11,440 28%  
    Number used as Flip Flops 3,219      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 4,073 5,720 71%  
    Number used as logic 3,427 5,720 59%  
        Number using O6 output only 2,574      
        Number using O5 output only 176      
        Number using O5 and O6 677      
        Number used as ROM 0      
    Number used as Memory 568 1,440 39%  
        Number used as Dual Port RAM 40      
            Number using O6 output only 12      
            Number using O5 output only 0      
            Number using O5 and O6 28      
        Number used as Single Port RAM 512      
            Number using O6 output only 512      
            Number using O5 output only 0      
            Number using O5 and O6 0      
        Number used as Shift Register 16      
            Number using O6 output only 11      
            Number using O5 output only 0      
            Number using O5 and O6 5      
    Number used exclusively as route-thrus 78      
        Number with same-slice register load 61      
        Number with same-slice carry load 17      
        Number with other load 0      
Number of occupied Slices 1,316 1,430 92%  
Number of MUXCYs used 652 2,860 22%  
Number of LUT Flip Flop pairs used 4,553      
    Number with an unused Flip Flop 1,619 4,553 35%  
    Number with an unused LUT 480 4,553 10%  
    Number of fully used LUT-FF pairs 2,454 4,553 53%  
    Number of unique control sets 156      
    Number of slice register sites lost
        to control set restrictions
444 11,440 3%  
Number of bonded IOBs 98 200 49%  
Number of RAMB16BWERs 3 32 9%  
Number of RAMB8BWERs 8 64 12%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 4 16 25%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.26      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentpon. 15. kwi 15:00:56 2019   
Translation ReportCurrentpon. 15. kwi 15:01:01 2019   
Map ReportCurrentpon. 15. kwi 15:02:06 2019   
Place and Route ReportCurrentpon. 15. kwi 15:02:46 2019   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentpon. 15. kwi 15:02:52 2019   
Bitgen ReportOut of Datepon. 15. kwi 14:59:40 2019   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentpon. 15. kwi 17:26:13 2019
WebTalk Log FileCurrentpon. 15. kwi 17:26:16 2019

Date Generated: 04/15/2019 - 17:26:17