BrieySOC Project Status
Project File: BrieySoC01.xise Parser Errors: No Errors
Module Name: BrieySOC Implementation State: Placed and Routed
Target Device: xc6slx9-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,228 11,440 28%  
    Number used as Flip Flops 3,228      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 4,051 5,720 70%  
    Number used as logic 3,438 5,720 60%  
        Number using O6 output only 2,557      
        Number using O5 output only 174      
        Number using O5 and O6 707      
        Number used as ROM 0      
    Number used as Memory 568 1,440 39%  
        Number used as Dual Port RAM 40      
            Number using O6 output only 12      
            Number using O5 output only 0      
            Number using O5 and O6 28      
        Number used as Single Port RAM 512      
            Number using O6 output only 512      
            Number using O5 output only 0      
            Number using O5 and O6 0      
        Number used as Shift Register 16      
            Number using O6 output only 11      
            Number using O5 output only 0      
            Number using O5 and O6 5      
    Number used exclusively as route-thrus 45      
        Number with same-slice register load 30      
        Number with same-slice carry load 15      
        Number with other load 0      
Number of occupied Slices 1,346 1,430 94%  
Number of MUXCYs used 652 2,860 22%  
Number of LUT Flip Flop pairs used 4,589      
    Number with an unused Flip Flop 1,643 4,589 35%  
    Number with an unused LUT 538 4,589 11%  
    Number of fully used LUT-FF pairs 2,408 4,589 52%  
    Number of unique control sets 157      
    Number of slice register sites lost
        to control set restrictions
451 11,440 3%  
Number of bonded IOBs 98 200 49%  
Number of RAMB16BWERs 3 32 9%  
Number of RAMB8BWERs 8 64 12%  
Number of BUFIO2/BUFIO2_2CLKs 2 32 6%  
    Number used as BUFIO2s 2      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 2 32 6%  
    Number used as BUFIO2FBs 2      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 5 16 31%  
    Number used as BUFGs 5      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 4 16 25%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.30      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentpon. 15. kwi 17:22:56 2019   
Translation ReportCurrentwt. 16. kwi 15:43:34 2019000
Map ReportCurrentwt. 16. kwi 15:44:54 201908 Warnings (0 new)8 Infos (0 new)
Place and Route ReportCurrentwt. 16. kwi 15:45:37 201909 Warnings (0 new)3 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentwt. 16. kwi 15:45:44 2019004 Infos (0 new)
Bitgen ReportOut of Datepon. 15. kwi 17:26:13 201908 Warnings (7 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Datepon. 15. kwi 17:26:13 2019
WebTalk Log FileOut of Datepon. 15. kwi 17:26:16 2019

Date Generated: 04/17/2019 - 14:55:26