System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC		 .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
Path E:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
E:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
E:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
E:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
E:\Xilinx\14.7\ISE_DS\common\bin\nt;
E:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Program Files (x86)\Common Files\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Editor\WinMerge;
C:\Tools\PuTTY\;
C:\Program Files (x86)\STMicroelectronics\STM32 ST-LINK Utility\ST-LINK Utility;
C:\Users\MGabryelski.FAM\AppData\Local\Microsoft\WindowsApps;
C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem		 E:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
E:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
E:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
E:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
E:\Xilinx\14.7\ISE_DS\common\bin\nt;
E:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Program Files (x86)\Common Files\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Editor\WinMerge;
C:\Tools\PuTTY\;
C:\Program Files (x86)\STMicroelectronics\STM32 ST-LINK Utility\ST-LINK Utility;
C:\Users\MGabryelski.FAM\AppData\Local\Microsoft\WindowsApps;
C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem		 E:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
E:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
E:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
E:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
E:\Xilinx\14.7\ISE_DS\common\bin\nt;
E:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Program Files (x86)\Common Files\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Editor\WinMerge;
C:\Tools\PuTTY\;
C:\Program Files (x86)\STMicroelectronics\STM32 ST-LINK Utility\ST-LINK Utility;
C:\Users\MGabryelski.FAM\AppData\Local\Microsoft\WindowsApps;
C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem		 E:\Xilinx\14.7\ISE_DS\ISE\\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\bin\nt;
E:\Xilinx\14.7\ISE_DS\ISE\lib\nt;
E:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;
E:\Xilinx\14.7\ISE_DS\PlanAhead\bin;
E:\Xilinx\14.7\ISE_DS\EDK\bin\nt;
E:\Xilinx\14.7\ISE_DS\EDK\lib\nt;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_be\bin;
E:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt_le\bin;
E:\Xilinx\14.7\ISE_DS\common\bin\nt;
E:\Xilinx\14.7\ISE_DS\common\lib\nt;
C:\Program Files (x86)\Common Files\Oracle\Java\javapath;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Windows\System32\OpenSSH\;
C:\Editor\WinMerge;
C:\Tools\PuTTY\;
C:\Program Files (x86)\STMicroelectronics\STM32 ST-LINK Utility\ST-LINK Utility;
C:\Users\MGabryelski.FAM\AppData\Local\Microsoft\WindowsApps;
C:\intelFPGA_lite\18.1\modelsim_ase\win32aloem
XILINX E:\Xilinx\14.7\ISE_DS\ISE\ E:\Xilinx\14.7\ISE_DS\ISE\ E:\Xilinx\14.7\ISE_DS\ISE\ E:\Xilinx\14.7\ISE_DS\ISE\
XILINX_DSP E:\Xilinx\14.7\ISE_DS\ISE E:\Xilinx\14.7\ISE_DS\ISE E:\Xilinx\14.7\ISE_DS\ISE E:\Xilinx\14.7\ISE_DS\ISE
XILINX_EDK E:\Xilinx\14.7\ISE_DS\EDK E:\Xilinx\14.7\ISE_DS\EDK E:\Xilinx\14.7\ISE_DS\EDK E:\Xilinx\14.7\ISE_DS\EDK
XILINX_PLANAHEAD E:\Xilinx\14.7\ISE_DS\PlanAhead E:\Xilinx\14.7\ISE_DS\PlanAhead E:\Xilinx\14.7\ISE_DS\PlanAhead E:\Xilinx\14.7\ISE_DS\PlanAhead
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   BrieySOC.prj  
-ofn   BrieySOC  
-ofmt   NGC NGC
-p   xc6slx9-3-csg324  
-top   BrieySOC  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-sd Cores Search Directories {"ipcore_dir" }  
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Translation Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise None
-dd   _ngo None
-p   xc6slx9-csg324-3 None
-sd Macro Search Path ipcore_dir None
 
Map Property Settings
Switch Name Property Name Value Default Value
-ol Place & Route Effort Level (Overall) high high
-xt Extra Cost Tables 0 0
-ir Use RLOC Constraints OFF OFF
-t Starting Placer Cost Table (1-100) Map 1 0
-r Register Ordering 4 4
-intstyle   ise None
-lc LUT Combining off off
-o   BrieySOC_map.ncd None
-w   true false
-pr Pack I/O Registers/Latches into IOBs off off
-p   xc6slx9-csg324-3 None
 
Place and Route Property Settings
Switch Name Property Name Value Default Value
-intstyle   ise  
-mt Enable Multi-Threading off off
-ol Place & Route Effort Level (Overall) high std
-w   true false
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz/2208 MHz Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz/2208 MHz Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz/2208 MHz Intel(R) Core(TM) i7-8750H CPU @ 2.20GHz/2208 MHz
Host 740-30 740-30 740-30 740-30
OS Name Microsoft , 64-bit Microsoft , 64-bit Microsoft , 64-bit Microsoft , 64-bit
OS Release major release (build 9200) major release (build 9200) major release (build 9200) major release (build 9200)