# Activity Stream

• Today, 21:15
Anyone??:cry:
1 replies | 123 view(s)
• Today, 21:01
Almost, the diode is in the right place but the arrow should point upwards. As shown it will conduct when the switch is pressed and divert the...
5 replies | 186 view(s)
• Today, 20:54
Thanks, KlausST. Could you plz introduce a source that explains the design procedure?
4 replies | 66 view(s)
• Today, 20:52
I know the relationship. need a circuit.
4 replies | 66 view(s)
• Today, 20:40
Dear friends, Suppose I have desinged a simple single-ended two-stage miller op-amp (seen in the image below)to drive Capacitive load CL and...
0 replies | 8 view(s)
• Today, 20:27
Hi, A low pass filter? Klaus
4 replies | 66 view(s)
• Today, 20:15
Dear friends, I recieved an answer from Cadence, there are two solutions: 1. Simulation using ADE Explorer to set up the surrounding sweep,...
7 replies | 377 view(s)
• Today, 20:13
Vmean=Vpeak*(thau/Period) thau:duty cycle
4 replies | 66 view(s)
• Today, 20:06
You say ADC and then you mention PWM, which is DAC. Which are you really trying to do? It it's PWM DAC, what is the highest modulation frequency...
2 replies | 42 view(s)
• Today, 18:57
I know such very basic thing. No. is not a Hermitian matrix. Here T means transpose of , + means conjugate transpose of . For lossless...
2 replies | 231 view(s)
• Today, 18:50
Hello, I am new to multisim and just started learning how to simulate basic circuits. I am using multisim 12.0. I am trying to simulate a basic...
0 replies | 6 view(s)
• Today, 18:14
Hi, This might seem silly but I need a circuit to detect the average value of a square waveform (0-1V), with frequencies below 20KHz. The duty...
4 replies | 66 view(s)
• Today, 17:28
Hi, To be honest: I donīt know the answer. * maybe the copper loss is tested with DC. Then there are additional losses caused by AC: Proximity...
2 replies | 86 view(s)
• Today, 17:20
You attachment 156028 returns an "invalid attachment" error. I am also curious what they mean parasitic leakage inductance losses. What I can...
2 replies | 86 view(s)
• Today, 17:20
Hi, Read RS232 specifications. There is no need for 11V. If Im not mistaken, then even 3V / -3V levels comply with RS232. If your connected...
1 replies | 57 view(s)
• Today, 17:13
Hi, I donīt think this is possible. Most probably the power has a a capacitor at the ouput. It needs a lot of power to charge this capacitor...
5 replies | 101 view(s)
• Today, 17:07
I believe that you are using an incorrect problem description. What I believe you are describing, based on your description, is an input transient...
5 replies | 101 view(s)
• Today, 17:05
Hi, We donīt know about your circuit. We donīt know what kind of ADC you try to build. We donīt know what cutoff frequency you like to have. ...
2 replies | 42 view(s)
• Today, 17:05
Sweep Vtune and look at Vout in dBm for first harmonic ( or whatsoever..) ..very simple.
1 replies | 84 view(s)
• Today, 17:01
If your signal has enough amplitude I would think that using the level detection method should be the easiest; noise shouldn't be an issue. What is...
5 replies | 278 view(s)
• Today, 16:56
To me you should be concentrating on the synthesis warnings and determine why the FSM current_state (flip-flops) are getting removed. Registers...
7 replies | 353 view(s)
• Today, 16:56
some time ago i needed a portable power supply that could lit led arrays so i can test various tv sets brought to my repair shop,so i decided to...
0 replies | 48 view(s)
• Today, 16:55
How are you testing this? How are you applying a "2KV surge"? How are you measuring it? What are its characteristics? Are you picking up something...
5 replies | 101 view(s)
• Today, 16:28
Hello, I need to simulate the input capacitor of a CMOS gates. Particularly now I am interested to see the input capacitance at the clk input of...
0 replies | 30 view(s)
• Today, 16:09
I forgot to add a few details to my post: 1. I have already began testing with SignalTap, just a different, earlier version of the design (since it...
7 replies | 353 view(s)
• Today, 15:48
There are also a number of the more complex cores written by companies advertising their expertise, if you go to the website of the company...
4 replies | 255 view(s)
• Today, 15:41
Add signal tap after the design is implemented (i.e. synth+par) The flip-flops for the FSM will exist in the routed design. Either that or...
7 replies | 353 view(s)
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