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How to make Verilog Code to a matlab subsystem
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> How to make Verilog Code to a matlab subsystem
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sudhirkv



Joined: 13 Dec 2005
Posts: 79
Helped: 4
Location: Chennai, India
Post05 Nov 2009 6:11   

How to make Verilog Code to a matlab subsystem
Hi all,

I Have verilog code and i need to include it as subsystem block in matlab. is it possible?

If so how?

Thanks

Sudhir
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medra



Joined: 15 Oct 2006
Posts: 140
Helped: 27
Location: Egypt
Post05 Nov 2009 22:31   

Re: How to make Verilog Code to a matlab subsystem
I don't know much details , but I heard that their is a block called link to model sim block may do so.


Also you may rewrite it in embedded matlab form.
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ckaa



Joined: 06 Apr 2006
Posts: 15
Helped: 4
Post05 Nov 2009 23:01   

Re: How to make Verilog Code to a matlab subsystem
Check out this old link on the forum. They talk about what you want. You may find it useful
http://www.edaboard.com/ftopic291327.html
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Post05 Nov 2009 23:01   

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LinXiaoling



Joined: 25 Feb 2008
Posts: 28
Helped: 2
Post06 Nov 2009 4:43   

Re: How to make Verilog Code to a matlab subsystem
use simulink for modelsim.
see simulink for modelsim on matlab manual in detail
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