Clock and data recovery circuit

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xwcwc1234

Joined: 21 Jul 2001
Posts: 316
Helped: 5

08 Dec 2004 10:31 Clock and data recovery circuit

Hi all,
I need to design a 10MHz clock and data recovery circuit . Anyone has some ideas on this subject ( includes phase detector , VCO and others )?

lianming1

Joined: 11 Jan 2004
Posts: 45
Helped: 4

09 Dec 2004 7:24 Clock and data recovery circuit

maybe you can take look book by razavi

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xwcwc1234

Joined: 21 Jul 2001
Posts: 316
Helped: 5

09 Dec 2004 7:36 Re: Clock and data recovery circuit

Yes, I've read Razivi's book on this subject. But , for almost CDR circuits , there are no frequency detector has wide capture range. That's the problem. My VCO always has large variation under process variations and voltage , temperature etc.

sutapanaki

Joined: 02 Nov 2001
Posts: 580
Helped: 33

09 Dec 2004 22:34 Re: Clock and data recovery circuit

Your incoming data has been clocked at the transmitter end with a certain frequency which you should know approximately - say 10MHz. Why not lock your VCO first to a regular clock of 10MHz using a PFD, charge pump etc. like a PLL and after it is locked then switch over to a phase detector receiving your real data and do the recovery. This way your VCO is already oscillating at a frequency close to the correct one and all you have to do is capture the phase with respect to the data.

xwcwc1234

Joined: 21 Jul 2001
Posts: 316
Helped: 5

10 Dec 2004 5:04 Re: Clock and data recovery circuit

Unfortunately, my circuit has no auxiluary PLL reference input , so that I can not lock the VCO into a known frequency . I'm looking for a circuit that can be used as PFD in CDR . That's what I want.

sutapanaki

Joined: 02 Nov 2001
Posts: 580
Helped: 33

10 Dec 2004 7:59 Re: Clock and data recovery circuit

Then you should probably know that the data (for example NRZ) does not contain enrgy at the clock frequency and it is hard to use somethink like a PFD to lock to something that's not there. Have you thought about doing edge detection to create energy at the clock frequency?

andy1

Joined: 24 Jul 2004
Posts: 126
Helped: 2

13 Dec 2004 0:46 Re: Clock and data recovery circuit

Can you describe more in detail what type of input signal format (NRZ, manchester...). Not only have to lock the clock to the local oscilator, you have to lock to the incomming signal also. It can get complicated. I beleive there are IC that is used in ethernet and LAN application you can use.

Please see the attached file for some basic idea.

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aicer

Joined: 20 Oct 2004
Posts: 7

14 Dec 2004 17:01 Clock and data recovery circuit

i guess your architecture are Dual-Loop without reference clock signal...you need PD FD CPs LPF&VCO..Linear phase PD is suitable for your design. It's okay for 10MHz data rate,all of the design skills you can check the papers.The close loop analysis of PD part is similar to the PLL,one of the FD part to check the rotational frequency detector.Remember,the VCO need to generate multi-phase(0 90 180 270 or 0 45 90...etc) due to the FD requirements.I suggest a paper about the FD part for u "A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet"(author:Shen-Iuan Liu et al.)

CDRCDR

Joined: 15 Feb 2004
Posts: 82
Helped: 2

14 Dec 2004 21:24 Clock and data recovery circuit

I recommend Potbaker's PFD for you to use,in which the double edged DFFs are used to construct the phase detection,then two phase detecor(I/Q) construct a PFD.It doesn't need reference clock

andy1

Joined: 24 Jul 2004
Posts: 126
Helped: 2

15 Dec 2004 5:46 Re: Clock and data recovery circuit

I still think the term "clock recovery" a little misleading since, at least in most implementation, there is alway a local clock so there is no need "to recover the clock" from anywhere.

What usually happens is that the already existing local clock needs to align its phase to the imcomming data. This local clock is usually derived from a local oscillator.

The term "clock alignment" is more descriptive.

aicer

Joined: 20 Oct 2004
Posts: 7

18 Dec 2004 12:21 Clock and data recovery circuit

indeed,just like andy1 saying.There are usually a reference clock in many CDR design.reference clock could improve aquisition time and design circuit much easier.In my thesis,I design a CDR with referenceless clock. i met many issues that would not exist in CDR with reference clock.So...maybe u should change your topology if you can or somebody permit.