design cpu

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zhoury

Joined: 25 Apr 2002
Posts: 27

05 Jul 2002 9:49 design cpu

Now i have a preject to design a 64 bit cpu . I have some question to ask whom have experience in doing that.pls pm me if you have experience with that and glad to help others.

gabby

Joined: 18 Mar 2002
Posts: 97
Location: Israel

05 Jul 2002 10:05

Hi

you have some info of vhdl cpu core at:

www.opencores.org

also you can ask there.

Best regards.

zhoury

Joined: 25 Apr 2002
Posts: 27

05 Jul 2002 13:48

First thanks for gabby.
Now i am involving in designing a real more complex cpu than embedded cpu. This is designed compatible for intel IA64.So now i want to make friends with those who have made work for intel or ibm.I need to know how they design such cpu .

Ace-X

Joined: 25 Jan 2002
Posts: 590
Helped: 26

05 Jul 2002 14:53

IA-64?

No chances!!! Probably, it's the most complicated processor on the market. It supports dynamic code translation from x86 code (CISC architecture) to internal VLIW representation. I tell you more: the main reason why there is no commercially available VLIW processors is that these kind of processor needs very complicated compiler, that will be able to look through different branches in your algorithm and will translate it to the long-word command. These guys (from Intel and HP) made even more crazy thing - they implemented this compiler in hardware! They designed it for several years.
And now, how do you think, when you'll finish this design? I expect it will be in 20 years, if you'll be lucky!?

With best wishes,

Ace-X.

zhoury

Joined: 25 Apr 2002
Posts: 27

05 Jul 2002 15:25 I am not joker.

I am seriously. If someone is interested in helping me pls pm me. Now we have experience for developing chinset about 4 million gates and want to do more. Now i am new for design cpu and want to know the difference between chipset and cpu. I want to know the basic for design such cpu especialy how to design the low macro such alu.We have design using synopsys dc and designware .But i think it is not proper method for cpu because cpu has much more gates than chipset and has more exactly time restric .If anyone have such experience pls pm me.

ASIC

Joined: 18 May 2001
Posts: 221

05 Jul 2002 16:23

Ace-X, just because you can't do it, doesn't mean that yechen can't. [Sorry Ace-X, I take back some of my words, it was not meant in a bad way]

Also, most DSPs, like the TI 6000 series are WLIW, and TI C compilers are actually available and working today. Finally, if the chip is IA64 compatible, Borland or M$ would do the compiler. Yechen wouldn't have to bother Wink

yechen, The verilog code for the Sun UltraSparc IIe CPU is available for free download at Sun's web-site. Also, you may want to look at the Leon CPU. It's HDL source is also available for free. Both CPUs are done using HDL and both come with $ynop$ys DC scripts. No DW though Smile

As for CPU architecture, I am not familiar with the IA64, but wasn't it Intel's idea to get rid of the x86 code translation altogether? Without this piece of junk, the CPU would be only half the size, use maybe 20% the steps in the pipeline and consume 1/4 the power? From what I see, a WLIW processor will be much simpler to build than the x86.

Maybe you can point me in the direction of some IA64 datasheets?

Finally, wouldn't Intel sue your ass off, if you made a clone IA64?

ASIC

Last edited by ASIC on 07 Jul 2002 15:05; edited 1 time in total

zhoury

Joined: 25 Apr 2002
Posts: 27

06 Jul 2002 1:56

Thanks asic. I will be glad to think through sun's cpu .
BTW anyone can point some best tool to design cpu ? If i buy i will share with everybody here.

ntxp

Joined: 29 May 2002
Posts: 57

06 Jul 2002 3:01

As Sparc CPU comes with Verilog RTL, I thought such CPU could be designed using DC, however, if you need to design something more dense and packed as a clone of IA64, some macros may need custom designed, and means it will come back to schematic and primitive layout editor, so if I need to start the project, I would use the conventional tools such as DC, Cadence and Avant (oh.. it is SNPS now).

Another good commercial example of VLIW is Trimedia, Philips has the compiler built and I know at least one Trimedia clone which is designed by a Pakistan company (not rocket technology), it just makes the clone and the user need to use the Trimedia's compiling tools, so likewise, no one need to worry about the software unless u want to roll out your brand new VLIW.

BTW, you may find the following books interesting when designing the architecture of your clone:
Computer Architecture - a Quantitative Approach (3rd Edition)
The Design of Complex Embedded Systems

Cool Project!

ntxp.

zhoury

Joined: 25 Apr 2002
Posts: 27

06 Jul 2002 13:27

Now i am just wondering for designing macro .Does there any commercial tool for design .
BTW we are not clone IA64.

Ace-X

Joined: 25 Jan 2002
Posts: 590
Helped: 26

06 Jul 2002 13:29

Just to clear situation:
-------------------------
I told not about the problems with compilers for IA64 - any compiler for x86 will work OK, but about its internal structure - the part of IA64 works as a compiler, which translate x86 commands to internal VLIW (EPIC) representation! This one part is the most complicated part of IA64 processor!

Concern to TriMedia, MediaEngine, TI and others - all of these processors are DSP, or, to be more close to our topic - they are SIMD (Single Instruction Multiple Data) - that's the natural way to get the profit of VLIW architecture without over-complicated compiler. But I told about compilers for general-purpose VLIW processors! Again, do you know why there is no pure VLIW general-purpose processors (except, Multiflow - but this company disappeared from market)? Anyway, I provided this example with compiler just to explain how complicated is the nature of IA64. Give a look at this URL to clear it: http://developer.intel.com/design/itanium/idfisa/index.htm

So, my advice is to start not with IA64, but with any other architecture. IA64 is the worst choice for novices in processor design (as far as I realized, that's the first experience of yechen with processor design).

And ntxp is right - you'd better start with this nice book from David Patterson and John Hennessy:
http://www.amazon.com/exec/obidos/ASIN/1558605967/qid=1025958103/sr=8-1/ref=sr_8_1/104-0586871-8110369
It will give you some ideas about the architecture details of modern uP.

With best wishes,

Ace-X.

dainis

Joined: 15 May 2001
Posts: 1451
Helped: 56

06 Jul 2002 17:59

Look:
h**p://w*w.f-cpu.org/
h**p://w*w.fpgacpu.org/links.html

ntxp

Joined: 29 May 2002
Posts: 57

08 Jul 2002 3:55

Thank Ace-X for the good pointers.

I thought yechen is going to build another transmeta and it would be cool to have such a dream.

Come back to reality, I agree that IA64 or even ISA compatible to it (not to even mention the performance compatibility) is a piece of big job. If yechen is really interested in doing this project, I think you should gather a group of people to do it like the f-cpu, otherwise Ace-X's projection of 20 years on this task is overly optimistic.

Great dream anyway,

ntxp

zhoury

Joined: 25 Apr 2002
Posts: 27

08 Jul 2002 14:25

Thanks above everyone.
Yes we have much people doing this project.And i am charging EDA for this project. So i am much interested in such asic design flow. Say truely i am not worried about the IA64 architecture complexity.We have great man for design this. The compiler question is too. Now i just wonder what is special for design cpu and design normal digital circuit.I mean design flow and eda tools.
We are not cloning IA64 . We are just want to design a IA64 compatibal cpu.Performance maybe not match up.It's startup.For us compatibal is much important.

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farmerwang

Joined: 29 May 2002
Posts: 60
Helped: 1

25 Jul 2002 5:02

I guess u must work for an academic orgnization. For a company who want earn some money from it's product will not choose such a project. CPU design is very complex, much than you can imagine, you will recognize this as your project advances. I strongly agress with ACE-x for some points. I had envovled in a CPU project for 3 years, it's a fully MIPS compatible embbed CPU, it took us 2 years before we can boot up WINCE GUI on our FPGA prototype. 3 re-spins take place before the core becomes stable. The bottleneck will be the verfication, not design(if u do not pursue a high clock frequency). I do think no company can afford such a project without a government background.