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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3 ... 245, 246, 247 ... 276, 277, 278  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2397	25 Mar 2007 8:41 klug
	have any one use pks to power reduce ?	1	haifengyuyun	90	02 Jul 2004 7:52 skymusic
	Mixed signal Verification	4	akp494	384	02 Jul 2004 5:10 akp494
	How to simulate & measure power consumption and current.	4	giggs11	312	02 Jul 2004 4:19 haifengyuyun
	OPENMORE excel spreadsheet	5	Beetroots	342	01 Jul 2004 23:50 Beetroots
	NC COV help	1	gold_kiss	612	01 Jul 2004 21:36 danny_isr
	how to find out fault coverage without scan (vectors only)	0	danny_isr	114	01 Jul 2004 20:02 danny_isr
	Suggest some books about amba	3	zwj_seu	249	01 Jul 2004 15:39 jamesyang1209
	SRL,ROR,... operator in VHDL	10	roger	1548	01 Jul 2004 14:54 radix
	Selective Shutdown in GALS processors	0	arunragavan	75	01 Jul 2004 10:45 arunragavan
	general purpose microprocessor + DSP solution ?	17	eexuke	693	01 Jul 2004 4:43 jamesyang1209
	what's different between Floorplan Compiler and JupiterXT?	4	Wang Chin	515	30 Jun 2004 16:57 Vasily
	help on HDLScore	1	gold_kiss	144	30 Jun 2004 4:11 z81203
	digital back-end design (gate-level netlist to GDSII)	0	eexuke	174	29 Jun 2004 7:00 eexuke
	where can i find the solution	0	westlife	183	29 Jun 2004 4:50 westlife
	Floorplan Compiler	7	mike_6281	993	26 Jun 2004 4:59 wadaye
	which is best nlint tools?	8	xworld2008	459	26 Jun 2004 4:14 wadaye
	Will Specman die for Vera as Borland die for Micro$oft?	11	sweesw	714	26 Jun 2004 3:21 zwj_seu
	Janick Bergeron was sold to Designware	5	sweesw	378	25 Jun 2004 20:02 efundas
	Netlist Simulations - Interview question	16	gold_kiss	822	25 Jun 2004 19:43 efundas
	who know how many transistors are in arm7tdmi core?	4	dada1019	216	25 Jun 2004 7:29 gerade
	C(at)dence IC443	0	wpwang	129	25 Jun 2004 7:26 wpwang
	Clock Synthesis with Synopsys DC	7	giggs11	498	24 Jun 2004 7:38 sandusty
	[REQ] User manual for @HDL, RealIntent, Cadence PSL tool	0	saho	339	22 Jun 2004 23:43 saho
	[REQ]TransEDA VN-SPEC user manual	0	saho	96	22 Jun 2004 23:40 saho
	Req: Nedd Magma Workshop or hand on training doc	0	kbulusu	216	22 Jun 2004 12:48 kbulusu
	DFT Tutorial	10	rakko	2038	21 Jun 2004 7:58 crek hardman
	what is the MCP?	3	dada1019	171	21 Jun 2004 1:24 eda_wiz
	Timing Analysis of Post Layout designs...	2	giggs11	264	20 Jun 2004 9:29 linuxluo
	How does STA specify the buffering...?	1	giggs11	132	20 Jun 2004 9:26 linuxluo
	how to dump very long time simulation in modelsim VHDL?	5	roger	330	19 Jun 2004 17:07 roger
	Req: Post Synthesis Simulation tools	12	PigiPigi	1743	19 Jun 2004 9:31 Zerox100
	open-drain and push-pull in MMC	1	zwj_seu	264	18 Jun 2004 9:49 svicent
	can connect pad power ring and core power ring ?	16	rod_wu	1657	18 Jun 2004 9:45 sandusty
	Read external stimuli file in ModelSim...	4	massive	192	18 Jun 2004 6:46 gerade
	model of seamless	0	dada1019	99	17 Jun 2004 17:05 dada1019
	how to integrate flash, sram, eeprom and cpu on a silicon?	0	dada1019	69	17 Jun 2004 17:03 dada1019
	Can anyone provide Synthesis Checklist	5	ymli	357	17 Jun 2004 11:27 gerade
	Any tools to translate from VHDL to Verilog?	6	jamesyang1209	246	17 Jun 2004 7:07 spauls
	how to suppress warning in modelsim	2	roger	912	17 Jun 2004 3:56 roger
	Design Compiler: report_timing -delay min	0	anjf	135	16 Jun 2004 13:38 anjf

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