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ASIC Design Methodologies & Tools (Digital)


ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

tags: asic design, fpga asic, asic company, asic engineer, asic vlsi, asic vhdl, asic dsp, ,
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This topic is locked: you cannot edit posts or make replies. Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!
 0 klug 3858 25 Mar 2007 8:41
klug
No new posts full adder .. please help with checking the program
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OKcomputer6
No new posts Calibre LVS aborted "LVS INTERNAL ERROR MEM35 (CAPACITY
 3 asbag 129 06 Nov 2009 9:48
research235
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luwanzen
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 2 kiranks9 108 06 Nov 2009 8:20
luwanzen
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 1 shandabogo 105 06 Nov 2009 7:55
shandabogo
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 2 cherin 123 06 Nov 2009 6:33
arjun1110
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 2 arunkumar446 75 06 Nov 2009 5:50
arunkumar446
No new posts I want to know the ccs model
 0 devop 36 06 Nov 2009 4:25
devop
No new posts How to design 1 to 8 multiplier
 2 kunal1514 108 05 Nov 2009 19:09
cherin
No new posts who can share the "dft compiler1" lab guide ?
 1 asic_andrea 246 05 Nov 2009 18:23
2139
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 3 vamsi_addagada 174 05 Nov 2009 10:18
Mckey_eye
No new posts CCS timing model question
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devop
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 1 hzhang96 93 05 Nov 2009 5:06
ljxpjpjljx
No new posts What is calibre Query Server
 3 srpatel9 373 04 Nov 2009 22:20
pritter
No new posts symetric transparent mbist
 0 kalaraj27 18 04 Nov 2009 9:55
kalaraj27
No new posts Icarus Verilog (iverilog) help needed
 2 rockgird 129 04 Nov 2009 7:42
rockgird
No new posts Specman generate (for each in)
 2 loglong 114 04 Nov 2009 5:43
loglong
No new posts About Astro: How to insert a power-cut cell?
 0 cheat0821 39 04 Nov 2009 5:24
cheat0821
No new posts FastScan at speed test with occ
 0 ed168 69 04 Nov 2009 3:40
ed168
No new posts anyone have BSD compiler user guide??
 3 simplescalar 243 03 Nov 2009 15:00
dongdong209
No new posts does synopsys has library generation tool?????????/
 5 sudheerprasad 264 03 Nov 2009 10:28
srehan
No new posts How to design BCH ecc circuit . . .
 0 elone 54 03 Nov 2009 8:42
elone
No new posts 64x16 SRAM DESIGN- request for resources
 3 bvp_dir 195 03 Nov 2009 7:20
pini_1
No new posts free simple AHB monitor to debug the activity of the bus
 1 pini_1 114 03 Nov 2009 3:33
ljxpjpjljx
No new posts something about synthesis
 2 chibijia 216 03 Nov 2009 2:14
chibijia
No new posts Jitter (pvt sensitivity) of buffer line.
 0 JuliaJ 90 02 Nov 2009 21:42
JuliaJ
No new posts ncelab: *W,MISSYST ( fielname.v,264|21): Unrecognized system
 0 mmk23 57 02 Nov 2009 13:49
mmk23
No new posts vhdl: records for a bus of digital signals
 2 xlynx3 87 02 Nov 2009 12:38
xlynx3
No new posts net input transition calcuation
 0 devop 60 02 Nov 2009 8:51
devop
No new posts mentor graphics tools
 3 ksrinivasan 426 02 Nov 2009 5:06
Vijay.iyer12
No new posts $rise and $fell in assertions
 1 kunal1514 108 02 Nov 2009 5:05
ljxpjpjljx
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 10 hfooo1 465 01 Nov 2009 17:07
aliputa
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 5 pini_1 138 01 Nov 2009 17:00
aliputa
No new posts standard cell parameters ...
 0 shams mr 99 01 Nov 2009 16:37
shams mr
No new posts how does the ICC calculate the EM problems??
 1 devop 129 01 Nov 2009 16:34
aliputa
No new posts 8 bit to 32 bit data conversion
 5 anjo_ca 270 31 Oct 2009 22:02
bepobalote
No new posts what is Spare-cells ?where i can use those cells
 3 vamsi_addagada 285 31 Oct 2009 19:45
shelby
No new posts corner selection during dc synthesis
 1 zhonghan 105 31 Oct 2009 19:36
shelby
No new posts Flase_Path reports in DC/PT
 6 koppolu1981 201 31 Oct 2009 19:29
shelby
No new posts how to measure leakage current or leakage power using HSPICE
 0 zeroburn 102 31 Oct 2009 12:12
zeroburn
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