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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3 ... 193, 194, 195 ... 276, 277, 278  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2397	25 Mar 2007 8:41 klug
	How to Construct a SoC System?	0	Thomson	84	23 Oct 2005 4:37 Thomson
	about ethernet switch ic	0	chenny	114	22 Oct 2005 8:15 chenny
	SCAN based and Boundry Scan	4	nani_1981	282	21 Oct 2005 19:50 nani_1981
	reg: anyone working cadence SPW5?	2	eda_boy	186	21 Oct 2005 16:45 aravind
	how to write the below verilog code in vhdl	7	tarkyss	216	21 Oct 2005 16:44 aji_vlsi
	how to bind a primitive channel to a port in SystemC	1	omara007	255	21 Oct 2005 13:54 noorullam
	how to calculate the input slew rate of inverter?	3	wholx	204	21 Oct 2005 10:53 eda_wiz
	setup time violation	9	cutykat	1998	20 Oct 2005 20:29 sparc200
	[question] Most Helpful Skill Codes	9	Raptor	468	20 Oct 2005 20:27 sparc200
	q of cpld for 16:1 mux?	0	abhineet22	120	20 Oct 2005 12:46 abhineet22
	Propagation Delay	8	sathi.ec	315	20 Oct 2005 12:18 urgentor
	which tool can translate verilog to vhdl	1	tarkyss	180	20 Oct 2005 8:44 Kukaz
	A question about specman & vera	0	claymore	75	20 Oct 2005 4:17 claymore
	insert scan problem	12	ls000rhb	447	19 Oct 2005 21:59 sam31
	Best Async FIFO Implementation	2	davyzhu	246	19 Oct 2005 11:32 eeeraghu
	what is the meaning of "stub" in "stub series	1	albred	132	19 Oct 2005 9:03 nand_gates
	help needed on clock generation	5	Anil Rana	177	19 Oct 2005 7:48 Anil Rana
	Multipliers	1	jayna	159	19 Oct 2005 7:02 arunragavan
	How to translate Spice module to IBIS module?	2	congqingzm	201	19 Oct 2005 6:35 mmirmak
	Fault coverage in BIST circuit	1	crystal	165	19 Oct 2005 4:19 dr_dft
	Variable Rate Multiplexing?????	2	ahmed osama	153	18 Oct 2005 22:42 ahmed osama
	EDIF format, help me to find it's documents	3	loyalpious	129	18 Oct 2005 8:49 loyalpious
	Fault coverage in RTL code	2	aditya_vij	186	18 Oct 2005 6:53 AlexWan
	Scripts for EDA...	14	satya	1457	18 Oct 2005 4:27 flyingcar
	where can i get memory model(verilog) ?	13	xldu	537	18 Oct 2005 3:59 firendchn
	utilities of Astro----scheme2pdef	0	taoly	63	18 Oct 2005 3:45 taoly
	eco, metal change and IPO in P&R?	3	triquent	216	17 Oct 2005 13:32 oxford
	how to use virtual clock inDC	5	googlegzh	360	17 Oct 2005 13:09 oxford
	IO pads	10	sandysuhy	798	17 Oct 2005 13:05 oxford
	search USB2.0 OTG IC design expert at China.	0	ghis9t	111	17 Oct 2005 3:51 ghis9t
	Silicon ensemble solaris problem..	1	jelydonut	147	15 Oct 2005 19:00 gliss
	Unpredictable testbench behaviour in Modelsim	2	thirumoorthyg	114	15 Oct 2005 12:29 thirumoorthyg
	how to improve systemC simulation speed	2	noorullam	150	15 Oct 2005 5:14 noorullam
	a false path in striclty 1 clock syncronous rtl possible ?	4	kslim	153	14 Oct 2005 18:17 dr_dft
	about testbench automatically writer	16	nmtr	1385	14 Oct 2005 12:38 sp
	tcl compiler	1	mahk	138	14 Oct 2005 10:18 junchaoguo51888
	bus synchronization	6	omid219	312	14 Oct 2005 8:03 eeeraghu
	8-bit binary divider and solutons of rabaey-digital intg.ckt	0	harry_madaan	162	14 Oct 2005 7:02 harry_madaan
	Z state, Is it a software bug or a fault of the circuitry?	1	ywguo	105	14 Oct 2005 6:01 sandysuhy
	synthesis question on FSM, error on syntheis netlist!!	17	hgz	912	14 Oct 2005 5:49 hgz

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