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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3 ... 115, 116, 117 ... 266, 267, 268  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	2148	25 Mar 2007 9:41 klug
	PC3 6400.....................DDR SDRAM	0	Guru59	84	11 Feb 2007 9:30 Guru59
	Hold Time Fixing for MultiMode Design	0	rakesh_aadhimoolam	159	11 Feb 2007 6:05 rakesh_aadhimoolam
	Scan chain with neg edge and pos edge flops	8	shahal	432	10 Feb 2007 20:49 dft_guy
	Delta sigma ADC..	2	dineshbabumm	141	10 Feb 2007 14:50 gingerjiang
	traffic density control project help	0	sunilkumar53	45	10 Feb 2007 11:24 sunilkumar53
	Synthesizable verilog/VHDL differential/integral model	0	hdang	90	10 Feb 2007 2:25 hdang
	Can I use this Verilog style inside VHDL ?	5	omara007	87	09 Feb 2007 19:29 omara007
	IC packaging and routing	1	karthiktr	66	09 Feb 2007 16:42 servicemann
	Flip chip packaging	0	karthiktr	93	09 Feb 2007 16:31 karthiktr
	All Synopsys Tutorials	18	ee171	2049	09 Feb 2007 16:07 karthiktr
	Vlan Tag	1	ashgun	51	09 Feb 2007 14:23 ad3y
	any docs on USAGE of PERL language in VLSI field......	4	rakesh_aadhimoolam	276	09 Feb 2007 10:33 ram
	new to asic...	2	sivakumar_tumma	99	09 Feb 2007 9:09 satyakumar
	why not add buffer but lockup ??	12	leeguoxian	363	09 Feb 2007 7:34 dr_dft
	A problem on PLI for Verilog	4	eruisi	237	09 Feb 2007 4:40 aji_vlsi
	Define stick diagram	2	amara	156	08 Feb 2007 13:43 sivakumar_tumma
	diagram	0	sivakumar_tumma	93	08 Feb 2007 13:31 sivakumar_tumma
	Changing positions of MOSFETS in CMOS inverter	4	engrbabarmansoor	132	08 Feb 2007 13:22 sivakumar_tumma
	slow to fast clock domain .... is an asynch. fifo needed ???	4	subramanyam	138	08 Feb 2007 11:02 s3034585
	ASIC companies in PUNE	2	Gireesh	174	08 Feb 2007 10:01 sagarcoco
	regarding testbenches	2	mallikmarasu	132	08 Feb 2007 9:38 mssajwan
	Tracks of a standard cell.	2	pandit_vlsi	111	08 Feb 2007 8:23 p_shinde
	Request for Advanced STA Interview Questions	7	shahal	378	07 Feb 2007 21:32 kbulusu
	Plz post some gud material on recovery and removal time	1	subramanyam	75	07 Feb 2007 8:36 shahal
	Is it valid violation?	2	shelkerahul	102	07 Feb 2007 8:03 shelkerahul
	Who has vhdl 2002 specification document?	1	hustyw	57	07 Feb 2007 7:25 rameshsuthapalli
	Generating VCD with ncverilog	3	Aastik	654	07 Feb 2007 7:08 Aastik
	GSM baseband Power Consumbtion	0	alzomor	60	07 Feb 2007 3:40 alzomor
	GSM baseband Power Consumbtion	0	alzomor	60	07 Feb 2007 3:36 alzomor
	FIFO.................what is this ?	5	Guru59	168	07 Feb 2007 1:02 khaila
	sequence detector	2	mallikmarasu	120	06 Feb 2007 16:52 vinodkumar
	hold time violations	3	mallikmarasu	183	06 Feb 2007 15:32 tronix
	What exactly PIPELINE means..............	5	Guru59	204	06 Feb 2007 14:11 mathuranathan
	CLOCK DISTRIBUTION TOPOLOGIES	2	rakesh_aadhimoolam	228	06 Feb 2007 13:04 Guru59
	question about DFF	4	danda821	177	06 Feb 2007 9:13 wice
	a paper on Clock Skew and Short Paths Timing	0	subramanyam	177	06 Feb 2007 7:24 subramanyam
	regarding multi cycle path	3	mallikmarasu	114	06 Feb 2007 6:57 wice
	sram timing circuits	0	atul799	84	05 Feb 2007 18:05 atul799
	A paper on Ram Fault MOdels........	3	rakesh_aadhimoolam	96	05 Feb 2007 13:41 wice
	Top-bottom Synthesis methodology Paper from SNUG?	0	davyzhu	84	05 Feb 2007 11:34 davyzhu

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