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ASIC Design Methodologies & Tools (Digital)


ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions

tags: asic design, fpga asic, asic company, asic engineer, asic vlsi, asic vhdl, asic dsp, ,
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This topic is locked: you cannot edit posts or make replies. Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!
 0 klug 3858 25 Mar 2007 8:41
klug
No new posts material on logic synthesis and p&r
 3 ram_kumar_abc 255 13 Nov 2009 22:09
rohanhelio
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 4 amit.dounde 270 13 Nov 2009 21:39
rohanhelio
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 2 george100 138 13 Nov 2009 22:56
george100
No new posts What are the guidelines that we use while doing floorplan?
 1 kumar_eee 96 13 Nov 2009 19:51
oak_tree
No new posts Multi voltage and multi power mode design partitioning
 2 oak_tree 114 13 Nov 2009 19:44
oak_tree
No new posts Mentor FastScan Error: Illegal global condition is forced to
 0 ed168 39 13 Nov 2009 19:39
ed168
No new posts Verilog code wont simulate properly
 5 user_asic 138 13 Nov 2009 17:44
Syswip
No new posts regarding threshold voltage
 2 muraleepatro 75 13 Nov 2009 16:48
muraleepatro
No new posts digital asic design flow. flow is better? why?
 3 cosmosd 225 13 Nov 2009 13:59
Syswip
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 4 senddilu 267 13 Nov 2009 11:42
niravbhatt
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feel_on_on
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 1 sunlei 84 13 Nov 2009 8:06
rsqf
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 4 raju3295 201 13 Nov 2009 8:00
vikram789
No new posts power structure calculations
 0 sunilbezawada 66 13 Nov 2009 7:51
sunilbezawada
No new posts help with behavioral cache verilog coding
 2 deepa1206 111 12 Nov 2009 21:23
deepa1206
No new posts whats wrong
 2 Rajesh.P 99 12 Nov 2009 18:23
akshay mahajan
No new posts Mini UART verilog code
 4 Aircraft Maniac 814 12 Nov 2009 18:21
akshay mahajan
No new posts repository of vhdl memory models - link
 0 pini_1 69 12 Nov 2009 9:37
pini_1
No new posts Does Synopsys LEDA support commands like 'set_false_path'?
 5 wufei 153 12 Nov 2009 5:02
wufei
No new posts can fork/join be nested in systemverilog
 2 hzhang96 138 11 Nov 2009 15:37
Syswip
No new posts How to calculate the power stripes in encounter 10 points
 3 mujju433 207 11 Nov 2009 11:14
cop02ia
No new posts Time Borrowing in latches
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Kaushalkk
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 6 red_0220 258 11 Nov 2009 6:13
Kazzam
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 0 priyanani 66 11 Nov 2009 6:07
priyanani
No new posts Help me on power calculation on a circuit
 1 ramesh441 75 11 Nov 2009 6:06
koggestone
No new posts fifo depth question
 9 dazzling_deepika 830 11 Nov 2009 4:55
rakko
No new posts Circuit for Clock Divide by 5 and 50 % duty cycle (urgent)
 4 spartanthewarrior 501 11 Nov 2009 4:42
rakko
No new posts Meaning of these terms in semiconductor field
 2 vikram789 138 11 Nov 2009 4:55
koggestone
No new posts named capture procedure in tetramax?
 2 ed168 75 10 Nov 2009 18:03
ed168
No new posts FULL CUSTOM DESIGN - request for resources
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research235
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 7 jonyRoyal 342 10 Nov 2009 10:35
jonyRoyal
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 1 civ3 114 10 Nov 2009 6:08
sachin_kirdat
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No new posts Relation b/w Timing parameter(Tcq) & PVT(Process,Volt.,T
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No new posts Dual power supply digital design
 0 analog2003 81 09 Nov 2009 18:26
analog2003
No new posts Vhdl real vs Verilog real
 0 xlynx3 54 09 Nov 2009 14:11
xlynx3
No new posts Difference b/w Procedural and Concrent Assertions
 2 kunal1514 96 09 Nov 2009 11:37
nilgiri1
No new posts how does ASIC designer transfer to firmware designer??
 0 vickyma 42 09 Nov 2009 5:59
vickyma
No new posts DFT explanation basic nomenclature
 4 Riffi 345 08 Nov 2009 18:59
Riffi
No new posts HELP ME FOR verilog code for USB 3.0 AND STATIC TIME ANALYSI
 0 naresh naik 60 08 Nov 2009 17:38
naresh naik
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