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ASIC Design Methodologies & Tools (Digital) ASIC (Application Specific Integrated Circuit) design methodologies design tool (simulator, synthesis...) related questions Moderator: Super Moderators		Goto page Previous  1, 2, 3, ... 256, 257, 258  Next Jump to page:
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Topics		Replies	Author	Views	Last Post
	Announcement: ALL E-BOOKS HERE WILL BE DELETED!!! USERS WILL BE WARNED!!!	0	klug	1905	25 Mar 2007 9:41 klug
	vi a array	1	S.Nikhil	27	01 Jul 2008 11:08 MarcS
	gate level sim help	12	balasub	270	01 Jul 2008 10:41 balasub
	Can not see any waveform in Debussy	2	xie.qiang	57	01 Jul 2008 10:05 jonnajagadeesh
	Can Verdi open a netlist ?	1	omara007	51	01 Jul 2008 10:00 jonnajagadeesh
	Scan D Flip Flop	5	rinaishlene	120	01 Jul 2008 9:11 rinaishlene
	how i can convert the color image into gray image using vhd	5	manish12	75	01 Jul 2008 7:22 sajjadi335
	DC output file usage and the full name of these file	3	ljxpjpjljx	54	01 Jul 2008 7:14 ygggliu
	Verilog module hierarchy causing problems	0	ktsangop	51	30 Jun 2008 23:15 ktsangop
	AMIS Setup	1	brunokasimin	30	30 Jun 2008 17:32 hock
	is division operator synthesizable in this conditoin....?	4	Tan	81	30 Jun 2008 15:07 wkong_zhu
	A problem about sdf annotate in post-simulation	0	gonewithstone	33	30 Jun 2008 14:39 gonewithstone
	can LEC read svf file generated by DC	4	wkong_zhu	60	30 Jun 2008 14:35 papertiger
	power ring width	4	siva_7517	141	30 Jun 2008 14:16 wkong_zhu
	A problem for the explanation of +race=all in VCS help	2	gonewithstone	48	30 Jun 2008 13:41 gonewithstone
	Random packet generator!	2	test_out	228	30 Jun 2008 10:46 straw
	80MS/S 10bit 8channel A/D	4	aho1363	36	29 Jun 2008 9:08 FvM
	VHDL to VERILOG CONVERTION	2	leongch	96	28 Jun 2008 15:56 atena
	How to embed a VHDL entity to an analog simulator?	0	linan0827	33	28 Jun 2008 12:21 linan0827
	SATA Specification Needed	4	shobhitk	159	28 Jun 2008 11:29 ljxpjpjljx
	RC extraction in soc encounter	4	gopakumargnair	39	27 Jun 2008 15:54 vlsitechnology
	The simulation waveform	2	rinaishlene	66	27 Jun 2008 15:02 gliss
	Power Gating Switches	0	shiva_107	42	27 Jun 2008 12:49 shiva_107
	BFM Bus Functional Model	0	balu304	33	27 Jun 2008 10:50 balu304
	ATPG timing problem	1	binbin1994	51	27 Jun 2008 10:34 leeguoxian
	MIPS+MCU	3	jzhangsun	72	27 Jun 2008 10:16 sdwsh
	TMAX's questions	3	binbin1994	81	27 Jun 2008 10:13 sdwsh
	WHAT IS MEANT by 1-polymophism 2- wildcard 3- virtual task	1	THUNDERRr	51	27 Jun 2008 7:34 nand_gates
	Which divider is the fastest in FPGA implementation	1	wkong_zhu	60	27 Jun 2008 6:16 FvM
	FIFO depth calculation	19	ppallavi	922	27 Jun 2008 4:49 sp3
	What's Macro Padding in Astro?	2	hgby2209	39	27 Jun 2008 3:44 hgby2209
	65nm Macro Orientation	2	praneshcn	63	27 Jun 2008 2:50 wkong_zhu
	reset synchronizer	4	alam.tauqueer	90	27 Jun 2008 2:23 wkong_zhu
	Anyone has VCI standard??	0	hpinmax	21	26 Jun 2008 14:00 hpinmax
	Using Synopsys DesignWare StarIPs without coreTools	5	hpinmax	78	26 Jun 2008 11:02 hpinmax
	Constraints on output ports and something about AMBA	5	yangbay81983	57	26 Jun 2008 5:45 lakshman.ar
	Concept of Multi Layer Masks	0	sp3	24	26 Jun 2008 5:24 sp3
	dc DRC	1	ASIC_intl	60	25 Jun 2008 22:41 gliss
	Who are familiar with coding VHDl using Emacs	3	bigyellow	153	25 Jun 2008 21:20 omara007
	estimation of gate count	8	sp3	174	25 Jun 2008 15:48 shankarmit
	need ovm_svcb.pdf	0	THUNDERRr	42	25 Jun 2008 14:51 THUNDERRr

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